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TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
D D D D D D D
Organization - TM4EN64xPU-xx . . . 4 194304 x 64 Bits - TM8EN64xPU-xx . . . 8388608 x 64 Bits Single 3.3-V Power Supply (10% Tolerance) JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket TM4EN64xPU-xx -- Utilizes Four 64M-Bit High-Speed (4M x 16-Bit) Dynamic RAMs TM8EN64xPU-xx -- Utilizes Eight 64M-Bit High-Speed (4M x 16-Bit) Dynamic RAMs High-Speed, Low-Noise LVTTL Interface High-Reliability 50-Lead 400-Mil-Wide Surface-Mount Thin Small-Outline Package (TSOP) (DGE Suffix)
D D D D D D D
Long Refresh Periods: - TMxEN64KPU: 64 ms (4 096 Cycles) - TMxEN64NPU: 64 ms (8192 Cycles) 3-State Output Extended-Data-Out (EDO) Operation With CAS-Before-RAS (CBR), RAS-Only, and Hidden Refresh Serial-Presence-Detect (SPD) Using EEPROM Ambient Temperature Range 0C to 70C Gold-Plated Contacts Performance Ranges
ACCESS TIME tRAC (MAX) 'xEN64xPU-40 40 ns 'xEN64xPU-50 50 ns 'xEN64xPU-60 60 ns ACCESS ACCESS EDO TIME TIME CYCLE tCAC tAA tHPC (MAX) (MAX) (MIN) 11 ns 20 ns 16 ns 13 ns 25 ns 20 ns 15 ns 30 ns 25 ns
description
The TM4EN64KPU is a 32M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of four TMS465169, 4 194 304 x 16-bit 4K-refresh EDO dynamic random-access memory (DRAM) devices, each in a 400-mil, 50-pin plastic thin small-outline package (TSOP) (DGE suffix) mounted on a substrate with decoupling capacitors. See the TMS465169 data sheet (literature number SMHS566). The TM4EN64NPU is a 32M-byte, 168-pin DIMM. The DIMM is composed of four TMS464169, 4 194 304 x 16-bit 8K-refresh EDO DRAMs, each in a 400-mil, 50-pin plastic TSOP (DGE suffix) mounted on a substrate with decoupling capacitors. See the TMS464169 data sheet (literature number SMHS566). The TM8EN64KPU is a 64M-byte ,168-pin DIMM. The DIMM is composed of eight TMS465169, 41934304 x 16-bit 4K-refresh EDO DRAMs, each in a 400-mil, 50-pin plastic TSOP (DGE suffix) mounted on a substrate with decoupling capacitors. See the TMS465169 data sheet (literature number SMHS566). The TM8EN64NPU is a 64M-byte ,168-pin DIMM. The DIMM is composed of eight TMS464169, 41934304 x 16-bit 8K-refresh EDO DRAMs, each in a 400-mil, 50-pin plastic TSOP (DGE suffix) mounted on a substrate with decoupling capacitors. See the TMS464169 data sheet (literature number SMHS566).
operation
The TM4EN64xPU operates as four TMS46x169s that are connected as shown in the TM4EN64xPU functional block diagram. The TM8EN64xPU operates as 18 TMS46x169s that are connected as shown in the TM8EN64xPU functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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1
PRODUCT PREVIEW
TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
DUAL-IN-LINE MEMORY MODULE ( TOP VIEW )
TM4EN64xPU ( SIDE VIEW )
TM8EN64xPU ( SIDE VIEW )
PIN NOMENCLATURE - TMxEN64KPU A[0:11] A[0:9] DQ[0:63] CAS[0:7] RAS[0:3] WE0 and WE2 OE0 and OE2 SA[0:2] SDA SCL NC VDD VSS Row Address Inputs Column Address Inputs Data In / Data Out Column-Address Strobe Row-Address Strobe Write Enable Output Enable Serial-Presence-Detect (SPD) Device Add Input Serial PD Address / Data Serial PD Clock No-Connect Pin 3.3-V Supply Ground
1
10 11
PIN NOMENCLATURE - TMxEN64NPU A[0:12] A[0:8] DQ[0:63] CAS[0:7] RAS[0:3] WE0 and WE2 OE0 and OE2 SA[0:2] SDA SCL NC VDD VSS Row Address Inputs Column Address Inputs Data In / Data Out Column-Address Strobe Row-Address Strobe Write Enable Output Enable Serial-Presence-Detect (SPD) Device Add Input Serial PD Address / Data Serial PD Clock No-Connect Pin 3.3-V Supply Ground
PRODUCT PREVIEW
40
41
84
2
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AAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AA A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA A AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAA A AA AA A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAA
NO. 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1 PIN NAME RAS0 CAS1 CAS0 DQ15 VDD DQ14 DQ13 DQ12 DQ10 DQ11 VDD WE0 VDD NC VDD DQ4 VSS DQ9 DQ8 DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 VSS DQ0 VSS A0 OE0 VSS NC A12 A10 NC NC NC NC A8 A6 A4 A2 NO. 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 PIN NAME
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Pin Assignments
DQ31
DQ30
DQ29
VDD DQ28
DQ27
DQ26
DQ25
VSS DQ24
DQ17
VSS DQ16
CAS3
CAS2
RAS2
WE2
VDD NC
VSS OE2
NC
NC
NC
TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
NO.
98
97
96
95
94
93
92
91
90
89
88
87
86
85
PIN NAME
DQ42
VSS DQ41
DQ40
DQ39
DQ38
DQ37
VDD DQ36
DQ35
DQ34
DQ33
VSS DQ32
NO.
140
VSS 139AAAAAA DQ48
138
137
136
135
134
133
132
131
130AAAAAA CAS6
129
128
127
PIN NAME
DQ49
CAS7
RAS3
SMMS692 - AUGUST 1997
VDD NC
VSS NC
NC
NC
NC
NC
PRODUCT PREVIEW
DQ23
DQ22
VSS DQ21
VDD DQ20
DQ19
DQ18
VDD
SDA
VSS NC
SCL
NC
NC
NC
NC
NC
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126 125 124 123 122 121 120 109 108 107 106 105 104 103 102 101 100 119 118 117 116 115 114 113 112 110 111 99 RAS1 CAS5 CAS4 DQ47 VDD DQ46 DQ45 DQ44 DQ43 VDD NC VDD NC VSS A1 VSS NC A11 NC NC NC NC NC NC A9 A7 A5 A3 168 167 166 165 164 163 162 161 160 159 158 157 156AAAAAA DQ59 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 DQ63 DQ62 DQ61 VDD DQ60 DQ58 DQ57 VSS DQ56 DQ55 DQ54 VSS DQ53 VDD DQ52 DQ51 DQ50 VDD VSS NC SA2 SA1 SA0 NC NC NC NC
3
TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
dual-in-line memory module and components
The dual-in-line memory module and components include:
D D D
PC substrate: 1,27
" 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Table 1. Component Table
Module TM4EN64xPU TM8EN64xPU Devices Used U[0:3] U[0:3], UB[0:3]
Bypass capacitors: Multilayer ceramic Contact area: Nickel plate and gold plate over copper
functional block diagram for the TMxEN64xPU
RAS0 WE0 OE0 RAS1 RAS2 WE2 OE2 CS W RAS LCAS DQ[0:7] U2 CAS5 DQ[40:47] UCAS DQ[8:15] CS W RAS LCAS DQ[0:7] U3 UCAS DQ[8:15] RAS3
PRODUCT PREVIEW
CAS0 DQ[0:7] CAS1 DQ[8:15]
CS W RAS LCAS DQ[0:7] U0 UCAS DQ[8:15] CS W RAS LCAS DQ[0:7] U1 UCAS DQ[8:15]
CS W RAS LCAS DQ[0:7] UB0 UCAS DQ[8:15] CS W RAS LCAS DQ[0:7] UB1 UCAS DQ[8:15]
CAS4 DQ[32:39]
CS W RAS LCAS DQ[0:7] UB2 UCAS DQ[8:15] CS W RAS LCAS DQ[0:7] UB3 UCAS DQ[8:15]
CAS2 DQ[16:23] CAS3 DQ[24:31]
CAS6 DQ[48:55] CAS7 DQ[56:63]
A[0:12]
A[0:12] : U[0:3], UB[0:3] SCL
SPD EEPROM SDA A0 A1 A2
LEGEND: SPD = Serial Presence Detect CS = Chip Select
SA0 SA1 SA2
A12 is not used in TM4EN64KPU, TM8EN64KPU
4
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TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM4EN64xPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 W TM8EN64xPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
VIL TA
Low-level input voltage Ambient temperature
- 0.3 0
0.8 70
V
C
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PRODUCT PREVIEW
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MIN 3 2 NOM MAX UNIT V V V V VDD VSS Supply voltage Supply voltage 3.3 0 3.6 VIH VIH-SPD High-level input voltage High-level input voltage for the SPD device 2AAA VDD + 0.3 5.5
recommended operating conditions
TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted)
TM4EN64KPU
PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Average read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA IOL = 100 A LVTTL LVCMOS LVTTL LVCMOS '4EN64KPU-40 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '4EN64KPU-50 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '4EN64KPU-60 MIN 2.4 V VDD - 0.2 0.4 V 0.2 10 10 A A MAX UNIT
VOH
VOL II IO
VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VO = 0 V to VDD,
ICC1
VDD = 3.6 V,
Minimum cycle
640
520
440
mA
PRODUCT PREVIEW
ICC2
Average g standby current
VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) VDD = 3.6 V, RASx low, tHPC = MIN, CASx cycling
4
4
4
mA
2
2
2
mA
ICC3
Average refresh current (RASx-only refresh or CBR) Average EDO current Average CBR refresh current
640
520
440
mA
ICC4 ICC5
600
480
400
mA
VDD = 3.6 V, Minimum cycle, RASx low after CASx low
640
520
440
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RASx = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
6
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TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued)
TM4EN64NPU
PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Average read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA IOL = 100 A LVTTL LVCMOS LVTTL LVCMOS '4EN64NPU-40 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '4EN64NPU-50 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '4EN64NPU-60 MIN 2.4 V VDD - 0.2 0.4 V 0.2 10 10 A A MAX UNIT
VOH
VOL II IO
VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VO = 0 V to VDD,
ICC1
VDD = 3.6 V,
Minimum cycle
540
440
400
mA
ICC2
Average g standby current
VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) VDD = 3.6 V, RASx low, tHPC = MIN, CASx cycling
4
4
4
mA
2
2
2
mA
ICC3
Average refresh current (RAS-only refresh or CBR) Average EDO current Average CBR refresh current
540
440
400
mA
ICC4 ICC5
560
440
360
mA
VDD = 3.6 V, Minimum cycle, RASx low after CASx low
640
520
440
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RASx = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
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PRODUCT PREVIEW
TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued)
TM8EN64KPU
PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Average read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA IOL = 100 A LVTTL LVCMOS LVTTL LVCMOS '8EN64KPU-40 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '8EN64KPU-50 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '8EN64KPU-60 MIN 2.4 V VDD - 0.2 0.4 V 0.2 10 10 A A MAX UNIT
VOH
VOL II IO
VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VO = 0 V to VDD,
ICC1
VDD = 3.6 V,
Minimum cycle
644
524
444
mA
PRODUCT PREVIEW
ICC2
Average g standby current
VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) VDD = 3.6 V, RASx low, tHPC = MIN, CASx cycling
4
4
4
mA
2
2
2
mA
ICC3
Average refresh current (RAS-only refresh or CBR) Average EDO current Average CBR refresh current
644
524
444
mA
ICC4 ICC5
604
484
404
mA
VDD = 3.6 V, Minimum cycle, RASx low after CASx low
640
520
440
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RASx = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
8
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TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued)
TM8EN64NPU
PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Average read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA IOL = 100 A LVTTL LVCMOS LVTTL LVCMOS '8EN64NPU-40 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '8EN64NPU-50 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '8EN64NPU-60 MIN 2.4 V VDD - 0.2 0.4 V 0.2 10 10 A A MAX UNIT
VOH
VOL II IO
VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VO = 0 V to VDD,
ICC1
VDD = 3.6 V,
Minimum cycle
544
444
404
mA
ICC2
Average g standby current
VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) VDD = 3.6 V, RASx low, tHPC = MIN, CASx cycling
4
4
4
mA
2
2
2
mA
ICC3
Average refresh current (RAS-only refresh or CBR) Average EDO current Average CBR refresh current
544
444
404
mA
ICC4 ICC5
560
440
360
mA
VDD = 3.6 V, Minimum cycle, RASx low after CASx low
640
520
440
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RASx = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
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PRODUCT PREVIEW
TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)
PARAMETER Ci(A) Ci(OE) Ci(CAS) Ci(RAS) Ci(W) Co Ci/o(SDA) Ci(SPD) Input capacitance, A0 - A12 Input capacitance, OEx Input capacitance, CASx Input capacitance, RASx Input capacitance, WEx Output capacitance Input/output capacitance, SDA input Input capacitance,SA0,SA1,SA2,SCL inputs '4EN64xPU MIN MAX 22 30 9 30 30 9 9 7 '8EN64xPU MIN MAX 42 58 16 30 58 16 9 7 UNIT pF pF pF pF pF pF pF pF
NOTE 2: VDD = NOM supply voltage 10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 3)
PRODUCT PREVIEW
PARAMETER tAA tCAC tCPA tRAC tOEA tCLZ tOEZ tREZ tCEZ tWEZ Access time from column address (see Note 4) Access time from CASx (see Note 4) Access time from CASx precharge (see Note 4) Access time from RASx (see Note 4) Access time from OEx (see Note 4) Delay time, CASx to output in low-impedance state Output buffer turn off delay from OEx (see Note 5) Output buffer turn off delay from RASx (see Note 5) Output buffer turn off delay from CASx (see Note 5) Output buffer turn off delay from WEx (see Note 5)
'xEN64xPU-40 MIN MAX 20 11 22 40 11 0 3 3 3 3 11 11 11 11
'xEN64xPU-50 MIN MAX 25 13 28 50 13 0 3 3 3 3 13 13 13 13
'xEN64xPU-60 MIN MAX 30 15 35 60 15 0 3 3 3 3 15 15 15 15
UNIT ns ns ns ns ns ns ns ns ns ns
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 4. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V. 5. The MAX specifications of tREZ, tCEZ, tWEZ, and tOEZ are specified when the outputs are no longer driven. Data-in should not be driven until one of the applicable maximum values is satisfied.
EDO timing requirements
'xEN64xPU-40 MIN tHPC tPRWC tCSH tCHO tDOH tCAS tWPE tCP tOCH tOEP Cycle time, EDO page mode, read-write Cycle time, EDO read-write Delay time, RASx active to CASx precharge Hold time, OEx from CASx Hold time, output from CASx Pulse duration, CASx active (see Pulse duration, WEx active (output disable only) Pulse duration, CASx precharge Setup time, OEx before CASx Precharge time, OEx 16 47 32 5 5 6 5 6 5 5 10 000 MAX 'xEN64xPU-50 MIN 20 57 40 5 5 8 5 8 5 5 10 000 MAX 'xEN64xPU-60 MIN 25 68 48 5 5 10 5 10 5 5 10 000 MAX UNIT ns ns ns ns ns ns ns ns ns ns
10
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* HOUSTON, TEXAS 77251-1443
TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
ac timing requirements (see Note 3)
'xEN64xPU-40 MIN tRC tRWC tRASP tRAS tRP tWP tASC tASR tDS tRCS tCWL tRWL tWCS tWRP tCSR tCAH tDH tRAH tRCH tRRH tWCH tRHCP tOEH tROH tWRH tCHS tAWD tCHR tCRP tCWD tOED tRAD tRAL Cycle time, read Cycle time, read-write Pulse duration, RASx active, page mode (see Note 6) Pulse duration, RASx active, nonpage mode (see Note 6) Pulse duration, RASx precharge Pulse duration, write command Setup time, column address Setup time, row address Setup time, data in (see Note 7) Setup time, read command Setup time, write command before CASx precharge Setup time, write command before RASx precharge Setup time, write command before CASx active (early-write only) Setup time, write before RASx active (CBR refresh only) Setup time, CASx referenced to RASx ( CBR refresh only ) Hold time, column address Hold time, data in (see Note 7) Hold time, row address Hold time, read command referenced to CASx (see Note 8) Hold time, read command referenced to RASx (see Note 8) Hold time, write command during CASx active ( early-write only ) Hold time, RASx active from CASx precharge Hold time, OEx command Hold time, RASx referenced to OEx Hold time, write after RASx active (CBR refresh only) Hold time, CASx active after RASx precharge ( self-refresh) Delay time, column address to write command ( read-write only ) Delay time, CASx referenced to RASx ( CBR refresh only ) Delay time, CASx precharge to RASx Delay time, CASx to write command ( read-write operation only ) Delay time, OEx to data in Delay time, RASx to column address (see Note 9) Delay time, column address to RASx precharge 69 92 40 100 000 40 25 6 0 0 0 0 6 6 0 5 5 6 6 6 0 0 6 22 11 6 6 - 50 35 6 5 26 11 8 20 12 20 10 000 MAX 'xEN64xPU-50 MIN 84 111 50 100 000 50 30 8 0 0 0 0 8 8 0 5 5 8 8 8 0 0 8 28 13 8 8 - 50 42 8 5 30 13 10 25 15 25 10 000 MAX 'xEN64xPU-60 MIN 104 135 60 100 000 60 40 10 0 0 0 0 10 10 0 5 5 10 10 10 0 0 10 35 15 10 10 - 50 49 10 5 34 15 12 30 18 30 10 000 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCAL Delay time, column address to CASx precharge NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 6. In a read-write cycle, tRWD and tRWL must be observed. 7. Referenced to the later of CASx or WEx in write operations 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. The maximum value is specified only to assure access time.
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11
PRODUCT PREVIEW
TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
ac timing requirements (see Note 3) (continued)
'xEN64xPU-40 MIN tRCD tRPC tRSH tRWD tCPW tRASS tRPS tREF Delay time, RASx to CASx ( see Note 9) Delay time, RASx precharge to CASx Delay time, CASx active to RASx precharge Delay time, RASx active to write command (read-write only) Delay time, CASx precharge to write command (read-write only) Pulse duration, RASx active, self-refresh (see Note 10) Pulse duration, RASx precharge after self-refresh Refresh time interval 10 5 6 55 37 100 70 64 MAX 29 'xEN64xPU-70 MIN 12 5 8 67 45 100 90 64 MAX 37 'xEN64xPU-60 MIN 14 5 10 79 54 100 110 64 MAX 45 UNIT ns ns ns ns ns s ns ms
tT Transition time 1 50 1 50 1 50 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 9. The maximum value is specified only to ensure access time. 10. During the period of 10 s tRASS 100 s, the device is in transition state from normal operational mode to self-refresh mode.
PRODUCT PREVIEW
12
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* HOUSTON, TEXAS 77251-1443
TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
serial presence detect
The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, DRAM organization, and timing parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. Tables in this section list the SPD contents as follows: Table 2 --TM4EN64KPU Table 4--TM8EN64KPU Table 3-- TM4EN64NPU Table 5--TM8EN64NPU
Table 2. Serial-Presence-Detect Data for the TM4EN64KPU
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module DIMM configuration type (non-parity, parity, ECC) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E LVTTL tRAC = 40 ns tCAC = 11 ns Non-parity 15.6 s x16 N/A Rev. 1 38 97h '4EN64KPU-40 ITEM 128 bytes DATA 80h '4EN64KPU-50 ITEM 128 bytes DATA 80h '4EN64KPU-60 ITEM 128 bytes DATA 80h
1 2 3 4 5 6 7 8 9 10 11 12 13 14 62 63 64-71
256 bytes EDO 12 10 1 bank 64 bits
08h 02h 0Ch 0Ah 01h 40h 00h 01h 28h 0Bh 00h 00h 10h 00h 01h 26h 9700...00h
256 bytes EDO 12 10 1 bank 64 bits
08h 02h 0Ch 0Ah 01h 40h 00h
256 bytes EDO 12 10 1 bank 64 bits
08h 02h 0Ch 0Ah 01h 40h 00h
LVTTL tRAC = 50 ns tCAC = 13 ns Non-parity 15.6 s x16 N/A Rev. 1 50 97h
01h 32h 0Dh 00h 00h 10h 00h 01h 32h 9700...00h
LVTTL tRAC = 60 ns tCAC = 15 ns Non-parity 15.6 s x16 N/A Rev. 1 62 97h
01h 3Ch 0Fh 00h 00h 10h 00h 01h 3Eh 9700...00h
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PRODUCT PREVIEW
TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
serial presence detect (continued)
Table 2. Serial-Presence-Detect Data for the TM4EN64KPU (Continued)
BYTE NO. 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166 FUNCTION DESCRIBED Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data '4EN64KPU-40 ITEM TBD TBD TBD TBD TBD TBD TBD TBD TBD DATA '4EN64KPU-50 ITEM TBD TBD TBD TBD TBD TBD TBD TBD TBD DATA '4EN64KPU-60 ITEM TBD TBD TBD TBD TBD TBD TBD TBD TBD DATA
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
PRODUCT PREVIEW
14
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TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
serial presence detect (continued)
Table 3. Serial-Presence-Detect Data for the TM4EN64NPU
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module DIMM configuration type (non-parity, parity, ECC) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data LVTTL tRAC = 40 ns tCAC = 11 ns Non-parity 15.6 s x16 N/A Rev. 1 38 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD '4EN64NPU-40 ITEM 128 bytes DATA 80h '4EN64NPU-50 ITEM 128 bytes DATA 80h '4EN64NPU-60 ITEM 128 bytes DATA 80h
1 2 3 4 5 6 7 8 9 10 11 12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
256 bytes EDO 13 9 1 bank 64 bits
08h 02h 0Dh 09h 01h 40h 00h 01h 28h 08h 00h 00h 10h 00h 01h 26h 9700...00h
256 bytes EDO 13 9 1 bank 64 bits
08h 02h 0Dh 09h 01h 40h 00h
256 bytes EDO 13 9 1 bank 64 bits
08h 02h 0Dh 09h 01h 40h 00h
LVTTL tRAC = 50 ns tCAC = 13 ns Non-parity 15.6 s x16 N/A Rev. 1 50 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 32h 0Dh 00h 00h 10h 00h 01h 32h 9700...00h
LVTTL tRAC = 60 ns tCAC = 15 ns Non-parity 15.6 s x16 N/A Rev. 1 62 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 00h 00h 10h 00h 01h 3Eh 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
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PRODUCT PREVIEW
TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
serial presence detect (continued)
Table 4. Serial-Presence-Detect Data for the TM8EN64KPU
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module DIMM configuration type (non-parity, parity, ECC) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data Open LVTTL tRAC = 40 ns tCAC = 11 ns Non-parity 15.6 s x16 N/A Rev. 1 39 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD '8EN64KPU-40 ITEM 128 bytes DATA 80h '8EN64KPU-50 ITEM 128 bytes DATA 80h '8EN64KPU-60 ITEM 128 bytes DATA 80h
1 2 3 4 5
256 bytes EDO 12 10 2 banks 64 bits
08h 02h 0Ch 0Ah 02h 40h 00h 01h 28h 0Bh 00h 00h 10h 00h 01h 27h 9700...00h
256 bytes EDO 12 10 2 banks 64 bits
08h 02h 0Ch 0Ah 02h 40h 00h
256 bytes EDO 12 10 2 banks 64 bits
08h 02h 0Ch 0Ah 02h 40h 00h
PRODUCT PREVIEW
6 7 8 9 10 11 12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166 167-255
LVTTL tRAC = 50 ns tCAC = 13 ns Non-parity 15.6 s x16 N/A Rev. 1 51 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 32h 0Dh 00h 00h 10h 00h 01h 33h 9700...00h
LVTTL tRAC = 60 ns tCAC = 15 ns Non-parity 15.6 s x16 N/A Rev. 1 63 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 00h 00h 10h 00h 01h 3Fh 9700...00h
TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
16
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TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
serial presence detect (continued)
Table 5. Serial-Presence-Detect Data for the TM8EN64NPU
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module DIMM configuration type (non-parity, parity, ECC) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data Open LVTTL tRAC = 40 ns tCAC = 11 ns Non-parity 15.6 s x16 N/A Rev. 1 39 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD '8EN64NPU-40 ITEM 128 bytes DATA 80h '8EN64NPU-50 ITEM 128 bytes DATA 80h '8EN64NPU-60 ITEM 128 bytes DATA 80h
1 2 3 4 5 6 7 8 9 10 11 12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166 167-255
256 bytes EDO 13 9 2 banks 64 bits
08h 02h 0Dh 09h 02h 40h 00h 01h 28h 0Bh 00h 00h 10h 00h 01h 27h 9700...00h
256 bytes EDO 13 9 2 banks 64 bits
08h 02h 0Dh 09h 02h 40h 00h
256 bytes EDO 13 9 2 banks 64 bits
08h 02h 0Dh 09h 02h 40h 00h
LVTTL tRAC = 50 ns tCAC = 13 ns Non-parity 15.6 s x16 N/A Rev. 1 51 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 32h 0Dh 00h 00h 10h 00h 01h 33h 9700...00h
LVTTL tRAC = 60 ns tCAC = 15 ns Non-parity 15.6 s x16 N/A Rev. 1 63 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 00h 00h 10h 00h 01h 3Fh 9700...00h
TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
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PRODUCT PREVIEW
TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
device symbolization (TM4EN64KPU illustrated)
TM4EN64KPU Unbuffered Key Position YY MM T -SS = = = =
-SS
YYMMT
3.3-V Voltage Key Position Year Code Month Code Assembly Site Code Speed Code
NOTE A: Location of symbolization may vary.
PRODUCT PREVIEW
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TM4EN64KPU, TM4EN64NPU 4194304 BY 64-BIT TM8EN64KPU, TM8EN64NPU 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS692 - AUGUST 1997
MECHANICAL DATA
BS (R-PDIM-N168) DUAL IN-LINE MEMORY MODULE
5.255 (133,48) 5.245 (133,22) Notch 0.157 (4,00) x 0.122 (3,10) Deep 2 Places
(Note D) Notch 0.079 (2,00) x 0.122 (3,10) Deep 2 Places 0.054 (1,37) 0.046 (1,17)
0.039 (1,00) TYP 0.125 (3,18) 0.118 (3,00) DIA 2 Places
0.050 (1,27) 0.125 (3,18)
0.014 (0,35) MAX
0.700 (17,78) TYP 1.130 (28,70) 1.120 (28,45) 0.106 (2,70) MAX 0.157 (4,00) MAX (For Double-Sided DIMM Only) 4088181/A 07/97
NOTES: A. B. C. D. E.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MO-161 Dimension includes de-panelization variations; applies between notch and tab edge. Outline may vary above notches to allow router/panelization irregularities.
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PRODUCT PREVIEW
0.118 (3,00) TYP
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Copyright (c) 1998, Texas Instruments Incorporated

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