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SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24
SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
EXTENDED COMMON-MODE RS-485 TRANSCEIVERS
FEATURES D Common-Mode Voltage Range (-20 V to 25 V)
More Than Doubles TIA/EIA-485 Requirement
DESCRIPTION
The transceivers in the HVD2x family offer performance far exceeding typical RS-485 devices. In addition to meeting all requirements of the TIA/EIA-485-A standard, the HVD2x family operates over an extended range of common-mode voltage, and has features such as high ESD protection, wide receiver hysteresis, and failsafe operation. This family of devices is ideally suited for long-cable networks, and other applications where the environment is too harsh for ordinary transceivers. These devices are designed for bidirectional data transmission on multipoint twisted-pair cables. Example applications are digital motor controllers, remote sensors and terminals, industrial process control, security stations, and environmental control systems. These devices combine a 3-state differential driver and a differential receiver, which operate from a single 5-V power supply. The driver differential outputs and the receiver differential inputs are connected internally to form a differential bus port that offers minimum loading to the bus. This port features an extended common-mode voltage range making the device suitable for multipoint applications over long cable runs.
D Reduced Unit-Load for Up to 256 Nodes D Bus I/O Protection to Over 16-kV HBM D Failsafe Receiver for Open-Circuit,
Short-Circuit and Idle-Bus Conditions
D Low Standby Supply Current 1-A Max D More Than 100 mV Receiver Hysteresis APPLICATIONS D Long Cable Solutions
- - - - - - Factory Automation Security Networks Building HVAC Electrical Power Inverters Industrial Drives Avionics
HVD2x APPLICATION SPACE
100
D Severe Electrical Environments
HVD2x Devices Operate Over a Wider Common-Mode Voltage Range
-20 V HVD23 HVD20 +25 V
Signaling Rate - Mbps
10 HVD24 HVD21
SUPER-485
RS-485
1 -7 V HVD22 -20 V -15 V -10 V -5 V 0 5V 10 V +12 V 15 V 20 V 25 V
0.1 10 100 Cable Length - m 1000
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
This document contains information on products in more than one phase of development. The status of each device is indicated on the page(s) specifying its electrical characteristics.
Copyright 2002 - 2003, Texas Instruments Incorporated
SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24
SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (continued)
The `HVD20 provides high signaling rate (up to 25 Mbps) for interconnecting networks of up to 64 nodes. The `HVD21 allows up to 256 connected nodes at moderate data rates (up to 5 Mbps). The driver output slew rate is controlled to provide reliable switching with shaped transitions which reduce high-frequency noise emissions. The `HVD22 has controlled driver output slew rate for low radiated noise in emission-sensitive applications and for improved signal quality with long stubs. Up to 256 `HVD22 nodes can be connected at signaling rates up to 500 kbps. The `HVD23 implements receiver equalization technology for improved jitter performance on differential bus applications with data rates up to 25 Mbps at cable lengths up to 160 meters. The `HVD24 implements receiver equalization technology for improved jitter performance on differential bus applications with data rates in the range of 1 Mbps to 10 Mbps at cable lengths up to 1000 meters. The receivers also include a failsafe circuit that will provide a high-level output within 250 microseconds after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or the absence of any active transmitters on the bus. This feature prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. The SN65HVD2X devices are characterized for operation over the temperature range of -40C to 85C.
PRODUCT SELECTION GUIDE
PART NUMBERS SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24 CABLE LENGTH AND SIGNALING RATE(1) Up to 50 m at 25 Mbps Up to 150 m at 5 Mbps (with slew rate limit) Up to1200 m at 500 kbps (with slew rate limit) Up to 160 m at 25 Mbps (with receiver equalization) Up to 500 m at 3 Mbps (with receiver equalization) NODES Up to 64 Up to 256 Up to 256 Up to 64 Up to 256 MARKING D: VP20 P: 65HVD20 D: VP21 P: 65HVD21 D: VP22 P: 65HVD22 D: VP23 P: 65HVD23 D: VP24 P: 65HVD24
(1) Distance and signaling rate predictions based upon Belden 3105A cable and 15% eye pattern jitter.
AVAILABLE OPTIONS
PLASTIC THROUGH-HOLE P-PACKAGE (JEDEC MS-001) SN65HVD20P SN65HVD21P SN65HVD22P SN65HVD23P SN65HVD24P PLASTIC SMALL-OUTLINE(1) D-PACKAGE (JEDEC MS-012) SN65HVD20D SN65HVD21D SN65HVD22D SN65HVD23D SN65HVD24D
(1) Add R suffix for taped and reeled carriers.
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SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24
SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
DRIVER FUNCTION TABLE
HVD20, HVD21, HVD22 INPUT D H L X X OPEN ENABLE DE H H L OPEN H OUTPUTS A H L Z Z H B L H Z Z L INPUT D H L X X OPEN HVD23, HVD24 ENABLE DE H H L OPEN H OUTPUTS A H L Z Z L B L H Z Z H
H = high level, L= low level, X = don't care, Z = high impedance (off), ? = indeterminate
RECEIVER FUNCTION TABLE
DIFFERENTIAL INPUT VID = (VA - VB) 0.2 V VID -0.2 V < VID < 0.2 V VID -0.2 V X X Open circuit Short Circuit ENABLE RE L L L H OPEN L L OUTPUT R H See Note A L Z Z H H
Idle (terminated) bus L H H = high level, L= low level, X = don't care, Z = high impedance (off), ? = indeterminate NOTE A: If the differential input VID remains within the indeterminate-logic range for more than 250 s, the integrated failsafe circuitry detects a bus fault, and set the receiver output to a high state. See Figure 15.
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SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24
SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
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POWER DISSIPATION RATINGS
PACKAGE D P CIRCUIT BOARD MODEL Low-K(1) High-K(2) Low-K(1) High-K(2) TA 25C POWER RATING 710 mW 1282 mW 984 mW 1478 mW DERATING FACTOR(3) ABOVE TA = 25C 5.68 mW/C 10.3 mW/C 7.87 mW/C 11.8 mW/C TA = 70C POWER RATING 455 mW 821 mW 630 mW 946 mW TA = 85C POWER RATING 370 mW 667 mW 512 mW 768 mW
(1) In accordance with the Low-K thermal metric definitions of EIA/JESD51-3. (2) In accordance with the High-K thermal metric definitions of EIA/JESD51-7. (3) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) SN65HVD2X Supply voltage(2), VCC Voltage at any bus I/O terminal Voltage input, transient pulse, A and B, (through 100 , see Figure 16) Voltage input at any D, DE or RE terminal Human Body Model(3) Electrostatic discharge Charged-Device Model(4) Machine Model(5) A, B, GND All pins All pins All pins -0.5 V to 7 V -27 V to 27 V -60 V to 60 V -0.5 V to VCC+ 0.5 V 16 kV 5 kV 1.5 kV 200 V See Power Dissipation Rating Table 150C -65C to 120C
Continuous total power dissipation Junction temperature, TJ Storage temperature, Tstg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. (3) Tested in accordance with JEDEC Standard 22, Test Method A114-A. (4) Tested in accordance with JEDEC Standard 22, Test Method C101. (5) Tested in accordance with JEDEC Standard 22, Test Method A115-A.
RECOMMENDED OPERATING CONDITIONS
MIN Supply voltage, VCC Voltage at any bus I/O terminal High-level input voltage, VIH Low-level input voltage, VIL Differential input voltage, VID Output current Operating free-air temperature, TA Junction temperature, TJ A, B D, DE, D DE RE A with respect to B Driver Receiver 4.5 -20 2 0 -25 -110 -8 -40 -40 NOM 5 MAX UNIT 5.5 25 VCC 0.8 25 110 8 85 125 mA C C V V V V
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SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24
SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)(1) PARAMETER VIK VO VOD(SS) |VOD(SS)| VOC(SS) VOC(SS) VOC(PP) VOD(RING) II IO(OFF) IOZ Input clamp voltage Open-circuit output voltage Steady-state Steady state differential output voltage magnitude Change in steady-state differential output voltage between logic states Steady-state common-mode output voltage Change in steady-state common-mode output voltage, VOC(H) - VOC(L) Peak-to-peak common-mode output voltage, VOC(MAX) - VOC(MIN) Differential output voltage over and under shoot Input current Output current with power off High impedance state output current TEST CONDITIONS II = -18 mA A or B, No load No load (open circuit) RL = 54 , See Figure 1 With common-mode loading, See Figure 2 See Figure 1 and Figure 3 See Figure 1 See Figure 1 and Figure 4 RL = 54 , CL = 50 pF, See Figure 1 and Figure 4 RL = 54 , CL = 50 pF, See Figure 5 D, DE VCC < = 2.5 V DE at 0 V VO = -20 V to 25 V, See Figure 9 -100 MIN TYP(1) -1.5 0 3.3 1.8 1.8 -0.1 2.1 -0.1 0.35 10% 100 A See receiver line in ut input current -250 See receiver CI 250 mA 2.5 0.1 2.9 0.1 V V V V 4.2 2.5 VCC VCC MAX UNIT V V V
IOS Short-circuit output current COD Differential output capacitance (1) All typical values are at VCC = 5 V and 25C.
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted) PARAMETER tPLH tPHL tr tf tPZH tPHZ tPZL tPLZ td(standby) td(wake) tsk(p) sk( ) Differential output propagation delay, low-to- high Differential output propagation delay, high-to-low Differential output rise time Differential output fall time Propagation delay time, high-impedance-to-high-level output Propagation delay time, high-level-output-to-high-impedance Propagation delay time, high-impedance-to-low-level output Propagation delay time, low-level-output-to-high-impedance Time from an active differential output to standby Wake-up time from standby to an active differential output Pulse skew | tPLH - tPHL | TEST CONDITIONS RL = 54 , CL = 50 pF pF, F, See Figure 3 RL = 54 , CL = 50 pF pF, F, See Figure 3 RE at 0 V, tV See Figure 6 g HVD20, HVD20 HVD23 HVD21, HVD21 HVD24 HVD22 HVD20, HVD20 HVD23 HVD21, HVD21 HVD24 HVD22 HVD20, HVD20 HVD23 HVD21, HVD21 HVD24 HVD22 HVD20, HVD20 HVD23 RE at 0 V, tV See Figure 7 g HVD21, HVD21 HVD24 HVD22 RE at VCC, See Figure 8 HVD20, HVD23 HVD21, HVD24 HVD22 (1) All typical values are at VCC = 5 V and 25C. MIN TYP(1) 6 20 160 2 20 200 10 32 280 6 40 400 MAX 20 60 500 12 60 600 40 100 300 40 100 300 2 8 2 6 50 ns s s ns ns ns ns UNIT
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SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24
SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
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RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions PARAMETER VIT(+) VIT(-) VHYS VIT(F ) IT(F+) VIT(F ) IT(F-) VIK VOH VOL Positive-going differential input voltage threshold Negative-going differential input voltage threshold Hysteresis voltage (VIT+ - VIT-) Positive going Positive-going differential in ut failsafe voltage input threshold Negative going Negative-going differential in ut failsafe voltage input threshold Input clamp voltage High-level output voltage Low-level output voltage See Figure 15 See Figure 15 VCM = -7 V to 12 V VCM = -20 V to 25 V VCM = -7 V to 12 V VCM = -20 V to 25 V TEST CONDITIONS See Figure 10 VO = 2.4 V, IO = -8 mA VO = 0.4 V, IO = 8 mA MIN TYP(1) 60 -200 100 40 40 -40 -40 -1.5 4 0.4 -400 -100 -800 -200 -100 24 96 20 500 125 1000 250 100 A k pF A -60 130 120 120 -120 -120 200 250 -200 -250 MAX 200 UNIT mV mV mV mV V V V
II = -18 mA VID = 200 mV, IOH = -8 mA, See Figure 11 VID = -200 mV, IOL = 8 mA, See Figure 11 VI = -7 to 12 V, 7 Other input = 0 V VI = -20 to 25 V, 20 Other input = 0 V HVD20, HVD23 HVD21, HVD22, HVD24 HVD20, HVD23 HVD21, HVD22, HVD24
II(BUS)
Bus input current (power on or power off)
II RI
Input current Input resistance
RE HVD20, 23 HVD21, 22, 24 VID = 0.5 + 0.4 sine (2 x 1.5 x 106t)
CID Differential input capacitance (1) All typical values are at 25C.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions PARAMETER tPLH tPHL tr tf tPZH tPHZ tPZL tPLZ tr(standby) tr(wake) tsk(p) tp(set) tp(reset) Propagation delay time, low-to-high level output Propagation delay time high to low level output time, high-to-low Receiver output rise time Receiver output fall time Receiver output enable time to high level Receiver output disable time from high level Receiver output enable time to low level Receiver output disable time from low level Time from an active receiver output to standby Wake-up time from standby to an active receiver output Pulse k P l skew | tPLH - tPHL | Delay time, bus fail to failsafe set Delay time, bus recovery to failsafe reset See Figure 14, DE at 0 V See Figure 11 See Figure 11 See Figure 12 See Figure 13 TEST CONDITIONS HVD20, HVD23 HVD21, HVD22 HVD21 HVD22, HVD24 MIN TYP 16 25 2 90 16 90 16 MAX 35 50 4 120 35 120 35 2 8 5 350 50 s ns s ns ns ns ns ns UNIT
See Figure 15 15,
pulse rate = 1 kHz
250
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SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24
SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
SUPPLY CURRENT
over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS HVD20 Driver enabled (DE at VCC), Receiver enabled (RE at 0 V) No load, VI = 0 V or VCC HVD21 HVD22 HVD23 HVD24 HVD20 Driver enabled (DE at VCC), Receiver disabled (RE at VCC) No load, VI = 0 V or VCC HVD21 HVD22 HVD23 HVD24 HVD20 Driver disabled (DE at 0 V), Receiver enabled (RE at 0 V) No load Driver disabled (DE at 0 V) Receiver disabled (RE at VCC) D open HVD21 HVD22 HVD23 HVD24 All HVD2x MIN TYP MAX 9 12 9 11 14 8 11 8 9 12 7 8 7 9 10 1 A mA mA mA UNIT
ICC
Supply current
RECEIVER EQUALIZATION CHARACTERISTICS
over recommended operating conditions PARAMETER TEST CONDITIONS 25 Mb s (attenuation similar Mbps to 160 m of Belden 3105A) Peak to eak Peak-to-peak eye-patttern jitter y j Pseudo-random NRZ code Pd d d with a bit pattern length of 216, See Figure 23 10 Mb s (attenuation similar Mbps to 250 m of Belden 3105A) 3 Mbps (attenuation similar to Mb s 500 m of Belden 3105A) 1 Mbps (attenuation similar to Mb s 1000 m of Belden 3105A) (1) The unit interval period, tui, is the inverse of the signaling rate. SN65HVD23 SN65HVD24 SN65HVD23 SN65HVD24 SN65HVD23 SN65HVD24 SN65HVD23 SN65HVD24 MIN TYP MAX 5% tui(1) N/A 5% tui 5% tui 15% tui 5% tui 25% tui 5% tui UNIT
tj( ) j(pp)
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SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24
SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
RE Inputs D Inputs (HVD20, 21, 22) VCC 100 k 1 k Input 9V 9V Input 100 k 1 k DE Input D Inputs (HVD23, 24) VCC
A Input VCC R1 Input 29 V R2 100 k 29 V
B Input VCC R1
100 k Input
R3
R3
R2
A and B Outputs VCC VCC
R Output
5 Output 29 V
Output 9V
HVD20, 23 HVD21, 22, 24
R1/R2 9 k 36 k
R3 45 k 180 k
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SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24
SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
NOTE: Test load capacitance includes probe and jig capacitance (unless otherwise specified).
Signal generator characteristics: rise and fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle, Zo = 50 (unless otherwise specified) IO VOD IO 50 pF 27 VOC
II 0 V or 3 V
27
Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
375 IO 0 V or 3 V IO VOD 60 375 VTEST = -20 V to 25 V
VTEST
Figure 2. Driver Test Circuit, VOD With Common-Mode Loading
3V INPUT RL = 54 Signal Generator 50 CL = 50 pF OUTPUT tr 0V 10% tf VOD(L) VOD tPLH 90% 1.5 V 1.5 V 0V tPHL VOD(H)
Figure 3. Driver Switching Test Circuit and Waveforms
27 A D Signal Generator 50 B 27 50 pF VOC VOC VA VB VOC(PP) 3.25 V 1.75 V VOC(SS)
Figure 4. Driver VOC Test Circuit and Waveforms
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SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24
SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
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VOD(SS) VOD(RING) VOD(PP) 0 V Differential
VOD(RING) VOD(SS) NOTE: VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from the VOD(H) and VOD(L) steady state values.
Figure 5. VOD(RING) Waveform and Definitions
A 0 V or 3 V 3 V if Testing A Output 0 V if Testing B Output DE Signal Generator 50 D B CL = 50 pF RL = 110 S1 Output DE tPZH Output 2.5 V tPHZ 1.5 V 1.5 V 0.5 V 0V VOH VOff 0 3V
Figure 6. Driver Enable/Disable Test, High Output
5V RL = 110 3V Output CL = 50 pF DE tPZL Output 1.5 V 1.5 V 0V tPLZ 2.5 V 0.5 V 5V VOL
0 V or 3 V 0 V if Testing A Output 3 V if Testing B Output DE Signal Generator 50
D
S1
Figure 7. Driver Enable/Disable Test, Low Output
3V DE 1.5 V 0V td(Wake) td(Standby) VOD 0.2 V 1.5 V
A 0 V or 3 V D B DE Signal Generator 50 RL = 54 CL = 50 pF VOD
Figure 8. Driver Standby/Wake Test Circuit and Waveforms
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SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24
SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
IOS VO Voltage Source
Figure 9. Driver Short-Circuit Test
IO VID VO
Figure 10. Receiver DC Parameter Definitions
Signal Generator
50 VID A B R IO Input B Input A tPLH Output 90% 1.5 V tr tf 50% 0V tPHL VOH 10% V OL 1.5 V
Signal Generator
50
CL = 15 pF
VO
Figure 11. Receiver Switching Test Circuit and Waveforms
VCC VCC
D DE A 54 B 3V R RE 1 k CL = 15 pF tPZH 1.5 V tPHZ VOH VOH -0.5 V GND 0V RE 1.5 V 0V
Signal Generator
50 R
Figure 12. Receiver Enable Test Circuit and Waveforms, Data Output High
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SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24
SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
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0V VCC
D DE A 54 B 3V R RE 1 k CL = 15 pF tPZL tPLZ VCC R 1.5 V VOL +0.5 V VOL 5V RE 1.5 V 0V
Signal Generator
50
Figure 13. Receiver Enable Test Circuit and Waveforms, Data Output Low
VCC A R B 1 k CL = 15 pF RE Signal Generator tr(Wake) 50 5V R 0V 1.5 V VOH -0.5 V VOL +0.5 V tr(Standby) VOH VOL RE
1.5 V
Switch Down for V(A) = 1.5 V, Switch Up for V(A) = -1.5 V 3V
1.5 V or -1.5 V
0V
Figure 14. Receiver Standby and Wake Test Circuit and Waveforms
200 mV -40 mV VID -200 mV -1.5 V Bus Data Valid Region Bus Data Indeterminate Region Bus Data Valid Region tp(SET) VOH R 1.5 V VOL tp(RESET)
Figure 15. Receiver Active Failsafe Definitions and Waveforms
100 Pulse Generator, 15 s Duration, 1% Duty Cycle
VTEST 0V 15 s 1.5 ms -VTEST
Figure 16. Test Circuit and Waveforms, Transient Over-Voltage Test
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SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24
SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
PIN ASSIGNMENTS
D or P PACKAGE (TOP VIEW)
R RE DE D
1 2 3 4
8 7 6 5
VCC B A GND
LOGIC DIAGRAM
POSITIVE LOGIC R RE DE D 1 2 3 4 6A 7 B
TYPICAL CHARACTERISTICS
HVD20, HVD23 BUS PIN CURRENT vs BUS PIN VOLTAGE
600 DE = 0 V 400 Bus Pin Current - A Bus Pin Current - A 100 150 DE = 0 V
HVD21, HVD22, HVD24 BUS PIN CURRENT vs BUS PIN VOLTAGE
200 VCC = 0 V 0
50 VCC = 0 V 0
VCC = 5 V
VCC = 5 V
-200
-50
-400 -600 -30
-100 -150 -30
-20
-10
0
10
20
30
-20
-10
0
10
20
30
Bus Pin Voltage - V
Bus Pin Voltage - V
Figure 17
Figure 18
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SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
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SUPPLY CURRENT vs SIGNALING RATE
75 70 ICC - Supply Current - mA 65 HVD22 60 55 50 45 40 0.1 HVD21 VCC = 5 V, DE = RE = VCC, LOAD = 54 , 50 pF HVD20
1 10 Signaling Rate - Mbps
100
Figure 19
DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs DRIVER LOAD CURRENT
5 VOD - Driver Differential Output Voltage - V VO - Receiver Output Voltage - V 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 10 20 30 40 50 60 IL - Driver Load Current - mA 70 80 -1 -0.2 -0.1 0 0.1 VID - Differential Input Voltage - V 0.2 VCC = 4.5 V VCC = 5.5 V VCC = 5 V 6 5 4
VCM = 0 V VIT(-) VCM = 25 V VIT(+) VCM = 25 V
RECEIVER OUTPUT VOLTAGE vs DIFFERENTAL INPUT VOLATGE
3 2 1 0
VCM = -20 V
VCM = 0 V
VCM = -20 V
Figure 20
Figure 21
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SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24
SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
APPLICATION INFORMATION
Figure 22. HVD22 Receiver Operation With 20 V Offset on Input Signal
H(s) + k0
1-k 1 )
k1p1 s ) p1
1-k
2
)
kp 22 s)p 2
1-k
3
)
kp 33 s)p 3
k0 (DC loss)
0.95 0.9 0.8 0.6
p1 (MHz)
0.25 0.25 0.25 0.3
k1
0.3 0.4 0.6 1
p2 (MHz)
3.5 3.5 2.2 3
k2
0.5 0.7 1 1
p3 (MHz)
15 12 8 6
k3
1 1 1 1
Similar to 160m of Belden 3105A Similar to 250m of Belden 3105A Similar to 500m of Belden 3105A Similar to 1000m of Belden 3105A
Signal Generator
H(s)
Figure 23. Cable Attenuation Model for Jitter Measurements
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SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24
SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
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Attenuation of Driver Signal
Sample Number
Attenuation of Driver Signal
Sample Number
Figure 24. Performance at 50 Mbps Signaling Rate Over 150 Meters Cable, Before and After Receiver Equalization (Preview)
Attenuation of Driver Signal
Sample Number
Attenuation of Driver Signal
Sample Number
Figure 25. Performance at 3 Mbps Signaling Rate Over 500 Meters Cable, Before and After Receiver Equalization (Preview)
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SN65HVD20, SN65HVD21 SN65HVD22, SN65HVD23, SN65HVD24
SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
MECHANICAL DATA
D (R-PDSO-G**)
8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20) NOM
Gage Plane 1 A 4 0- 8 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX A MIN
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
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SLLS552A - DECEMBER 2002 - REVISED MARCH 2003
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MECHANICAL DATA
P (R-PDIP-T8)
0.400 (10,60) 0.355 (9,02) 8 5
PLASTIC DUAL-IN-LINE
0.260 (6,60) 0.240 (6,10)
1
4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gage Plane
0.020 (0,51) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25)
M
0.430 (10,92) MAX
4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm 18
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