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TSL218 512 x 1 PIXEL LINEAR ARRAY
SOES014B - AUGUST 1994 - REVISED NOVEMBER 1995
* * * * * * *
512 x 1 Sensor Element Organization 200-Dots-per-Inch Sensor Pitch Extendable Data I/O for Expanding the Number of Arrays Analog Buffer With Sample-and-Hold Circuitry for Analog Output Over Full Clock Period 500-kHz Shift-Clock Operation Single 5-V Supply Advanced LinCMOSTM Technology
TSL218 PACKAGE (TOP VIEW)
1 2 3 4 5 6 7
VDD SI CLK AO GND SO VDD
description
The TSL218 intelligent optosensor consists of eight sections of 64 charge-mode pixels arranged in a 512 x 1 linear array. Each pixel measures 120 m x 70 m with 125-m center-to-center spacing. Operation is simplified by internal logic requiring only clock and serial-input pulse signals. The TSL218 is intended for use in a wide variety of applications including contact imaging, barcode reading, edge detection and positioning, level detection, and linear encoding.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1995, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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TSL218 512 x 1 PIXEL LINEAR ARRAY
SOES014B - AUGUST 1994 - REVISED NOVEMBER 1995
functional block diagram
VDD 1,7
1
2
3
512 Pixels Sense Node
Pixel Buffer Pixel Buffer
Pixel Selector Switch S1 Reset S2 S3 S512
Dark-Pixel Reference Generator
Differential Amplifier
Sample and Hold
Output Buffer RL (internal load)
4
AO
5
GND
Nonoverlapping Clock Generator 6 Q1 Q2 Q3 Q512 SO
CLK SI
3 2
512-Bit Shift Register
Clock Generator
Terminal Functions
TERMINAL NAME AO CLK GND SI SO VDD NO. 4 3 5 2 6 1, 7 Analog output Clock. The clock controls charge transfer, pixel output, and reset. Ground (substrate). All voltages are referenced to the substrate. Serial input. SI defines the start of the data-out sequence. Serial output. SO signals the end of the data-out sequence. Supply voltage for both analog and digital circuits DESCRIPTION
detailed description
sensor elements The line of sensor elements, called pixels, consists of 512 discrete photosensing areas. Light energy striking a pixel generates electron-hole pairs in the region under the pixel. The field generated by the bias on the pixel causes the electrons to collect in the element while the holes are swept into the substrate. The amount of charge accumulated in each element is directly proportional to the amount of incident light and the integration time. device operation Operation of the 512 x 1 array sensor is a function of two time periods--an integration period during which a charge is accumulated in the pixels and an output period during which signals are transferred to the output. The integration period is defined by the interval between the externally supplied SI pulses and includes the output period (see Figure 1). The required length of the integration period depends on the amount of incident light and the desired output-signal level.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSL218 512 x 1 PIXEL LINEAR ARRAY
SOES014B - AUGUST 1994 - REVISED NOVEMBER 1995
sense node On completion of the integration period, the charge contained in each pixel is transferred in turn to the sense node under the control of the CLK and SI signals. The signal voltage generated at this node is directly proportional to the amount of charge and inversely proportional to the capacitance of the sense node. reset An internal reset signal is generated by the nonoverlapping clock generator (NOCG) and occurs every clock cycle. Reset establishes a known voltage on the sense node in preparation for the next charge transfer. This voltage is used as a reference level for the differential signal amplifier. shift register The 512-bit shift register controls the transfer of charge from the pixels to the output stages and provides timing signals for the NOCG. The serial input (SI) signal provides the input to the shift register and is shifted under direct control of CLK out to the serial output (SO) on the 512th clock cycle. This SO pulse can then be used as the SI pulse for the next device. The output period is initiated by the presence of the SI input pulse coincident with a rising edge of CLK (see Figures 1 and 2). The analog output voltage corresponds to the level of the first pixel after settling time (ts) and remains constant for a minimum time (tv). A voltage corresponding to each succeeding pixel is available at each rising edge of CLK. The output period of the device ends when it sees the rising edge of the 513th clock cycle, at which time the output assumes the high-impedance state. Once the output period has been initiated by an SI pulse, CLK must be allowed to complete 513 positive-going transitions in order to reset the internal logic to a known state. To achieve minimum integration time, the SI pulse may be present on the 514th rising clock to immediately restart the output phase. sample-and-hold The sample-and-hold signal generated by the NOCG holds the analog output voltage of each pixel constant until the next pixel is clocked out. The signal is sampled while CLK is high and held constant while CLK is low. nonoverlapping clock generators The NOCG circuitry provides internal control signals for the sensor, including reset and pixel-charge sensing. The signals are synchronous and are controlled by the outputs of the shift register. initialization Initialization of the sensor elements may be necessary on power up or during operation after any period of CLK or SI inactivity exceeding the integration time. The initialization phase consists of 12 to 15 consecutively performed output cycles and clears the pixels of any charge that may have accumulated during the inactive period. multiple-unit operation Multiple-sensor devices can be connected together in a serial or parallel configuration. The serial connection is accomplished by connecting analog outputs (AO) together and connecting the SO output of each sensor device to the SI input of the next device. The SI signal is applied to only the first device. Each succeeding device receives its SI input from the SO output of the preceding device. For m-cascaded devices, the SI pulse is applied to the first device after every m x 512th positive-going CLK transition. A common clock signal is applied to all the devices simultaneously. Parallel operation of multiple devices is accomplished by supplying CLK and SI signals to all the devices simultaneously. The output of each device is then separately used for processing.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
TSL218 512 x 1 PIXEL LINEAR ARRAY
SOES014B - AUGUST 1994 - REVISED NOVEMBER 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Digital output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VDD + 0.5 V Digital output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 mA Digital input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 20 mA to 20 mA Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 25C to 85C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN Supply voltage, VDD Input voltage, VI High-level input voltage, VIH Low-level input voltage, VIL Wavelength of light source, Clock frequency, fclock Sensor integration time, tint (see Figures 1 and 2) Pulse duration, CLK low, tw(CLKL) Setup time, SI before CLK, tsu(SI) (see Figure 2) Hold time, SI after CLK, th(SI) (see Note 1) (see Figure 2) Operating free-air temperature, TA NOTE 1: SI must go low before the rising edge of the next clock pulse. 4.5 0 VDD x 0.7 0 565 10 1.028 1 50 50 0 70 5 NOM 5 MAX 5.5 VDD VDD VDD x 0.3 700 500 UNIT V V V V nm kHz ms s ns ns C
electrical characteristics at fclock = 200 kHz, VDD = 5 V, TA = 25C, p = 660 nm, tint = 5 ms, Ee = 20 W/cm2 (unless otherwise noted)
PARAMETER Analog output voltage (white, average over 512 pixels) Analog output voltage (dark, each pixel) Dispersion of analog output voltage Linearity of analog output voltage Analog output saturation Supply current High-level input current Low-level input current Input capacitance VI = VDD VI = 0 5 See Note 2 See Note 3 Ee = 60 W/cm2 0.85 3 3.4 16 24 0.5 0.5 TEST CONDITIONS MIN 1.75 TYP 2.2 0.25 0.4 20% 1.15 V mA A A pF MAX UNIT V V
NOTES: 2. Dispersion is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated. 3. Linearity of analog-output voltage is calculated by averaging over 512 pixels and measuring the maximum deviation of the voltage at 3 ms and 4.5 ms from a line drawn between the voltage at 3 ms and 6 ms.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSL218 512 x 1 PIXEL LINEAR ARRAY
SOES014B - AUGUST 1994 - REVISED NOVEMBER 1995
operating characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figure 2)
PARAMETER tr(SO) tf(SO) tpd(SO) ts tv Rise time, SO Fall time, SO Propagation delay time, SO Settling time Valid time CL = 30 pF TEST CONDITIONS MIN TYP 25 25 70 1 1/2 fclock MAX UNIT ns ns ns s s
PARAMETER MEASUREMENT INFORMATION
CLK 512 Cycles Clock Continues or Remains Low After 512th Cycle 512 Cycles
tint SI
SO
Analog Output Period AO
Figure 1. Timing Diagram
tw CLK tsu(SI)
1
2
512
513 2.5 V
SI
50% 0V th(SI) tpd(SO) 90% 10% ts ts 90% Pixel 1 tv 90% Pixel 512 tr(SO) tpd(SO) 10% 90% tf(SO)
SO
AO
Figure 2. Operational Waveforms
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IIIII IIIII
5V 0V 5V 5
IIIII IIIII
TSL218 512 x 1 PIXEL LINEAR ARRAY
SOES014B - AUGUST 1994 - REVISED NOVEMBER 1995
APPLICATION INFORMATION
The device consists of eight cascaded 64 x 1 arrays mounted in a single, glass-epoxy substrate with a cover glass for protection. Mounting holes are standard and pins are optional.
0.094 (2,39) 0.084 (2,13) DIA Mounting Holes 2 Places 1.215 (30,86) 1.185 (30,10) 0.240 (6,10) 0.220 (5,59) TOP VIEW 0,100(2.54) BSC
0.230 (5,84) 0.210 (5,33) See Note A
1 Pixel 1 Linear Array
7 Pixel 512 0.510 (12,95) 0.490 (12,45)
0.080 (2,03) 0.060 (1,52)
2.855 (72,52) 2.835 (72,01) 3.010 (76,45) 2.990 (75,95)
0.200 (5,08) MIN 0.140 (3,56) 0.115 (2,92) 0.022 (0,56) DIA 0.018 (0,46) 7 Places (optional) Cover Glass 0.015 (0,38) Typical Free Area
Linear Array
NOTES: A. All linear dimensions are in inches(millimeters). B. This drawing is subject to change without notice. C. The pixel centers are in line with center line of mounting holes.
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IIIIIIIIIIIIIIIIIIIII
Figure 3. TSL218 Mechanical Specifications
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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Copyright (c) 1998, Texas Instruments Incorporated

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