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TIBPSG507AC 13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D - D3029, MAY 1987 - REVISED NOVEMBER 1995
* * * * * * * *
58-MHz Max Clock Rate Ideal for Waveform Generation and High-Performance State Machine Applications 6-Bit Internal Binary Counter 8-Bit Internal State Register Programmable Clock Polarity Outputs Programmable for Registered or Combinational Operation 6-Bit Counter Simplifies Logic Equation Development in State Machine Designs Programmable Output Enable
JT OR NT PACKAGE (TOP VIEW)
CLK I0 I1 I2 I3 I4 I5 Q0 Q1 Q2 Q3 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC I6 I7 I8 I9 I10 I11 I12/OE Q7 Q6 Q5 Q4
description
The TIBPSG507AC is a 13 x 80 x 8 Programmable Sequence Generator (PSG) that offers the system designer unprecedented flexibility in a high-performance field-programmable logic device. Applications such as waveform generators, state machines, dividers, timers, and simple logic reduction are all possible with the PSG. By utilizing the built-in binary counter, the PSG is capable of generating complex timing controllers. The binary counter also simplifies logic equation development in state machine and waveform generator applications. The TIBPSG507AC contains 80 product (AND) terms, a 6-bit binary counter with control logic, eight S/R state holding registers, and eight outputs. The eight outputs can be individually programmed for either registered or combinational operation. The clock input is fuse programmable for either positive- or negativeedge operation.
FK OR FN PACKAGE (TOP VIEW)
I2 I3 I4 NC I5 Q0 Q1
5 6 7 8 9 10
I1 I0 CLK NC VCC I6 I7
4 3 2 1 28 27 26 25 24 23 22 21 20 11 19 12 13 14 15 16 17 18
I8 I9 I10 NC I11 I12/OE Q7
NC - No internal connection
The 6-bit binary counter is controlled by a synchronous-clear and a count/hold function. Each control function has a nonregistered and registered option. When either SCLR0 or SCLR1 is taken high, the counter resets to zero on the next active clock edge. When either CNT/HLD0 or CNT/HLD1 is taken high, the counter is held at the present count and is not allowed to advance on the active clock edge. The SCLR function overrides the CNT/HLD feature when both lines are simultaneously high. Clock polarity is programmable through the clock polarity fuse. Leaving this fuse intact selects positive-edge triggering. Negative-edge triggering is selected by blowing this fuse. Pin 17 functions as an input and/or an output enable. When the output enable fuse is intact, all outputs are always enabled allowing pin 17 to be used strictly as an input. Blowing the output enable fuse lets pin 17 function as an output enable and an input. In this mode, the outputs are enabled when pin 17 is low and are in a high-impedance state when pin 17 is high.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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Q2 Q3 GND NC Q4 Q5 Q6
Copyright (c) 1995, Texas Instruments Incorporated
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TIBPSG507AC 13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D - D3029, MAY 1987 - REVISED NOVEMBER 1995
description (continued)
The eight outputs can be individually programmed for combinational operation by blowing the output multiplexer fuse. After power up, the device must be initialized to the desired state. When the output multiplexer fuse is left intact, registered operation is selected. The TIBPSG507AC is characterized for operation from 0C to 75C.
6-BIT COUNTER CONTROL FUNCTION TABLE (see Note 1) CNT/HLD1 L X X X H CNT/HLD0 L X X H X SCLR1 L X H L L SCLR0 L H X L L OPERATION counter active synchronous clear synchronous clear hold counter hold counter
NOTE 1: When all fuses are blown on a product line (AND), its output will be high. When all fuses are blown on a sum line (OR), its output will be low. All product and sum terms are low on devices with fuses intact. S/R FUNCTION TABLE (see Note 2) CLK POLARITY FUSE INTACT INTACT INTACT INTACT BLOWN BLOWN BLOWN BLOWN CLK S L L H H L L H H R L H L H L H L H STATE REGISTER Q0 L H INDET Q0 L H INDET
Output state is indeterminate NOTE 2: After power up, the device must be initialized to its desired state. Q0 is the state of the S/R register before the active clock edge.
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TIBPSG507AC 13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D - D3029, MAY 1987 - REVISED NOVEMBER 1995
functional block diagram (positive logic)
CLK
8 6 State Registers 1 80 x 38 C1 1S 1R 1S 6x 6 6 8x 8 8 80 8 I0 - I11 I12/OE 12 1 13 x 13 13 8 8 C1 8x 1S 1R 8 8 6 & 54 x 80 1R Binary Counter CTR 6 G2
1CT = 0 C1/2,3+ G3 1CT = 0
6 C0 - C5
Output Cell 1
C1 8 8 8x 1S 1R G1 EN 8 1 8 Q0 - Q7
denotes fused inputs
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3
1380
2852
3588
4324
5050
5796
6532
644
7360 2 3 4 5 6 7 23 22 21 20 19 18 17 26 0
7268
2115
"AND" Term Numbers
"AND" Term Numbers
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logic diagram (positive logic)
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SRPS002D - D3029, MAY 1987 - REVISED NOVEMBER 1995
TIBPSG507AC 13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
CLK
I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 PRE/OE
7361
0
Binary Counter Functional Logic Symbol CTR 6 CNT/HLD1 SCLR1 CLK CNT/HLD0 SCLR0
P0 P1 P2 P3 P4 P5 P6 P7 CTR C0 C1 C2 C3 C4 C5
5
C0 C1 C2 C3 C4 C5
G2 1CT = 0 C1/2,3+ G3 1CT = 0
10
15
20
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53
SCLR0 54
1S C1 1R
SCLR1 CNT/HLD0 CNT/HLD1
58
1S C1 1R 1S C1 1R
62
1S C1 1R 1S C1 1R
66
1S C1 1R
1S C1 1R
70
1S C1 1R 1S C1 1R
74 "OR" Term Numbers
1S C1 1R 1 MUX 1S C1 1R 1 G1 1 MUX
8 7362 9 7363 10 7364 11 7365 13 7366 14 7367 15 7368 16 7369
Q0
78
1S C1 1R 1S C1 1R
Q1
1 G1 1 MUX
Q2
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TIBPSG507AC 13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
82
1S C1 1R 1S C1 1R
Q3
G1 1 MUX 1 G1 1 MUX
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86
1S C1 1R 1S C1 1R
Q5
1 G1 1 MUX 1 G1 1 MUX 1
Q6
SRPS002D - D3029, MAY 1987 - REVISED NOVEMBER 1995
90 91
1S C1 1R
Q7
G1
All inputs to AND gates, exclusive-OR gates, and multiplexers with a blown link assume the logic-1 state. All OR gate inputs with a blown link assume the logic-0 state.
TIBPSG507AC 13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D - D3029, MAY 1987 - REVISED NOVEMBER 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to disabled output (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 75C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
NOTE 3: These ratings apply except for programming pins during a programming cycle or during the diagnostic mode.
recommended operating conditions
MIN VCC VIH VIL IOH IOL tw Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Pulse duration Clock high Clock low Input or feedback to S/R inputs tsu Setup time before CLK active transition Input or feedback to S/R inputs Input or feedback to SCLR0 Input or feedback to CNT/HLD0 Input or feedback at S/R inputs th Hold time after CLK active transition Input or feedback at SCLR0 Input or feedback at CNT/HLD0 6 6 12 19 20 25 0 0 0 ns ns 4.75 2 NOM 5 MAX 5.25 5.5 0.8 - 3.2 16 UNIT V V V mA mA ns
TA Operating free-air temperature 0 25 75 C Internal setup and hold times, tsu feedback to SCLR1, feedback to CNT/HLD1; th feedback at SCLR1 and feedback at CNT/HLD1, are guaranteed by fmax specifications. The active transition of CLK is determined by the programmed state of the CLK polarity fuse. See the OR term loading section and Figure 3.
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TIBPSG507AC 13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D - D3029, MAY 1987 - REVISED NOVEMBER 1995
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL IOZH IOZL II IIH IIL IO ICC Ci Co Cclk VCC = 4.75 V, VCC = 4.75 V, VCC = 4.75 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, f = 1 MHz, f = 1 MHz, f = 1 MHz, TEST CONDITIONS II = - 18 mA IOH = - 3.2 mA IOL = 16 mA VO = 2.7 V VO = 0.4 V VI = 5.5 V VI = 2.7 V VI = 0.4 V VO = 0.5 V See Note 4, VI = 2 V VO = 2 V VCLK = 2 V - 30 Outputs open 156 7 11 14 MIN 2.4 TYP 3.2 0.25 0.5 20 -20 0.1 20 - 0.25 -130 210 MAX - 1.2 UNIT V V V A A mA A mA mA mA pF pF pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER FROM (INPUT) 6-Bit counter with SCLR0 6-Bit counter with CNT/HLD0 With external feedback (see Figure 1) Q (nonregistered)# tpd ten tdis CLK I or Feedback OE OE Q (registered) Q (nonregistered) Q Q R1 = 300 , R2 = 390 , See Figure 6 TO (OUTPUT) TEST CONDITION MIN 58 40 33 45 6 3 6 1 1 6 6 TYP 65 55 50 60 25 10 20 10 10 ns ns ns ns MHz MAX UNIT
6-Bit counter with SCLR1 or CNT/HLD1 fmax
All typical values are at VCC = 5 V, TA = 25C. This parameter approximates IOS. The condition VO = 0.5 V takes tester noise into account. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. See the fmax calculations section. The active edge of CLK is determined by the programmed state of the CLK polarity fuse. # tpd CLK to Q (nonregistered) is the same for data clocked from the counter or state registered. NOTE 4: When the clock is programmed for negitive edge, then VI = 4.5 V. When the clock is programmed for positive edge, then VI = 0.
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TIBPSG507AC 13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D - D3029, MAY 1987 - REVISED NOVEMBER 1995
fmax calculations
The following are the different speeds that can be achieved when using the TIBPSG507AC as a state machine. The way the 6-bit counter is controlled will largely determine the operating frequency of the state machine. where setup time tsu for input CLK to Q pd or feedback to the S/R inputs = 12 ns and propagation delay time tpd CLK to Q for the internal S/R registers = 5 ns (difference in tpd from CLK and feedback, 25 to 20). t su t Thus: fmax for this condition fmax for a 6-bit counter using SCLR1 or CNT/HLD1 =
)
1
+
1 (12 + 5) ns
+
1 17 ns t su
+
t
58 MHz. 1
where setup time tsu for input or CLK to Q pd feedback to the SCLR0 inputs = 20 ns and propagation delay time tpd CLK to Q for the internal S/R registers = 5 ns (difference in tpd from CLK and feedback, 25 to 20) Thus: fmax for this condition
fmax for a 6-bit counter using SCLR0 for reset =
)
+
1 (20 + 5) ns
+
1 25 ns t su
+
40 MHz. 1 t
where setup time tsu for input or CLK to Q pd feedback to CNT/HLD0 = 25 ns and propagation delay time tpd CLK to Q for the internal S/R registers = 5 ns (difference in tpd from CLK and feedback, 25 to 20). Thus: fmax for this condition
fmax for a 6-bit counter using CNT/HLD0 for reset =
)
+
1 (25 + 5) ns
+
1 30 ns
+
33 MHz.
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers. Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. Information on programmers that are capable of programming Texas Instruments programmable logic is also available, upon request, from the nearest TI sales office, local authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.
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TIBPSG507AC 13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D - D3029, MAY 1987 - REVISED NOVEMBER 1995
tmin(1) Min Clock Period Using This Path tmin(2) Min Clock Period using This Path Dedicated Inputs tmin(3) Min Clock Period Using This Path Counter or Internal SRs SCLR0 or CNT/HLD0 SR SR
tsu(3) tmin(2) CLK tsu(2) I to Internal S or R
Feedback Lines
SR CLK Internal
Output SRs
CLK tmin(1) SR
tpd(3) CLK Internal to Output Response
tsu(1) I to Output S or R
SR
tpd(2) CLK to Q Pin tpd(1) I to Output Pin
Dedicated Inputs Output Pin
Figure 1. Timing Model
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TIBPSG507AC 13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D - D3029, MAY 1987 - REVISED NOVEMBER 1995
glossary -- timing model
tpd(1) -- tpd(2) -- tpd(3) -- Maximum time interval from the time a signal edge is received at any input pin to the time any logically affected combinational output pin delivers a response. Maximum time interval from a positive edge on the clock input pin to data delivery on the output pin corresponding to any output SR register. Maximum time interval from the positive edge on the clock input pin to the response on any logically affected combinational configured output (at the pin), where data origin is any internal SR register or counter bit. Minimum time interval that must be allowed between the data edge on any dedicated input and the active clock edge on the clock input pin when data affects the S or R line of any output SR register. Minimum time interval that must be allowed between the data edge on any dedicated input and the active clock edge on the clock input pin when data affects the S or R line of any internal SR register. Minimum time interval that must be allowed between the data edge on any dedicated input and the active clock edge on the clock input pin only when entering data on the CNT/HLD0 line. Minimum time interval that must be allowed between the data edge on any dedicated input and the active clock edge on the clock input pin only when entering data on the SCLR0 line.
tsu(1) -- tsu(2) -- tsu(3) -- tsu(4) --
tmin(1) -- Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using feedback from any internal SR register or counter bit to feed the S or R line of any output SR register. tmin(2) -- Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using feedback from any internal SR register to feed the S or R line of any internal SR register. tmin(3) -- Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using feedback from any internal SR register or counter bit to feed SCLR0 or CNT/HLD0.
PARAMETER VALUES FOR TIMING MODEL tpd(1) = 20 ns tpd(2) = 10 ns tpd(3) = 25 ns tsu(1) = 12 ns tsu(2) = 12 ns tsu(3) = 25 ns tsu(4) = 20 ns INTERNAL NODE NUMBERS SCLR0 SCLR1 25 SET 26 RESET 27 C0-C5 CNTHLD0 CNTHLD1 28 SET 29 RESET 30 55-60 Q0-Q7 P0-P7 SET 31-38 RESET 39-46 RESET 47-54 tmin(1) = 17 ns tmin(2) = 17 ns tmin(3) = 25 ns
Use tsu = 19 ns for applications where the setup time for S/R inputs are required.
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SRPS002D - D3029, MAY 1987 - REVISED NOVEMBER 1995
diagnostics
A diagnostic mode is provided that allows the user to inspect the contents of the state registers. The following are step-by-step procedures required for the diagnostics. Step 1. Step 2. Step 3. Disable all outputs by taking pin 17 (OE) high (see Note 5). Take pin 8 (Q0) to VIHH to enable the diagnostics test sequence. Apply appropriate levels of voltage to pins 11 (Q3), 13 (Q4), and 14 (Q5) to select the desired state register (see Table 1).
The voltage level monitored on pin 9 will indicate the state of the selected state register.
NOTE 5: If pin 17 is being used as an input to the array, then pin 7 (I5) must be taken to VIHH before pin 17 is taken high. VIHH I5 Pin 7 OE Pin 17 VIH 100 ns VOHH VOH 100 ns Q3, Q4, Q5 Pins 11, 13, 14 100 ns Q1 Pin 9 VIHH = 10.25 V min, 10.5 V nom, 10.75 V max VOL VOHH VOH VOL VOH VOL
Q0 Pin 8
Figure 2. Diagnostics Waveforms Table 1. Addressing State Registers During Diagnostics
REGISTER BINARY ADDRESS PIN 11 L L L L L L L L L H H H H H H H H H PIN13 L L L H H H HH HH HH L L L H H H HH HH HH PIN 14 L H HH L H HH L H HH L H HH L H HH L H HH BURIED REGISTER SELECTED SCLR0 SCLR1 CNT/HLD0 CNT/HLD1 P0 P1 P2 P3 P4 P5 P6 P7 C0 C1 C2 C3 C4 C5
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TIBPSG507AC 13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D - D3029, MAY 1987 - REVISED NOVEMBER 1995
PRINCIPLES OF OPERATION PSG design theory
Most state machine and waveform generator designs can be simplified with the PSG by referencing all or part of each sequence to a binary count. The internal state registers can then be used to keep track of which binary count sequence is in operation, to store input data and keep track of internally generated status bits, or as output registers when connected to a nonregistered output cell. State registers can also be used to expand the binary counter when a larger counter is needed. Through the use of the binary counter, the number of product lines and state registers required for a design is usually reduced. In addition, the designer does not have to be concerned about generating wait states where the outputs are unaffected because these can be timed from the binary counter. For detailed information and examples using this design concept, see A Designer's Guide to the TIBPSG507 applications report.
OR term loading
As shown in Figure 3 and by the fmax calculation, fmax is affected by the number of terms connected to each OR array line. Theoretically, fmax is calculated as: 1 fmax = t su t CLK to Q pd Since the setup time (input or feedback to S/R) varies with the number of terms connected to each OR array line, (due to capacitance loading) fmax will also vary. Figure 3 illustrates the relationship between the number of terms connected per OR line and the setup time.
)
Use Figure 3 to determine the worst-case setup time for a particular application. Identify the OR array line with the maximum number of terms connected. Count the number of terms and use the graph to determine the setup time.
WORST-CASE SETUP TIME (input or feedback to SR) vs "OR" TERM LOAD
20 19 18 t su - Setup Time - ns 17 16 15 14 13 12 11 10 0 20 40 60 80 Maximum Number of OR Terms Connected VCC = 4.75 V TA = 75C
Figure 3
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TIBPSG507AC 13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D - D3029, MAY 1987 - REVISED NOVEMBER 1995
fmax with external feedback
The configuration shown is a typical state-machine design with feedback signals sent off-chip. This external feedback could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining the clock period is the sum of the clock-to-output delay time and the setup time for the input or feedback signals (tsu + tpd CLK to Q). Thus: fmax with external feedback = t su
)
1 t pd CLK to Q
CLK Input
Logic Array
Internal SR Registers
Output SR Registers
Next Device
tsu
tpd CLK to Q
Figure 4
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TIBPSG507AC 13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D - D3029, MAY 1987 - REVISED NOVEMBER 1995
APPLICATION INFORMATION
The TIBPSG507AC is used in this application to generate the required memory timing control signals (RAS, CAS, etc.) for the memory timing controller.
RFC Refresh Timer REFREQ REFEQ Memory Timing Controller TIBPSG507A Clock Generator OSC CLK RFC VCC LE RAASI CAASI MSEL MC1 OE RAS2 CAS2 W Q0-Q8 Dynamic Memory Controller SN74ALS6301 A0-A8 RAS0 CAS0 W
Dynamic RAM Bank0 1 Meg x 32 Bit TMS4C1027
A0-A8 RAS1 CAS1 W
Bank1 1 Meg x 32 Bit TMS4C1027
RESET
AS
WAIT R/W A22 ALE
A0-A8
Bank2 1 Meg x 32 Bit TMS4C1027
CS Microprocessor SN74ALS6301
A0-A8 Address 2 Memory Bank Signals SEL0,1 RAS3 CAS3 W
Bank3 1 Meg x 32 Bit TMS4C1027
Data For detailed information, please see the Systems Solution for Static Column Decode Application Report.
Figure 5
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TIBPSG507AC 13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D - D3029, MAY 1987 - REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
5V
S1 R1 From Output Under Test CL (see Note A) R2 Test Point
LOAD CIRCUIT FOR 3-STATE OUTPUTS High-Level Pulse 3.5 V 1.5 V 1.5 V 0.3 V tw Low-Level Pulse 3.5 V 1.5 V 1.5 V 0.3 V VOLTAGE WAVEFORMS PULSE DURATIONS Output Control (low-level enabling) ten 3.5 V 1.5 V 1.5 V 0.3 V tdis 1.5 V
Timing Input tsu Data Input 1.5 V
3.5 V 1.5 V 0.3 V th 3.5 V 1.5 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
3.5 V Input tpd In-Phase Output 1.5 V 1.5 V 1.5 V 0.3 V tpd VOH 1.5 V VOL tpd 1.5 V VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
Waveform 1 S1 Closed (see Note B) ten Waveform 2 S1 Open (see Note B)
3.3 V VOL +0.5 V
VOL
tpd Out-of-Phase Output (see Note D)
tdis VOH 1.5 V VOH -0.5 V
0V
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses have the following characteristics: PRR 1 MHz, tr = tf 2 ns, duty cycle = 50%. D. When measuring propagation delay times of 3-state outputs, switch S1 is closed. E. Equivalent loads may be used for testing.
Figure 6. Load Circuit and Voltage Waveforms
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TIBPSG507AC 13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D - D3029, MAY 1987 - REVISED NOVEMBER 1995
TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs FREE-AIR TEMPERATURE
200 175 I CC - Supply Current - mA 150 125 100 75 50 25 0 0 25 50 75 TA - Free-Air Temperature - C
VCC = 5.25 V VCC = 5 V VCC = 4.75 V
Figure 7
POWER DISSIPATION vs FREQUENCY
1000
950 Power Dissipation - mW
900
850 TA = 0C 800 TA = 25C 750 TA = 50C 700 1 2 4 7 10 20 40 70 100 f - Frequency - MHz
Figure 8
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TIBPSG507AC 13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D - D3029, MAY 1987 - REVISED NOVEMBER 1995
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME vs SUPPLY VOLTAGE
20 18 Propagation Delay Time - ns Propagation Delay Time - ns 16 14 12 10 8 6 4 2 R1 = 300 R2 = 390 CL = 50 pF TA = 25C 5 VCC - Supply Voltage - V tPHL (CLK to Q) tPLH (CLK to Q) tPLH (I or Feedback to Q) tPHL (I or Feedback to Q) 25 30 VCC = 5 V R1 = 300 R2 = 390 TA = 25C
PROPAGATION DELAY TIME vs LOAD CAPACITANCE
20
15 tPHL (I or Feedback to Q) tPLH (I or Feedback to Q) tPLH (CLK to Q) tPHL (CLK to Q)
10
5
0 4.75
0 5.25 0 100 300 400 500 200 CL - Load Capacitance - pF 600
Figure 9
Figure 10
PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE
20 18 tPHL (I or Feedback to Q) Propagation Delay Time - ns 14 12 10 8 6 tPHL (CLK to Q) 4 2 0 0 VCC = 5 V R1 = 300 R2 = 390 CL = 50 pF 25 0 50 75 TA - Free-Air Temperature - C tPLH (CLK to Q) Propagation Delay Time - ns 16 tPLH (I or Feedback to Q) 16 14 12 10 8 6 4 2 0 0 20 18
PROPAGATION DELAY TIME vs NUMBER OF OUTPUTS SWITCHING
tPHL (I or Feedback to Q)
tPLH (I or Feedback to Q)
tPLH (CLK to Q)
VCC = 5 V R1 = 300 R2 = 390 CL = 50 pF TA = 25C 1 2 3 4
tPHL (CLK to Q)
5
6
7
8
Number of Outputs Switching
Figure 11
Figure 12
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