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TLC2551, TLC2552, TLC2555 5-V, LOW-POWER, 12-BIT, 175/360 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276D - MARCH 2000 - REVISED MAY 2003
D Maximum Throughput . . . 175/360 KSPS D INL/DNL: 1 LSB Max, SINAD: 72 dB, D D D D
SFDR: 85 dB, fi = 20 kHz SPI/DSP-Compatible Serial Interface Single 5-V Supply Rail-to-Rail Analog Input With 500 kHz BW Three Options Available: - TLC2551: Single Channel Input
TOP VIEW TLC2551
D D
- TLC2552: Dual Channels With Autosweep - TLC2555: Single Channel With Pseudo-Differential Input Low Power With Autopower Down - Operating Current: 3.5 mA Autopower Down: 8 A Small 8-Pin MSOP and SOIC Packages
TOP VIEW TLC2552 8 7 6 5
TOP VIEW TLC2555 8 7 6 5
CS VREF GND AIN
1 2 3 4
SDO FS VDD SCLK
CS VREF GND AIN0
1 2 3 4
SDO SCLK VDD AIN1
CS VREF GND AIN(+)
1 2 3 4
8 7 6 5
SDO SCLK VDD AIN(-)
description
The TLC2551, TLC2552, and TLC2555 are a family of high performance, 12-bit, low-power, miniature, CMOS analog-to-digital converters (ADC). The TLC255x family uses a 5-V supply. Devices are available with single, dual, or single pseudo-differential inputs. Each device has a chip select (CS), serial clock (SCLK), and serial data output (SDO) that provides a direct 3-wire interface to the serial port of most popular host microprocessors (SPI interface). When interfaced with a TMS320 DSP, a frame sync signal (FS) can be used to indicate the start of a serial data frame on CS for all devices or on FS for the TLC2551. The TLC2551, TLC2552, and TLC2555 are designed to operate with very low power consumption. The power saving feature is further enhanced with an autopower-down mode. This product family features a high-speed serial link to modern host processors with SCLK up to 20 MHz. The maximum SCLK frequency is dependent upon the mode of operation (see Table 1). The TLC255x family uses SCLK as the conversion clock, which provides synchronous operation and a minimum conversion time of 1.5 s using a 20-MHz SCLK.
AVAILABLE OPTIONS PACKAGED DEVICES TA 8-MSOP (DGK) TLC2551CDGK (AHF) 0C to 70 C 0 C 70C TLC2552CDGK (AHH) TLC2555CDGK (AHJ) TLC2551IDGK (AHG) - 40C to 85C 40 C 85 C TLC2552IDGK (AHI) TLC2555IDGK (AHK) TLC2551ID TLC2552ID TLC2555ID 8-SOIC (D)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320 is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002 - 2003, Texas Instruments Incorporated
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TLC2551, TLC2552, TLC2555 5-V, LOW-POWER, 12-BIT, 175/360 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276D - MARCH 2000 - REVISED MAY 2003
functional block diagram
TLC2551 VDD VREF VREF AIN0 AIN S/H LOW POWER 12-BIT SAR ADC AIN1 SDO S/H /2 SCLK CS FS /2 CONTROL LOGIC SCLK CS CONTROL LOGIC GND TLC2555 VDD VREF LOW POWER SAR ADC SDO Mux TLC2552 VDD
GND
AIN (+) S/H AIN (-)
LOW POWER 12-BIT SAR ADC
SDO
/2 SCLK CS CONTROL LOGIC GND
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SLAS276D - MARCH 2000 - REVISED MAY 2003
Terminal Functions TLC2551
TERMINAL NAME AIN CS FS GND SCLK SDO NO. 4 1 7 3 5 8 I/O I I I I I O Analog input channel Chip select. A high-to-low transition on the CS input removes SDO from 3-state within a maximum setup time. CS can be used as the FS pin when a dedicated DSP serial port is used. DSP frame sync input. Indication of the start of a serial data frame. Tie this terminal to VDD if not used. Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. Output serial clock. This terminal receives the serial SCLK from the host processor. The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state until CS falling edge or FS rising edge, whichever occurs first. The output format is MSB first. When FS is not used (FS = 1 at the falling edge of CS), the MSB is presented to the SDO pin after CS falling edge and output data is valid on the first falling edge of SCLK. When CS and FS are both used (FS = 0 at the falling edge of CS), the MSB is presented to the SDO pin after the falling edge of CS. When CS is tied/held low, the MSB is presented on SDO after rising FS. Output data is valid on the first falling edge of SCLK. (This is typically used with an active FS from a DSP.) VDD VREF 6 2 I I Positive supply voltage External reference input DESCRIPTION
TLC2552/55
TERMINAL NAME AIN0 /AIN(+) AIN1/AIN (-) CS GND SCLK SDO NO. 4 5 1 3 7 8 I/O I I I I I O DESCRIPTION Analog input channel 0 for TLC2552--Positive input for TLC2555 Analog input channel 1 for TLC2552--Inverted input for TLC2555 Chip select. A high-to-low transition on CS removes SDO from 3-state within a maximum delay time. This pin can be connected to the FS output from a DSP on a dedicated serial port. Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. Output serial clock. This terminal receives the serial SCLK from the host processor. The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state when CS is high and presents output data after the CS falling edge until the LSB is presented. The output format is MSB first. SDO returns to the Hi-Z state after the 16th SCLK. Output data is valid on the falling SCLK edge. Positive supply voltage External reference input
VDD VREF
6 2
I I
detailed description
The TLC2551, TLC2552, and TLC2555 are successive approximation (SAR) ADCs utilizing a charge redistribution DAC. Figure 1 shows a simplified version of the ADC. The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is balanced, the conversion is complete and the ADC output code is generated.
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SLAS276D - MARCH 2000 - REVISED MAY 2003
detailed description (continued)
Charge Redistribution DAC
AIN
_ +
Control Logic
ADC Code
GND/AIN(-)
Figure 1. Simplified SAR Circuit serial interface
OUTPUT DATA FORMAT MSB D15-D4 Conversion result (OD11-OD0) D3-D0 Don't care LSB
The output data format is binary (unipolar straight binary). binary Zero-scale code = 000h, Vcode = GND Full-scale code = FFFh, Vcode = VREF - 1 LSB pseudo-differential inputs The TLC2555 operates in pseudo-differential mode. The inverted input is available on pin 5. It can have a maximum input ripple of 0.2 V. This is normally used for ground noise rejection.
control and timing
start of the cycle Each cycle may be started by either CS, FS, or a combination of both. The internal state machine requires one SCLK high-to-low transition to determine the state of these control signals so internal blocks can be powered up in an active cycle. Special care to SPI mode is necessary. Make sure there is at least one SCLK whenever CS (pin 1) is high to assure proper operation. TLC2551
D Control via CS ( FS = 1 at the falling edge of CS)--The falling edge of CS is the start of the cycle. The MSB
may be read on the first falling SCLK edge after CS is low. Output data changes on the rising edge of SCLK. This is typically used for a microcontroller with an SPI interface, although it can also be used for a DSP. The microcontroller SPI interface may be programmed for CPOL = 0 (serial clock referenced to ground) and CPHA = 1 (data is valid on the falling edge of serial clock). At least one falling edge transition on SCLK is needed whenever CS is brought high.
D Control via FS--The MSB is presented after the rising edge of FS. The falling edge of FS starts the cycle.
The MSB may be read on the first falling edge of SCLK after FS is low. This is the typical configuration when the ADC is the only device on the DSP serial port.
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control and timing (continued)
D Control via both CS and FS--The MSB is presented after the falling edge of CS. The falling edge of FS starts
the sampling cycle. The MSB may be read on the first falling SCLK edge after FS is low. Output data changes on the rising edge of SCLK. This control via CS and FS is typically used for multiple devices connected to a TMS320 DSP. TLC2552 and TLC2555 All control is provided using CS (pin 1) on the TLC2552 and TLC2555. The cycle starts on the falling edge transition provided by either a CS signal from an SPI microcontroller or FS signal from a TMS320 DSP. Timing is similar to the TLC2551, with control via CS only.
TLC2552 channel MUX reset cycle
The TLC2552 uses CS to reset the analog input multiplexer (MUX). A short active CS cycle (4 to 7 SCLKs) resets the MUX to AIN0. When the CS cycle time is greater than 7 SCLKs in duration, as is the case for a complete conversion cycle, (CS is low for 16 SCLKs plus maximum conversion time), the MUX toggles to the next channel (see Figure 4 for timing).
sampling
The converter sample time is 12 SCLKs in duration, beginning on the fifth SCLK received after the converter has received a high-to-low CS transition (or a high-to-low FS transition for the TLC2551).
conversion
The TLC2551, TLC2552, and TLC2555 completes conversion in the following manner. The conversion starts after the 16th SCLK falling edge during the cycle and requires 28 SCLKs to complete. Enough time for conversion should be allowed before a rising CS or FS edge so that no conversion is terminated prematurely. TLC2552 input channel selection is toggled on each rising CS edge. The MUX channel can be reset to AIN0 via CS as described earlier and in Figure 4. The input is sampled for 12 SCLKs and converted. The result is presented on SDO during the next cycle. Care should also be taken to allow enough time between samples to avoid prematurely terminating the cycle, which occurs on a rising CS transition if the conversion is not complete. The SDO data presented during a cycle is the result of the conversion of the sample taken during the previous cycle.
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TLC2551, TLC2552, TLC2555 5-V, LOW-POWER, 12-BIT, 175/360 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276D - MARCH 2000 - REVISED MAY 2003
timing diagrams/conversion cycles
1 2 3 4 5 6 7 12 13 14 15 16 44 1
SCLK CS FS
t(sample) tc t(powerdown)
SDO
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD0
Figure 2. TLC2551 Timing: Control via CS (FS = 1)
1 2 3 4 5 6 12 13 14 15 16
SCLK CS FS
t(sample) t(powerdown)
SDO
OD11
OD10
OD9
OD8
OD7
OD6
OD0
Figure 3. TLC2551 Timing: Control via CS and FS or FS Only
1 2 3 4 5 1 4 12 16 44 1
SCLK
>8 SCLKs, MUX Toggles to AIN1
CS
<8 SCLKs, MUX Resets to AIN0
t(sample) tc
SDO
Figure 4. TLC2552 Reset Timing
6 7 12 13 14 15 16 44
1
2
3
4
5
SCLK CS
t(sample)
OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD0
Figure 5. TLC2552 and TLC2555 Timing
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SDO
IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII
OD11
OD0
1
tc
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III
IIIIIIIIIIIIIII IIIIIIIIIIIIIII
44 1 tc 4 12 16 t(powerdown) t(sample) AIN0 Result tc t(powerdown)
OD11 OD10 OD9
I I I I I I I IIIIII
TLC2551, TLC2552, TLC2555 5-V, LOW-POWER, 12-BIT, 175/360 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276D - MARCH 2000 - REVISED MAY 2003
using CS as the FS input
When interfacing the TLC2551 with the TMS320 DSP, the FSR signal from the DSP may be connected to the CS input if this is the only device on the serial port. This connection saves one output terminal from the DSP. (Output data changes on the falling edge of SCLK. This is the default configuration for the TLC2552 and TLC2555). SCLK and conversion speed The SCLK input can range in frequency from 100 kHz to 20 MHz. The required number of conversion clocks is 14. The conversion clock for the ADC is SCLK/2 which translates to 28 SCLK cycles to perform a conversion. For a 15-MHz SCLK, the minimum total cycle time is given by: 16x(1/15 M)+14x(1/7.5 M)+1 SCLK = 3.0 s. An additional SCLK is added to account for the required CS or FS high time. These times specify the minimum cycle time for an active CS or FS signal. If violated, the conversion terminates, invalidating the next data output cycle. Table 1 gives the maximum SCLK frequency for a given operational mode. control via pin 1 (CS, SPI interface) All devices are compatible with this mode of operation. A falling CS initiates the cycle. (For TLC2551, the FS input is tied to VDD.) CS remains low for the entire cycle time (sample + convert + 1 SCLK) and can then be released.
NOTE: IMPORTANT: A single SCLK is required whenever CS is high.
control via pin 1 (CS, DSP interface) All devices are compatible with this mode of operation. The FS signal from a DSP is connected directly to the CS input of the ADC. A falling edge on the CS input initiates the cycle. (For TLC2551, the FS input can be tied to VDD, although better performance can be achieved by using the FS input for control. Refer to the control via pin 1 and pin 7 (CS and FS or FS only, DSP interface) section. The CS input should remain low for the entire cycle time (sample + convert + 1 SCLK) and can then be released.
NOTE: IMPORTANT: A single SCLK is required whenever CS is high. This requirement is usually of little consequence since SCLK is normally always present when interfacing with a DSP.
control via pin 1 and pin 7 (CS and FS or FS only, DSP interface) Only the TLC2551 is compatible with this mode of operation. The CS input to the ADC can be controlled via a general-purpose I/O pin from the DSP. The FS signal from the DSP is connected directly to the FS input of the ADC. A falling edge on CS, if used, releases the MSB on the SDO output. When CS is not used, the rising FS edge releases the MSB. The falling edge on the FS input while SCLK is high initiates the cycle. The CS and FS inputs should remain low for the entire cycle time (sample + convert + 1 SCLK) and can then be released. reference voltage An external reference is applied via VREF. The voltage level applied to this pin establishes the upper limit of the analog inputs to produce a full-scale reading. The value of VREF and the analog input must not exceed the positive supply or be less than GND, consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher than VREF and at zero when the input signal is equal to or lower than GND. powerdown and powerup Autopower down is built into these devices in order to reduce power consumption. The actual power savings depends on the inactive time between cycles and the power supply (loading) decoupling/storage capacitors. Power-down takes effect immediately after the conversion is complete. This is fast enough to provide some power savings between cycles with longer than 1 SCLK inactive time. The device power goes down to 8 A within 0.5 s. To achieve the lowest power-down current (deep powerdown) of 1 A requires 2-ms inactive time between cycles. The power-down state is initiated at the end of conversion. These devices wake up immediately at the next falling edge of CS or the rising edge of FS.
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SLAS276D - MARCH 2000 - REVISED MAY 2003
ICC With 1-F/0.1-F Capacitor Between Supply and Ground VDD = 5 V 3.5 mA 0.5 S 2 mS
8 A
1 A
t(Powerdown) - Powerdown time - S
Table 1. Modes of Operation and Data Throughput
CONTROL PIN(s)/DEVICE CS control only (TLC2551 only) For SPI DSP interface CS and FS control (TLC2551 only) DSP interface See Figure 21(a). See Figure 21(b). See Figure 21(c). 20 400 MAX SCLK (MHz) (50/50 duty cycle) VDD = 4.5 V 15 8 APPROXIMATE CONVERSION THROUGHPUT (ksps) VDD = 4.5 V 333 175
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, GND to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6.5 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD+ 0.3 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 150C Operating free-air temperature range, TA: C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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recommended operating conditions
MIN Supply voltage, VDD Positive external reference voltage input, VREFP (see Note 1) Analog input voltage (see Note 1) High level control input voltage, VIH Low-level control input voltage, VIL Setup time, CS falling edge before first SCLK falling edge, tsu(CSL-SCLKL) Hold time, CS falling edge after SCLK falling edge, th(SCLKL-CSL) VDD = REF = 4.5 V 40 5 0.5 0.35 0.65 100 0.75 50 0.4 0.4 0.05 4 7 40 1 11 30 28 See Note 2 TLC2551/2/5C TLC2551/2/5I 300 0 -40 70 85 10000 0.6 0.6 7 4.5 2 0 2.1 0.6 NOM 5 MAX 5.5 VDD VDD UNIT V V V V V ns ns SCLKs SCLKs SCLKs ns SCLKs ns SCLKs SCLKs s SCLKs ns ns ns ns SCLKs ns C
Delay time, delay from CS falling edge to FS rising edge td(CSL-FSH) (TLC2551 only) Setup time, FS rising edge before SCLK falling edge, tsu(FSH-SCLKL) (TLC2551 only) Hold time, FS hold high after SCLK falling edge, th(SCLKL-FSL) (TLC2551 only) Pulse width CS high time, tw(H_CS) Pulse width FS high time, tw(H_FS) (TLC2551 only) SCLK cycle time, VDD = 5.5 V to 4.5 V, tc(SCLK) (maximum tolerance of 40/60 duty cycle) Pulse width low time, tw(L_SCLK) Pulse width high time, tw(H_SCLK) Hold time, hold from end of conversion to CS high, th(EOC-CSH) (EOC is internal, indicates end of conversion time, tc) Active CS cycle time to reset internal MUX to AIN0, t(Reset cycle) (TLC2552 only) Delay time, delay from CS falling edge to SDO valid, td(CSL-SDOV) Delay time, delay from FS falling edge to SDO valid, td(FSL-SDOV) (TLC2551 only) Delay time, delay from SCLK rising edge to SDO valid, td(SCLKH-SDOV) Delay time, delay from 17th SCLK rising edge to SDO 3-state, td(SCLK17H-SDOZ) Conversion time, tc Sampling time, t(sample) Operating free air temperature TA free-air temperature, VDD = REF = 4.5 V, 25-pF load VDD = REF = 4.5 V, 25-pF load VDD = REF = 4.5 V, 25-pF load VDD = REF = 4.5 V, 25-pF load
NOTES: 1. Analog input voltages greater than that applied to VREF convert as all ones (111111111111), while input voltages less than that applied to GND convert as all zeros(000000000000). 2. Minimal t(sample) is given by 0.9 x 50 pF x (RS + 0.5 k), where RS is the source output impedance.
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electrical characteristics over recommended operating free-air temperature range,
VDD = VREF = 4.5 V to 5.5 V, (unless otherwise noted)
PARAMETER VOH VOL IOZ IIH IIL ICC High-level output voltage Low-level output voltage Off-state out ut current output (high-impedance-state) High-level input current Low-level input current Operating supply current Autopower-down current t(powerdown) 0.5 s Deep autopower-down current t(powerdown) 2 ms Selected analog input channel in ut leakage current Ci Input capacitance TEST CONDITIONS VDD = 5.5 V, IOH = -0.2 mA at 30-pF load VDD = 5.5 V, IOL = 0.8 mA at 30-pF load VO = VDD VO = 0 VI = VDD VI = 0 V CS at 0 V, VDD = 4.5 V to 5.5 V CS = VDD MIN 2.4 0.4 1 -1 0.005 -0.00 5 3 2.5 -2.5 2.5 2.5 3.5 8 A A 1 1 -1 20 45 5 50 25 500 pF A A TYP MAX UNIT V V A A A A mA
ICC(AUTOPWDN)
For all digital inputs, 0.3 0.3 V, 0 VI 0 3 V or VI VDD- 0 3 V SCLK = 0, VDD = 4.5 V to 5.5 V, Ext ref Selected channel at VDD Selected channel at 0 V Analog inputs Control Inputs VDD = 5.5 V
Input on resistance All typical values are at VDD = 5 V, TA = 25C.
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ac specifications (fi = 20 kHz)
PARAMETER SINAD THD ENOB SFDR Signal-to-noise ratio + distortion Total harmonic distortion Effective number of bits Spurious free dynamic range Full-power bandwidth, -3 dB Full-power bandwidth, -1 dB TEST CONDITIONS 400 KSPS, VDD = VREF = 5 V 400 KSPS, VDD = VREF = 5 V 400 KSPS, VDD = VREF = 5 V 400 KSPS, VDD = VREF = 5 V MIN 70 TYP 72 -84 11.8 -84 1 500 -80 -80 MAX UNIT dB dB bits dB MHz kHz
Analog Input
external reference specifications
PARAMETER Reference input voltage Reference input impedance Reference current Reference input capacitance VREF Reference voltage TEST CONDITIONS VDD = 4.5 V to 5.5 V CS = 1, VDD = 5.5 V 55 VDD = VREF = 5.5 V CS = 1, VDD = VREF = 5.5 V 55 VDD = 4.5 V to 5.5 V CS = 0, SCLK = 0 SCLK = 20 MHz 5 20 45 CS = 0, SCLK = 0 SCLK = 20 MHz MIN 2 100 20 25 100 400 15 50 VDD pF V TYP MAX VDD UNIT V M k A
dc specification, VDD = VREF = 4.5 V to 5.5 V, SCLK frequency = 20 MHz (unless otherwise noted)
PARAMETER INL DNL EO EG Et Integral linearity error (see Note 4) Differential linearity error Offset error (see Note 5) Gain error (see Note 5) Total unadjusted error (see Note 6) See Note 3 TLC2551/52 See Note 3 See Note 3 See Note 3 TLC2555 TLC2551/52 TLC2555 TLC2551/52 TLC2555 TEST CONDITIONS MIN TYP 0.6 0.5 MAX 1 1 1.5 2.5 2 5 2 5 UNIT LSB LSB LSB LSB LSB
NOTES: 3. Analog input voltages greater than that applied to VREF convert as all ones (111111111111). 4. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics. 5. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference between 111111111111 and the converted output for full-scale input voltage. 6. Total unadjusted error comprises linearity, zero, and full-scale errors.
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TLC2551, TLC2552, TLC2555 5-V, LOW-POWER, 12-BIT, 175/360 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276D - MARCH 2000 - REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
t(sample) tw(H_SCLK) VIH 1 2 4 12 16 tc 44
SCLK
VIL tsu(CSL-SCLKL) tw(L_SCLK) t(powerdown)
CS
th(SCLKL-FSL) tsu(FSH-SCLKL) td(CSL-FSH) td(SCLKH-SDOV) tw(H_CS) th(EOC-CSH)
FS
tw(H_FS) td(SCLK17H-SDOZ)
OD8 OD0
SDO
OD11
td(CSL-SDOV)
Figure 6. TLC2551 Critical Timing (Control via CS and FS or FS only)
tsu(CSL-SCLKL) 1 2 4 12 16
SCLK
CS
td(SCLKH-SDOV) td(SCLK17H-SDOZ)
OD0
SDO
OD11
OD10
OD9
td(CSL-SDOV)
Figure 7. TLC2551 Critical Timing (Control via CS only, FS = 1)
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IIIII IIIII
t(sample) tc 44 t(powerdown) th(EOC-CSH)
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TLC2551, TLC2552, TLC2555 5-V, LOW-POWER, 12-BIT, 175/360 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
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PARAMETER MEASUREMENT INFORMATION
t(sample) tc 1 1 4 12 16 44
SCLK
t(reset cycle) MUX = AIN0 tw(H_CS) td(CSL-SDOV) td(SCLKH-SDOV)
CS
th(EOC-CSH)
SDO
OD11
OD0
td(CSL-SDOV)
Figure 8. TLC2552 Reset Cycle Critical Timing
tw(H_SCLK) VIH 1 2 4 12
t(sample) 16
SCLK
VIL th(SCLKL-CSL) tw(L_SCLK) t(powerdown) tsu(CSL-SCLKL)
CS
tw(H_CS) td(SCLKH-SDOV) td(SCLK17H-SDOZ) th(EOC-CSH)
SDO
OD11
OD8
OD0
td(CSL-SDOV)
Figure 9. TLC2552 and TLC2555 Conversion Cycle Critical Timing
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IIIII IIIII IIIII IIIII
IIII IIII
OD11
td(SCLK17H-SDOZ)
tc 44
13
TLC2551, TLC2552, TLC2555 5-V, LOW-POWER, 12-BIT, 175/360 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276D - MARCH 2000 - REVISED MAY 2003
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE
0.7 VDD = REF = 5.5 V 400 KSPS DNL - Differential Nonlinearity - LSB INL - Integral Nonlinearity - LSB 0.4 VDD = REF = 5.5 V 400 KSPS
DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE
0.65
0.35
0.6 -40
25 TA - Free-Air Temperature - C
90
0.3 -40
25 TA - Free-Air Temperature - C
90
Figure 10
OFFSET ERROR vs FREE-AIR TEMPERATURE
0.5 VDD = REF = 5.5 V 400 KSPS 0.9
Figure 11
GAIN ERROR vs FREE-AIR TEMPERATURE
VDD = REF = 5.5 V 400 KSPS 0.85
Offset Error - LSB
0.45
Gain Error - LSB 25 TA - Free-Air Temperature - C 90
0.8
0.75
0.4 -40
0.7 -40
25 TA - Free-Air Temperature - C
90
Figure 12
Figure 13
14
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLC2551, TLC2552, TLC2555 5-V, LOW-POWER, 12-BIT, 175/360 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276D - MARCH 2000 - REVISED MAY 2003
TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs FREE-AIR TEMPERATURE
3.1 VDD = REF = 5.5 V 400 KSPS
Supply Current - mA
3.05
3 -40
25 TA - Free-Air Temperature - C
90
Figure 14
DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODES
DNL - Differential Nonlinearity - LSB 1 VDD = REF = 5 V 400 KSPS 0.5
0
-0.5
-1 1 Digital Output Codes 4094
Figure 15
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
15
TLC2551, TLC2552, TLC2555 5-V, LOW-POWER, 12-BIT, 175/360 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276D - MARCH 2000 - REVISED MAY 2003
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODES
INL - Integral Nonlinearity - LSB 1 VDD = REF = 5 V 400 KSPS 0.5
0
-0.5
-1 1 Digital Output Codes 4094
Figure 16
2048 POINTS FAST FOURIER TRANSFORM (FFT)
0 -20 Magnitude - dB -40 -60 -80 -100 -120 -140 -160 0 20 40 60 80 100 120 140 160 180 200 VDD = REF = 5.5 V 400 KSPS fi = 20 kHz
f - Input Frequency - KHz
Figure 17
16
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLC2551, TLC2552, TLC2555 5-V, LOW-POWER, 12-BIT, 175/360 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276D - MARCH 2000 - REVISED MAY 2003
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY
75 SINAD - Signal-To-Noise and Distortion - dB ENOB - Effective Number of Bits - Bits VDD = REF = 5.5 V 400 KSPS 73 12 VDD = REF = 5.5 V 400 KSPS 11.5
EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY
71
11
69
10.5
67
65 0 20 40 60 80 100 120 140 160 180 200 f - Input Frequency - KHz
10 0 20 40 60 80 100 120 140 160 180 200 f - Input Frequency - KHz
Figure 18
TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY
-65 THD - Total Harmonic Distortion - dB VDD = REF = 5.5 V 400 KSPS -70
Figure 19
-75
-80
-85
-90 0 20 40 60 80 100 120 140 160 180 200 f - Input Frequency - KHz
Figure 20
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
17
TLC2551, TLC2552, TLC2555 5-V, LOW-POWER, 12-BIT, 175/360 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276D - MARCH 2000 - REVISED MAY 2003
APPLICATION INFORMATION
VDD 10 k TLC2551 FS SDO CS SCLK GND VDD AIN VREF EXT Reference (a) VDD 10 k TLC2551 FS SDO SCLK CS GND VREF EXT Reference (b) VDD TLC2551 FSX FSR DR CLKX CLKR GPIO DSP CS GND VREF EXT Reference (c) FS SDO SCLK AIN VDD VDD VDD VDD
MISO SS SCLK SPI PORT
DR CLKX CLKR FSX FSR DSP
AIN
Figure 21. Typical TLC2551 Interface to a TMS320 DSP
18
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLC2551, TLC2552, TLC2555 5-V, LOW-POWER, 12-BIT, 175/360 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276D - MARCH 2000 - REVISED MAY 2003
APPLICATION INFORMATION
VDD
TMS320 FSX FSR DR CLKR CLKX DSP
10 k
10 k VDD CS SDO SCLK VREF
EXT Reference
TLC2552/55 AIN 0/AIN (+) AIN 1/AIN (-)
GND For TLC2555 only
Figure 22. Typical TLC2552/55 Interface to a TMS320 DSP
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
19
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