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TLV5616C, TLV5616I 2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS152C - DECEMBER 1997 - REVISED NOVEMBER 2002
D D D D D D D
12-Bit Voltage Output DAC Programmable Settling Time vs Power Consumption 3 s in Fast Mode 9 s in Slow Mode Ultra Low Power Consumption: 900 W Typ in Slow Mode at 3 V 2.1 mW Typ in Fast Mode at 3 V Differential Nonlinearity . . . <0.5 LSB Typ Compatible With TMS320 and SPI Serial Ports Power-Down Mode (10 nA) Buffered High-Impedance Reference Input
D D D D D D D D
Voltage Output Range . . . 2 Times the Reference Input Voltage Monotonic Over Temperature Available in MSOP Package
applications
Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices
description
The TLV5616 is a 12-bit voltage output digital-to-analog converter (DAC) with a flexible 4-wire serial interface. The 4-wire serial interface allows glueless interface to TMS320, SPI, QSPI, and Microwire serial ports. The TLV5616 is programmed with a 16-bit serial string containing 4 control and 12 data bits. Developed for a wide range of supply voltages, the TLV5616 can operate from 2.7 V to 5.5 V.
D, DGK, OR P PACKAGE (TOP VIEW)
DIN SCLK CS FS
1 2 3 4
8 7 6 5
VDD OUT REFIN AGND
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need for a low source impedance drive to the terminal. Implemented with a CMOS process, the TLV5616 is designed for single supply operation from 2.7 V to 5.5 V. The device is available in an 8-terminal SOIC package. The TLV5616C is characterized for operation from 0C to 70C. The TLV5616I is characterized for operation from - 40C to 85C.
AVAILABLE OPTIONS PACKAGE TA 0C to 70C SMALL OUTLINE (D) TLV5616CD MSOP (DGK) TLV5616CDGK PLASTIC DIP (P) TLV5616CP TLV5616IP
- 40C to 85C TLV5616ID TLV5616IDGK Available in tape and reel as the TLV5616CDR and the TLV5616IDR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
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TLV5616C, TLV5616I 2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS152C - DECEMBER 1997 - REVISED NOVEMBER 2002
functional block diagram
_ 6 REFIN +
DIN
1
Serial Input Register
14
12 12-Bit Data Latch 12 x2 7 OUT
SCLK CS FS
2 3 4 16 Cycle Timer Update
Power-On Reset
2 Speed/Power-Down Logic
Terminal Functions
TERMINAL NAME AGND CS DIN FS OUT REFIN SCLK VDD NO. 5 3 1 4 7 6 2 8 I I I O I I I/O Analog ground Chip select. Digital input used to enable and disable inputs, active low. Serial digital data input Frame sync. Digital input used for 4-wire serial interfaces such as the TMS320 DSP interface. DAC analog output Reference analog input voltage Serial digital clock input Positive power supply DESCRIPTION
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TLV5616C, TLV5616I 2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS152C - DECEMBER 1997 - REVISED NOVEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5616C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C TLV5616I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN Supply voltage VDD voltage, High-level High level digital input voltage, VIH voltage Low-level Low level digital input voltage, VIL voltage Reference voltage, Vref to REFIN terminal Reference voltage, Vref to REFIN terminal Load resistance, RL Load capacitance, CL Clock frequency, fCLK Operating free-air temperature, TA free air temperature TLV5616C TLV5616I 0 - 40 VDD = 5 V VDD = 3 V DVDD = 2.7 V DVDD = 5.5 V DVDD = 2.7 V DVDD = 5.5 V VDD = 5 V (see Note 1) VDD = 3 V (see Note 1) AGND AGND 2 2.048 1.024 10 100 20 70 85 4.5 2.7 2 2.4 0.6 1 VDD -1.5 VDD - 1.5 NOM 5 3 MAX 5.5 3.3 UNIT V V V V V V V V k pF MHz C C
NOTE 1: Due to the x2 output buffer, a reference input voltage VDD/2 causes clipping of the transfer function.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
power supply
PARAMETER TEST CONDITIONS VDD = 5 V, VREF = 2.048 V, No load, All inputs = AGND or VDD, DAC latch = 0x800 VDD = 3 V, VREF = 1.024 V No load, All inputs = AGND or VDD, DAC latch = 0x800 Fast Slow Fast Slow MIN TYP 0.9 0.4 0.7 0.3 10 See Note 2 See Note 3 -80 -80 2 MAX 1.35 0.6 1.1 0.45 UNIT mA mA mA mA nA dB V
IDD
Power supply current
Power down supply current (see Figure 12) PSRR Power supply rejection ratio Power on threshold voltage, POR NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) - EZS(VDDmin))/VDDmax] 3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) - EG(VDDmin))/VDDmax] Zero scale Full scale
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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)
static DAC specifications RL = 10 k, CL = 100 pF
PARAMETER Resolution INL DNL EZS Integral nonlinearity Differential nonlinearity Zero-scale error (offset error at zero scale) Zero-scale-error temperature coefficient EG Gain error Gain-error temperature coefficient See Note 4 See Note 5 See Note 6 See Note 7 See Note 8 See Note 9 10 10 0.6 TEST CONDITIONS MIN TYP 12 1.9 0.5 MAX 12 4 1 10 UNIT bits LSB LSB mV ppm/C % of FS voltage ppm/C
NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. 5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) - EZS (Tmin)]/Vref x 106/(Tmax - Tmin). 8. Gain error is the deviation from the ideal output (2Vref - 1 LSB) with an output load of 10 k excluding the effects of the zero-error. 9. Gain temperature coefficient is given by: EG TC = [EG(Tmax) - EG (Tmin)]/Vref x 106/(Tmax - Tmin).
output specifications
PARAMETER VO Voltage output range Output load regulation accuracy RL = 10 k RL = 2 k, vs 10 k TEST CONDITIONS MIN 0 0.1 TYP MAX AVDD-0.1 0.25 UNIT V % of FS voltage
reference input (REF)
PARAMETER VI RI CI Input voltage range Input resistance Input capacitance Reference input bandwidth Reference feed through REFIN = 0.2 Vpp + 1.024 V dc 02 1 024 REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) Slow Fast TEST CONDITIONS MIN 0 10 5 525 1.3 -75 TYP MAX VDD-1.5 UNIT V M pF kHz MHz dB
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
PARAMETER IIH IIL CI High-level digital input current Low-level digital input current Input capacitance VI = VDD VI = 0 V 3 TEST CONDITIONS MIN TYP MAX 1 1 UNIT A A pF
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TLV5616C, TLV5616I 2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS152C - DECEMBER 1997 - REVISED NOVEMBER 2002
operating characteristics over recommended operating free-air temperature range (unless otherwise noted)
analog output dynamic performance
PARAMETER ts(FS) (FS) ts(CC) (CC) SR Output settling time, full scale time Output settling time, code to code time Slew rate Glitch energy S/N S/(N+D) THD Signal to noise Signal to noise + distortion Total harmonic distortion Spurious free dynamic range fs = 400 KSPS fout = 1.1 kHz, k, CL = 100 pF pF, RL = 10 k BW = 20 kHz TEST CONDITIONS RL = 10 k, , See Note 11 RL = 10 k, , See Note 12 RL = 10 k, , See Note 13 CL = 100 pF, CL = 100 pF, CL = 100 pF, , Fast Slow Fast Slow Fast Slow MIN TYP 3 9 1 2 3.6 0.9 10 74 66 -68 70 MAX 5.5 20 UNIT s s s V/s nV-s dB dB dB dB
Code transition from 0x7FF to 0x800
NOTES: 11. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of 0x080 to 0x3FF or 0x3FF to 0x080. Not tested, ensured by design. 12. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of one count. Code change from 0x1FF to 0x200. Not tested, ensured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
digital input timing requirements
MIN tsu(CS-FS) tsu(FS-CK) tsu(C16-FS) tsu(C16-CS) twH twL tsu(D) th(D) twH(FS) Setup time, CS low before FS Setup time, FS low before first negative SCLK edge Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising edge of FS Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup time is between the FS rising edge and CS rising edge. Pulse duration, SCLK high Pulse duration, SCLK low Setup time, data ready before SCLK falling edge Hold time, data held valid after SCLK falling edge Pulse duration, FS high 10 8 10 NOM MAX UNIT ns ns ns
10 25 25 8 5 20
ns ns ns ns ns ns
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SLAS152C - DECEMBER 1997 - REVISED NOVEMBER 2002
PARAMETER MEASUREMENT INFORMATION
twL SCLK twH
1
2 th(D) D15 D14
3
4
5
15
16
tsu(D)
DIN
D13
D12
D1
D0
tsu(FS-CK)
tsu(CS-FS)
tsu(C16-CS)
CS twH(FS) FS tsu(C16-FS)
Figure 1. Timing Diagram
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IIII IIII III III
IIII IIII IIIII IIIII
TLV5616C, TLV5616I 2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS152C - DECEMBER 1997 - REVISED NOVEMBER 2002
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE vs LOAD CURRENT
2.004 3 V Slow Mode, SOURCE 2.002 2 3 V Fast Mode, SOURCE VDD = 3 V, Vref = 1 V, Full Scale 4.01 4.005 4 5 V Fast Mode, SOURCE 3.995 3.99 5 V Slow Mode, SOURCE
OUTPUT VOLTAGE vs LOAD CURRENT
VDD = 5 V, Vref = 2 V, Full Scale
VO - Output Voltage - V
1.998 1.996 1.994 1.992 1.990 0 0.01 0.02 0.05 0.1 0.2 0.5 1 2 4 Load Current - mA
VO - Output Voltage - V
3.985
3.98 3.975 0 0.02 0.04 0.1 0.2 0.4 1 Load Current - mA 2 4
Figure 2
OUTPUT VOLTAGE vs LOAD CURRENT
0.2 0.18 0.16 VO - Output Voltage - V VO - Output Voltage - V 0.14 3 V Slow Mode, SINK 0.12 0.1 0.08 3 V Fast Mode, SINK 0.06 0.04 0.05 0.02 0 0 0.01 0.02 0.05 0.1 0.2 0.5 Load Current - mA 1 2 0 0 0.25 VDD = 3 V, Vref = 1 V, Zero Code 0.35 0.3 VDD = 5 V, Vref = 2 V, Zero Code
Figure 3
OUTPUT VOLTAGE vs LOAD CURRENT
5 V Slow Mode, SINK 0.2 0.15 5 V Fast Mode, SINK 0.1
0.02 0.04 0.1 0.2 0.4 1 Load Current - mA
2
4
Figure 4
Figure 5
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs FREE-AIR TEMPERATURE
1 VDD = 3 V, Vref = 1 V, Full Scale I DD - Supply Current - mA 0.8 Fast Mode 0.6 I DD - Supply Current - mA 0.8 1 VDD = 5 V, Vref = 2 V, Full Scale Fast Mode
SUPPLY CURRENT vs FREE-AIR TEMPERATURE
0.6
0.4
0.4 Slow Mode
Slow Mode 0.2 -55 -40 85 -25 0 25 40 70 TA - Free-Air Temperature - C 125 0.2 85 -55 -40 -25 0 25 40 70 TA - Free-Air Temperature - C 125
Figure 6
TOTAL HARMONIC DISTORTION vs FREQUENCY
0 THD - Total Harmonic Distortion - dB -10 -20 -30 --40 -50 -60 Fast Mode -70 -80 0 5 10 20 30 50 100 f - Frequency - kHz Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale 0 THD - Total Harmonic Distortion - dB -10 -20 -30 --40 -50 -60
Figure 7
TOTAL HARMONIC DISTORTION vs FREQUENCY
Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale
Slow Mode -70 -80 0 5 10 20 30 50 100 f - Frequency - kHz
Figure 8
Figure 9
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TLV5616C, TLV5616I 2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS152C - DECEMBER 1997 - REVISED NOVEMBER 2002
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY
THD - Total Harmonic Distortion And Noise - dB Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale THD - Total Harmonic Distortion And Noise - dB 0 -10 -20 -30 --40 -50 Fast Mode -60 -70 -80 0 5 10 20 30 50 100 f - Frequency - kHz 0 -10 -20 -30 --40 -50 Slow Mode -60 -70 -80 0 5 10 20 30 50 100 f - Frequency - kHz Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale
TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY
Figure 10
SUPPLY CURRENT vs TIME (WHEN ENTERING POWER-DOWN MODE)
900 800 I DD - Supply Current - A 700 600 500 400 300 200 100 0 0 100 200 300 400 500 600 700 800 900 1000 T - Time - ns
Figure 11
Figure 12
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TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR
INL - Integral Nonlinearity Error - LSB 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 0 256 515 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 Digital Code
Figure 13
DNL - Differential Nonlinearity Error - LSB
DIFFERENTIAL NONLINEARITY ERROR
0.3 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 -0.45 -0.5 0
256
512 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 Digital Code
Figure 14
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APPLICATION INFORMATION general function
The TLV5616 is a 12-bit single supply DAC based on a resistor string architecture. The device consists of a serial interface, speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by external reference) is given by: 2 REF CODE [V] 2n where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n-1, where n = 12 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data format section. A power-on reset initially resets the internal latches to a defined state (all bits zero).
serial interface
Explanation of data transfer: First, the device has to be enabled with CS set to low. Then, a falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch which updates the voltage output to the new level. The serial interface of the TLV5616 can be used in two basic modes:
D D
Four wire (with chip select) Three wire (without chip select)
Using chip select (four wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). The interface is compatible with the TMS320 family. Figure 15 shows an example with two TLV5616s connected directly to a TMS320 DSP.
TLV5616 CS FS DIN SCLK TLV5616 CS FS DIN SCLK
TMS320 DSP XF0 XF1 FSX DX CLKX
Figure 15. TMS320 Interface
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APPLICATION INFORMATION serial interface (continued)
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows an example of how to connect the TLV5616 to a TMS320, SPI, or Microwire port using only three pins.
TMS320 DSP FSX DX CLKX TLV5616 FS DIN SCLK CS SPI SS MOSI SCLK TLV5616 FS DIN SCLK CS Microwire I/O SO SK TLV5616 FS DIN SCLK CS
Figure 16. Three-Wire Interface Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed to program the TLV5616. After the write operation(s), the DAC output is updated automatically on the next positive clock edge following the sixteenth falling clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by: f SCLKmax
+t
) twL(min) + 20 MHz wH(min)
1 1 16 t
The maximum update rate is: f UPDATEmax
+
wH(min)
) twL(min)
+ 1.25 MHz
The maximum update rate is a theoretical value for the serial interface, since the settling time of the TLV5616 has to be considered also.
data format
The 16-bit data word for the TLV5616 consists of two parts:
D D
D15 X
Control bits New DAC value
D14 SPD D13 PWR D12 X
(D15 . . . D12) (D11 . . . D0)
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
New DAC value (12 bits) 0 slow mode 0 normal operation
X: don't care SPD: Speed control bit. PWR: Power control bit.
1 fast mode 1 power down
In power-down mode, all amplifiers within the TLV5616 are disabled.
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APPLICATION INFORMATION TLV5616 interfaced to TMS320C203 DSP
hardware interfacing Figure 17 shows an example how to connect the TLV5616 to a TMS320C203 DSP. The serial interface of the TLV5616 is ideally suited to this configuration, using a maximum of four wires to make the necessary connections. In applications where only one synchronous serial peripheral is used, the interface can be simplified even further by pulling CS low all the time as shown in the figure.
TMS320C203 FS DX CLKX REF TLV5616 FS DIN SCLK OUT REFIN CS AGND RLOAD VDD
Figure 17. TLV5616 to DSP Interface software No setup procedure is needed to access the TLV5616. The output voltage can be set using just a single command.
out data_addr, SDTR
where data_addr points to an address location holding the control bits and the 12 data bits providing the output voltage data. SDTR is the address of the transmit FIFO of the synchronous serial port. The following code shows how to use the timer of the TMS320C203 as a time base to generate a voltage ramp with the TLV5616. A timer interrupt is generated every 205 s. The corresponding interrupt service routine increments the output code (stored at 0x0064) for the DAC, adds the DAC control bits to the four most significant bits, and writes the new code to the TLV5616. The resulting period of the saw waveform is: = 4096 x 205 E-6 s = 0.84 s
;*************************************************************************************** ;* Title : Ramp generation with TLV5616 * ;* Version : 1.0 * ;* DSP : TI TMS320C203 * ;* (1998) Texas Instruments Incorporated * ;*************************************************************************************** ;----------- I/O and memory mapped regs ------------ .include "regs.asm" ;----------- vectors ------------------------------- .ps 0h b start b INT1 b INT23 b TIM_ISR
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APPLICATION INFORMATION
;*************************************************************************************** ;* Main Program ;*************************************************************************************** .ps 1000h .entry start: ; disable interrupts setc INTM ; disable maskable interrupts splk #0ffffh, IFR splk #0004h, IMR ; set up the timer to interrupt ever 205uS splk #0000h, 60h splk #00FFh, 61h out 61h, PRD out 60h, TIM splk #0c2fh, 62h out 62h, TCR ; Configure SSP to use internal clock, internal frame sync and burst mode splk #0CC0Eh, 63h out 63h, SSPCR splk #0CC3Eh, 63h out 63h, SSPCR splk #0000h, 64h ; set initial DAC value ; enable maskable interrupts ;wait for interrupt
; enable interrupts clrc INTM ; loop forever! next: idle b next ; all else fails stop here done: b done
;hang there
;*************************************************************************************** ;* Interrupt Service Routines ;*************************************************************************************** INT1: ret ;do nothing and return INT23: TIM_ISR: lacl add and sacl or sacl out clrc ret .END 64h #1h #0FFFh 64h #4000h 65h 65h, SDTR intm ; ; ; ; ; ; ; restore counter value to ACC increment DAC value mask 4 MSBs store 12 bit counter value set DAC control bits store DAC value send data ret ;do nothing and return
; re-enable interrupts
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APPLICATION INFORMATION TLV5616 interfaced to MCS51 microcontroller
hardware interfacing Figure 18 shows an example of how to connect the TLV5616 to an MCS51 compatible microcontroller. The serial DAC input data and external control signals are sent via I/O port 3 of the controller. The serial data is sent on the RxD line, with the serial clock output on the TxD line. P3.4 and P3.5 are configured as outputs to provide the chip select and frame sync signals for the TLV5616.
MCS51 Controller RxD TxD P3.4 P3.5 REF TLV5616 SDIN SCLK CS FS OUT REFIN AGND RLOAD VDD
Figure 18. TLV5616 to MCS51 Controller Interface software The example program puts out a sine wave on the OUT pin. The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine fetches and writes the next sample to the DAC. The samples are stored in a lookup table, which describes one full period of a sine wave. The serial port of the controller is used in mode 0, which transmits 8 bits of data on RxD, accompanied by a synchronous clock on TxD. Two writes concatenated together are required to write a complete word to the TLV5616. The CS and FS signals are provided in the required fashion through control of I/O port 3, which has bit addressable outputs.
;*************************************************************************************** ;* Title : Ramp generation with TLV5616 * ;* Version : 1.0 * * ;* MCU : INTEL MCS51 ;* (1998) Texas Instruments Incorporated * ;*************************************************************************************** ;--------------------------------------------------------------------------------------- ; Program function declaration ;--------------------------------------------------------------------------------------- NAME MAIN ISR SINTBL VAR1 STACK GENSINE SEGMENT SEGMENT SEGMENT SEGMENT SEGMENT CODE CODE CODE DATA IDATA
;--------------------------------------------------------------------------------------- ; Code start at address 0, jump to start ;--------------------------------------------------------------------------------------- CSEG AT 0
MCS is a registered trademark of Intel Corporation
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SLAS152C - DECEMBER 1997 - REVISED NOVEMBER 2002
APPLICATION INFORMATION
LJMP start ; Execution starts at address 0 on power-up. ;--------------------------------------------------------------------------------------- ; Code in the timer0 interrupt vector ;--------------------------------------------------------------------------------------- CSEG AT 0BH LJMP timer0isr ; Jump vector for timer 0 interrupt is 000Bh ;--------------------------------------------------------------------------------------- ; Define program variables ;--------------------------------------------------------------------------------------- RSEG VAR1 rolling_ptr: DS 1 ;--------------------------------------------------------------------------------------- ; Interrupt service routine for timer 0 interrupts ;--------------------------------------------------------------------------------------- RSEG timer0isr: PUSH PUSH CLR CLR ; ; ; ; PSW ACC T0 T1 ; set CSB low ; set FS low ISR
The signal to be output on the dac is a sine function. One cycle of a sine wave is held in a table @ sinevals as 32 samples of msb, lsb pairs (64 bytes). The pointer, rolling_ptr, rolls round the table of samples incrementing by 2 bytes (1 sample) on each interrupt (at the end of this routine). DPTR,#sinevals ; set DPTR to the start of the table of sine signal values A,rolling_ptr ; ACC loaded with the pointer into the sine table A,@A+DPTR A, #00H SBUF,A ; get msb from the table ; set control bits ; send out msb of data word
MOV MOV MOVC ORL MOV
MOV A,rolling_ptr ; move rolling pointer in to ACC INC A ; increment ACC holding the rolling pointer MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC MSB_TX: JNB CLR MOV LSB_TX: JNB SETB CLR MOV INC INC ANL MOV SETB POP POP TI, MSB_TX TI SBUF,A TI, LSB_TX T1 TI A,rolling_ptr A A A,#03FH rolling_ptr,A T0 ACC PSW ; wait for transmit to complete ; clear for new transmit ; and send out the lsb ; wait for lsb transmit to complete ; set FS = 1 ; clear for new transmit ; load ACC with rolling pointer ; increment the ACC twice, to get next sample ; wrap back round to 0 if >64 ; move value held in ACC back to the rolling pointer ; CSB high
RETI ;------------------------------------------------------------------------------- ; Set up stack ;-------------------------------------------------------------------------------
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POST OFFICE BOX 655303
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TLV5616C, TLV5616I 2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS152C - DECEMBER 1997 - REVISED NOVEMBER 2002
APPLICATION INFORMATION
RSEG STACK DS 10h ; 16 Byte Stack! ;------------------------------------------------------------------------------- ; Main Program ;------------------------------------------------------------------------------- RSEG start: MOV CLR MOV MOV MOV SETB SETB SETB SETB MOV SETB MAIN SP,#STACK-1 A SCON,A TMOD,#02H TH0,#0C8H T1 T0 ET0 EA rolling_ptr,A TR0 ; first set Stack Pointer ; ; ; ; ; set set set set set serial port 0 to mode 0 timer 0 to mode 2 - auto-reload TH0 for 16.67 kHs interrupts FS = 1 CSB = 1
; enable timer 0 interrupts ; enable all interrupts ; set rolling pointer to 0 ; start timer 0
always: SJMP always ; while(1) ! RET ;------------------------------------------------------------------------------- ; Table of 32 sine wave samples used as DAC data ;------------------------------------------------------------------------------- RSEG SINTBL sinevals: DW 01000H DW 0903EH DW 05097H DW 0305CH DW 0B086H DW 070CAH DW 0F0E0H DW 0F06EH DW 0F039H DW 0F06EH DW 0F0E0H DW 070CAH DW 0B086H DW 0305CH DW 05097H DW 0903EH DW 01000H DW 06021H DW 0A0E8H DW 0C063H DW 040F9H DW 080B5H DW 0009FH DW 00051H DW 00026H DW 00051H DW 0009FH DW 080B5H DW 040F9H DW 0C063H DW 0A0E8H DW 06021H END
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TLV5616C, TLV5616I 2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS152C - DECEMBER 1997 - REVISED NOVEMBER 2002
APPLICATION INFORMATION linearity, offset, and gain error using single ended supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 19.
Output Voltage
0V Negative Offset DAC Code
Figure 19. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage.
power-supply bypassing and ground management
Printed-circuit boards that use separate analog and digital ground planes offer the best system performance. Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected together at the low-impedance power-supply source. The best ground connection may be achieved by connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground currents are well managed and there are negligible voltage drops across the ground plane. A 0.1-F ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the digital power supply. Figure 20 shows the ground plane layout and bypassing technique.
Analog Ground Plane 1 2 3 4 8 7 6 5 0.1 F
Figure 20. Power-Supply Bypassing
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POST OFFICE BOX 655303
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TLV5616C, TLV5616I 2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS152C - DECEMBER 1997 - REVISED NOVEMBER 2002
APPLICATION INFORMATION definitions of specifications and terminology
integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (EZS) Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (EG) Gain error is the error in slope of the DAC transfer function. signal-to-noise ratio + distortion (S/N+D) S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. total harmonic distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal and is expressed in decibels.
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TLV5616C, TLV5616I 2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS152C - DECEMBER 1997 - REVISED NOVEMBER 2002
MECHANICAL DATA
D (R-PDSO-G**)
14 PIN SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.010 (0,25) M
Gage Plane
0.010 (0,25) 1 A 7 0- 8 0.044 (1,12) 0.016 (0,40)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80) 4040047 / D 10/96
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLV5616C, TLV5616I 2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS152C - DECEMBER 1997 - REVISED NOVEMBER 2002
MECHANICAL DATA
DGK (R-PDSO-G8)
0,38 0,25 8 5
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,25 M
0,15 NOM 3,05 2,95 4,98 4,78
Gage Plane 0,25 1 3,05 2,95 4 0- 6 0,69 0,41
Seating Plane 1,07 MAX 0,15 0,05 0,10
4073329/B 04/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187
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21
TLV5616C, TLV5616I 2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS152C - DECEMBER 1997 - REVISED NOVEMBER 2002
MECHANICAL DATA
P (R-PDIP-T8)
0.400 (10,60) 0.355 (9,02) 8 5
PLASTIC DUAL-IN-LINE PACKAGE
0.260 (6,60) 0.240 (6,10)
1
4 0.070 (1,78) MAX 0.020 (0,51) MIN 0.310 (7,87) 0.290 (7,37)
0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0.010 (0,25) NOM
0- 15
4040082 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001
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Copyright 2002, Texas Instruments Incorporated

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