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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
D Highest-Performance Fixed-Point Digital
Signal Processors (DSPs) - 2-, 1.67-, 1.39-ns Instruction Cycle Time - 500-, 600-, 720-MHz Clock Rate - Eight 32-Bit Instructions/Cycle - Twenty-Eight Operations/Cycle - 4000, 4800, 5760 MIPS - Fully Software-Compatible With C62x - C6414/15/16 Devices Pin-Compatible VelociTI.2 Extensions to VelociTI Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x DSP Core - Eight Highly Independent Functional Units With VelociTI.2 Extensions: - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle - Non-Aligned Load-Store Architecture - 64 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional Instruction Set Features - Byte-Addressable (8-/16-/32-/64-Bit Data) - 8-Bit Overflow Protection - Bit-Field Extract, Set, Clear - Normalization, Saturation, Bit-Counting - VelociTI.2 Increased Orthogonality Viterbi Decoder Coprocessor (VCP) [C6416] - Supports Over 500 7.95-Kbps AMR - Programmable Code Parameters Turbo Decoder Coprocessor (TCP) [C6416] - Supports up to Six 2-Mbps 3GPP (6 Iterations) - Programmable Turbo Code and Decoding Parameters L1/L2 Memory Architecture - 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped) - 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative) - 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation)
D Two External Memory Interfaces (EMIFs)
- One 64-Bit (EMIFA), One 16-Bit (EMIFB) - Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO) - 1280M-Byte Total Addressable External Memory Space Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) Host-Port Interface (HPI) - User-Configurable Bus Width (32-/16-Bit) 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415/C6416 ] - Three PCI Bus Address Registers: Prefetchable Memory Non-Prefetchable Memory I/O - Four-Wire Serial EEPROM Interface - PCI Interrupt Request Under DSP Program Control - DSP Interrupt Via PCI I/O Cycle Three Multichannel Buffered Serial Ports - Direct Interface to T1/E1, MVIP, SCSA Framers - Up to 256 Channels Each - ST-Bus-Switching-, AC97-Compatible - Serial Peripheral Interface (SPI) Compatible (Motorola) Three 32-Bit General-Purpose Timers Universal Test and Operations PHY Interface for ATM (UTOPIA) [C6415/C6416] - UTOPIA Level 2 Slave ATM Controller - 8-Bit Transmit and Receive Operations up to 50 MHz per Direction - User-Defined Cell Format up to 64 Bytes Sixteen General-Purpose I/O (GPIO) Pins Flexible PLL Clock Generator IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 532-Pin Ball Grid Array (BGA) Package (GLZ and ZLZ Suffix), 0.8-mm Ball Pitch 0.13-m/6-Level Cu Metal Process (CMOS) 3.3-V I/Os, 1.2-V/1.25-V Internal (500 MHz) 3.3-V I/Os, 1.4-V Internal (600 and 720 MHz)
D
D D D
D
D
D D
D D
D
D D D D D D D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
This document contains information on products in more than one phase of development. The status of each device is indicated on the page(s) specifying its electrical characteristics.
Copyright 20034 Texas Instruments Incorporated
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
Table of Contents
revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 GLZ and ZLZ BGA package (bottom view) . . . . . . . . . . . . . . 5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 functional block and CPU (DSP core) diagram . . . . . . . . . . . 9 CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . 10 memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . . . 15 EDMA channel synchronization events . . . . . . . . . . . . . . . . 28 interrupt sources and interrupt selector . . . . . . . . . . . . . . . . 30 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 multiplexed pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 debugging considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 general-purpose input/output (GPIO) . . . . . . . . . . . . . . . . . . 71 power-down mode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 JTAG compatibility statement . . . . . . . . . . . . . EMIF device speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 75 75 76 76 bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature . 77 78 78 79
recommended clock and control signal transition behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 parameter measurement information . . . . . . . . . . . . . . . 80 input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 86 programmable synchronous interface timing . . . . . . . . 90 synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 95 HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . 109 host-port interface (HPI) timing . . . . . . . . . . . . . . . . . . . 110 peripheral component interconnect (PCI) timing [C6415 and C6416 only] . . . . . . . . . . . . . . . . . . . . 115 multichannel buffered serial port (McBSP) timing . . . . 118 UTOPIA slave timing [C6415 and C6416 only] . . . . . . 129 timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 general-purpose input/output (GPIO) port timing . . . . 133 JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
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REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS146J device-specific data sheet to make it an SPRS146K revision. Scope: Applicable updates to the C64x device family, specifically relating to the C6414, C6415, and C6416 devices, have been incorporated. Added C6414, C6415, and C6416 silicon revision 2.0 devices and associated device-specific information at the production data (PD) stage of development.
PAGE(S) NO. 1 5
ADDITIONS/CHANGES/DELETIONS Updated the 532-pin Ball Grid Array (BGA) Package bullet to list both GLZ and ZLZ suffix. Updated the package title to read: GLZ and ZLZ BGA package (bottom view) Updated Table 1, Characteristics of the C6414, C6415, and C6416 Processors as follows: BGA Package for C6414, C6415, AND C6416 added "and ZLZ" to (GLZ). Now reads 532-Pin BGA (GLZ and ZLZ). Product Status for C6414, C6415, AND C6416 updated to read PD and AI. Added new footnote containing AI information. For signal names XSP_CLK, XSP_DI, and XSP_DO, added (PCI_EN = 1). Added a last paragraph to discuss ZLZ package type. Table 30, TMS320C6414/C6415/C6416 Device Part Numbers (P/Ns) and Ordering Information Changed all non-extended temperature TMX... part numbers to TMS.... Figure 4, TMS320C64x DSP Device Nomenclature (Including the C6414, C6415, and C6416 Devices) Updated the package type to include ZLZ. Updated the head table row to read "GLZ and ZLZ PACKAGE - 23 x 23 mm BGA." Updated the paragraph below Figure 9 to reflect additional power-down mode information. Added the following paragraph below the paragraph that begins "TRST only needs to be..." RESET must be released only in order..." absolute maximum ratings over operating case temperature range Operating case temperature ranges, TC: (A version) Removed 14/15/16GLZ and GLZ so that the bracketed information now reads [A-5E0, A-6E3] For each Parameter NO. 5, changed Peak-to-Peak to Period. For each Parameter NO. 1, changed Cycle-to-cycle to Period. timing requirements for ECLKIN for EMIFA and EMIFB For Parameter NO. 5, changed Peak-to-Peak to Period. switching characteristics over recommended operating conditions for ECLKOUT1 for EMIFA and EMIFB modules For Parameter NO. 1, changed Cycle-to-cycle to Period.
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46 64 64 - 66
66
70 73 76
78
82 83 84
85 90
For Parameter NO. 1, changed Cycle-to-cycle to Period. switching characteristics over recommended operating conditions for programmable synchronous interface cycles for EMIFA module For Parameters 10 and 11, removed the overbar from EDx.
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PAGE(S) NO. 91
ADDITIONS/CHANGES/DELETIONS switching characteristics over recommneded operating conditions for programmable synchronous interface cycles for EMIFB module For Parameters 10 and 11, removed the overbar from EDx. switching characteristics over recommended operating conditions for synchronous DRAM cycles for EMIFA module For Parameters 9 and 10, removed the overbar from EDx. switching characteristics over recommended operating conditions for synchronous DRAM cycles for EMIFB module For Parameters 9 and 10, removed the overbar from EDx. Changed Parameter NO. 16 to NO. 18. Figure 36, Reset Timing Changed PCLK from 16 to 18. Updated Figure 46, PCI Serial EEPROM Interface Timing. timing requirements for McBSP Updated Parameter NO. 2 MIN value to "4P or 6.67." Added two footnotes: P = 1/CPU clock... Use whichever value is greater. Updated the footnotes listed in the table to reflect the new footnote order. switching characteristics over recommended operating conditions for McBSP Updated Parameter NO. 2 MIN value to "4P or 6.67." Added two footnotes: P = 1/CPU clock... Use whichever value is greater. Updated the footnotes listed in the table to reflect the new footnote order. switching characteristics over recommended operating conditions for JTAG test port Changed the MIN value from -3 to 0. MECHANICAL DATA Updated the left portion of the figure header to reflect ZLZ.
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GLZ and ZLZ BGA package (bottom view)
GLZ 532-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW )
AF AE AD AC AB AA Y W V U T R P N M L K J G F E D C B A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 H
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
description
The TMS320C64x DSPs (including the TMS320C6414, TMS320C6415, and TMS320C6416 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The TMS320C64x (C64x) device is based on the second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture (VelociTI.2) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64x is a code-compatible member of the C6000 DSP platform. With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units--two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-- with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI architecture. The C64x can produce four 32-bit multiply-accumulates (MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5760 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The C6416 device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 500 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to thirty-six 384-Kbps or six 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller. The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port (C6415/C6416 only); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI) [C6415/C6416 only]; a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals. The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.
TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation. All trademarks are the property of their respective owners. Throughout the remainder of this document, the TMS320C6414, TMS320C6415, and TMS320C6416 shall be referred to as TMS320C64x or C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414, C6415, or C6416. These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name.
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device characteristics
Table 1 provides an overview of the C6414, C6415, and C6416 DSPs. The table shows significant features of the C64x devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 1. Characteristics of the C6414, C6415, and C6416 Processors
HARDWARE FEATURES EMIFA (64-bit bus width) (default clock source = AECLKIN) Peripherals Not all peripherals pins are available at the same time. (For more details, see the Device Configuration section.) Peripheral performance is dependent on chip-level configuration. EMIFB (16-bit bus width) (default clock source = BECLKIN) EDMA (64 independent channels) HPI (32- or 16-bit user selectable) PCI (32-bit) [DeviceID Register value 0xA106] McBSPs (default internal clock source = CPU/4 clock frequency) UTOPIA (8-bit mode) 32-Bit Timers (default internal clock source = CPU/8 clock frequency) General-Purpose Input/Output 0 (GP0) VCP Decoder Coprocessors TCP Size (Bytes) On-Chip Memory Organization Control Status Register (CSR.[31:16]) Silicon Revision Identification Register (DEVICE_REV [19:16]) Address: 0x01B0 0200 MHz DEVICE_REV[19:16] 1111 0001 0010 or 0000 0011 C6414, C6415, AND C6416 1 1 1 1 (HPI16 or HPI32) 1 [C6415/C6416 only] 3 1 [C6415/C6416 only] 3 16 1 (C6416 only) 1 (C6416 only) 1056K 16K-Byte (16KB) L1 Program (L1P) Cache 16KB L1 Data (L1D) Cache 1024KB Unified Mapped RAM/Cache (L2) 0x0C01 Silicon Revision 1.03 or earlier 1.03 1.1 2.0 500, 600, 720 2 ns (C6414-5E0, C6415-5E0, C6416-5E0) and (C6414A-5E0, C6415A-5E0, C6416A-5E0) [500-MHz CPU, 100-MHz EMIF] 1.67 ns (C6414-6E3, C6415-6E3, C6416-6E3) and (C6414A-6E3, C6415A-6E3, C6416A-6E3) [600-MHz CPU, 133-MHz EMIFA] 1.39 ns (C6414-7E3, C6415-7E3, C6416-7E3) [720-MHz CPU, 133-MHz EMIFA] 1.2 V (-5E0) 1.25 V (A-5E0) 1.4 V (-6E3, A-6E3, -7E3) 3.3 V Bypass (x1), x6, x12 532-Pin BGA (GLZ and ZLZ) 0.13 m PD, AI
CPU ID + CPU Rev ID
Device_ID
Frequency
Cycle Time
ns
Voltage
Core (V) I/O (V)
PLL Options BGA Package Process Technology Product Status
CLKIN frequency multiplier 23 x 23 mm m Product Preview (PP), Advance Information (AI), Production Data (PD)
On these C64x devices, the rated EMIF speed affects only the SDRAM interface on EMIFA. For more detailed information, see the EMIF Device Speed section of this data sheet. The extended temperature devices for silicon revision 2.0 (C641x A-5E0, C641xA-6E3) are at the advance information (AI) stage of development. All other devices are at the Production Data (PD) stage of development.
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device compatibility
The C64x generation of devices has a diverse and powerful set of peripherals. The common peripheral set and pin-compatibility that the C6414, C6415, and C6416 devices offer lead to easier system designs and faster time to market. Table 2 identifies the peripherals and coprocessors that are available on the C6414, C6415, and C6416 devices. The C6414, C6415, and C6416 devices are pin-for-pin compatible, provided the following conditions are met:
D All devices are using the same peripherals.
The C6414 is pin-for-pin compatible with the C6415/C6416 when the PCI and UTOPIA peripherals on the C6415/C6416 are disabled. The C6415 is pin-for-pin compatible with the C6416 when they are in the same peripheral selection mode. [For more information on peripheral selection, see the Device Configurations section of this data sheet.]
D The BEA[9:7] pins are properly pulled up/down.
[For more details on the device-specific BEA[9:7] pin configurations, see the Terminal Functions table of this data sheet.]
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Table 2. Peripherals and Coprocessors Available on the C6414, C6415, and C6416 Devices
PERIPHERALS/COPROCESSORS EMIFA (64-bit bus width) EMIFB (16-bit bus width) EDMA (64 independent channels) HPI (32- or 16-bit user selectable) PCI (32-bit) [Specification v2.2] McBSPs (McBSP0, McBSP1, McBSP2) UTOPIA (8-bit mode) [Specification v1.0] Timers (32-bit) [TIMER0, TIMER1, TIMER2] GPIOs (GP[15:0]) VCP/TCP Coprocessors C6414 -- -- -- C6415 -- C6416
-- denotes peripheral/coprocessor is not available on this device. Not all peripherals pins are available at the same time. (For more details, see the Device Configuration section.)
For more detailed information on the device compatibility and similarities/differences among the C6414, C6415, and C6416 devices, see the How To Begin Development Today With the TMS320C6414, TMS320C6415, and TMS320C6416 DSPs application report (literature number SPRA718).
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functional block and CPU (DSP core) diagram
C64x Digital Signal Processor
VCP TCP SDRAM SBSRAM ZBT SRAM FIFO SRAM ROM/FLASH I/O Devices Timer 0 Timer 2
64 16
L1P Cache Direct-Mapped 16K Bytes Total
EMIF A EMIF B C64x DSP Core Instruction Fetch Instruction Dispatch Advanced Instruction Packet Instruction Decode Data Path A A Register File A31-A16 A15-A0 Data Path B B Register File B31-B16 B15-B0 Control Registers Control Logic Test
Timer 1
McBSP2
.L1 UTOPIA: Up to 400 Mbps Master ATMC McBSPs: Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs UTOPIA or Enhanced DMA Controller (64-channel) L2 Memory 1024K Bytes
.S1
.M1 .D1
.D2 .M2 .S2
.L2
Interrupt Control
McBSP1
McBSP0
L1D Cache 2-Way Set-Associative 16K Bytes Total
16
GPIO[8:0] GPIO[15:9]
32
HPI
or PCI PLL (x1, x6, x12) Power-Down Logic
Boot Configuration
Interrupt Selector
VCP and TCP decoder coprocessors are applicable to the C6416 device only. For the C6415 and C6416 devices, the UTOPIA peripheral is muxed with McBSP1, and the PCI peripheral is muxed with the HPI peripheral and the GPIO[15:9] port. For more details on the multiplexed pins of these peripherals, see the Device Configurations section of this data sheet.
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Advanced In-Circuit Emulation
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
CPU (DSP core) description
The CPU fetches VelociTI advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other VLIW architectures. The C64x VelociTI.2 extensions add enhancements to the TMS320C62x DSP VelociTI architecture. These enhancements include:
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D D D D D D
Register file enhancements Data path extensions Quad 8-bit and dual 16-bit extensions with data flow enhancements Additional functional unit hardware Increased orthogonality of the instruction set Additional instructions that reduce code size and increase register flexibility
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the packed 16-bit and 32-/40-bit fixed-point data types found in the C62x VelociTI VLIW architecture, the C64x register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP core) diagram, and Figure 1]. The four functional units on each side of the CPU can freely share the 32 registers belonging to that side. Additionally, each side features a "data cross path"--a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in the same execute packet. All functional units in the C64x CPU can access operands via the data cross path. Register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that register was updated in the previous clock cycle. In addition to the C62x DSP fixed-point instructions, the C64x DSP includes a comprehensive collection of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2 extensions allow the C64x CPU to operate directly on packed data to streamline data flow and increase instruction set efficiency. Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single instruction. And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits) with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 64 registers. Some registers, however, are singled out to support specific addressing modes or to hold the condition for conditional instructions (if the condition is not automatically "true").
TMS320C62x is a trademark of Texas Instruments.
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CPU (DSP core) description (continued)
The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two 16 x 16-bit multiplies or four 8 x 8-bit multiplies per clock cycle. The .M unit can also perform 16 x 32-bit multiply operations, dual 16 x 16-bit multiplies with add/subtract operations, and quad 8 x 8-bit multiplies with add operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies, and bidirectional variable shift hardware. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual 16-bit, and quad 8-bit operations. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. A C64x DSP device enhancement now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x/TMS320C67x DSP devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the C64x DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes, half-words, words, or doublewords. All load and store instructions are byte-, half-word-, word-, or doubleword-addressable. For more details on the C64x CPU functional units enhancements, see the following documents: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) TMS320C64x Technical Overview (literature number SPRU395) How To Begin Development Today With the TMS320C6414, TMS320C6415, and TMS320C6416 DSPs application report (literature number SPRA718)
TMS320C67x is a trademark of Texas Instruments.
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CPU (DSP core) description (continued)
src1 .L1 src2 8 8
dst long dst long src ST1b (Store Data) ST1a (Store Data) 32 MSBs 32 LSBs long src long dst dst .S1 src1 Data Path A src2 long dst dst .M1 src1
8 8 Register File A (A0-A31)
See Note A See Note A
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src2 LD1b (Load Data) LD1a (Load Data) DA1 (Address) 32 MSBs 32 LSBs .D1 dst src1 src2 2X 1X src2 DA2 (Address) LD2a (Load Data) LD2b (Load Data) 32 LSBs 32 MSBs src2 .M2 src1 dst long dst src2 Data Path B .S2 src1 dst long dst long src See Note A See Note A Register File B (B0- B31) 8 8 .D2 src1 dst
ST2a (Store Data) ST2b (Store Data)
32 MSBs 32 LSBs long src long dst dst .L2 src2 src1 Control Register File 8 8
NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs.
Figure 1. TMS320C64x CPU (DSP Core) Data Paths
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memory map summary
Table 3 shows the memory map address ranges of the TMS320C64x device. Internal memory is always located at address 0 and can be used as both program and data memory. The external memory address ranges in the C64x device begin at the hex address locations 0x6000 0000 for EMIFB and 0x8000 0000 for EMIFA.
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memory map summary (continued)
Table 3. TMS320C64x Memory Map Summary
MEMORY BLOCK DESCRIPTION Internal RAM (L2) Reserved External Memory Interface A (EMIFA) Registers L2 Registers HPI Registers McBSP 0 Registers McBSP 1 Registers Timer 0 Registers Timer 1 Registers Interrupt Selector Registers EDMA RAM and EDMA Registers McBSP 2 Registers EMIFB Registers Timer 2 Registers GPIO Registers UTOPIA Registers (C6415 and C6416 only) TCP/VCP Registers (C6416 only) Reserved PCI Registers (C6415 and C6416 only) Reserved QDMA Registers Reserved McBSP 0 Data McBSP 1 Data McBSP 2 Data UTOPIA Queues (C6415 and C6416 only) Reserved TCP/VCP (C6416 only) EMIFB CE0 EMIFB CE1 EMIFB CE2 EMIFB CE3 Reserved EMIFA CE0 EMIFA CE1 EMIFA CE2 EMIFA CE3 Reserved BLOCK SIZE (BYTES) 1M 23M 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 4M - 256K 52 736M - 52 64M 64M 64M 64M 256M 256M 64M 64M 64M 64M 256M 256M 256M 256M 256M 1G HEX ADDRESS RANGE
0000 0010 0180 0184 0188 018C 0190 0194 0198 019C 01A0 01A4 01A8 01AC 01B0 01B4 01B8 01BC 01C0 01C4 0200 0200 3000 3400 3800 3C00 4000 5000 6000 6400 6800 6C00 7000 8000 9000 A000 B000 C000
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0034 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
000F 017F 0183 0187 018B 018F 0193 0197 019B 019F 01A3 01A7 01AB 01AF 01B3 01B7 01BB 01BF 01C3 01FF 0200 2FFF 33FF 37FF 3BFF 3FFF 4FFF 5FFF 63FF 67FF 6BFF 6FFF 7FFF 8FFF 9FFF AFFF BFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 0033 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
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For the C6414 device, these memory address locations are reserved. The C6414 device does not support the UTOPIA and PCI peripherals. Only the C6416 device supports the VCP/TCP Coprocessors. For the C6414 and C6415 devices, these memory address locations are reserved.
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peripheral register descriptions
Table 4 through Table 23 identify the peripheral registers for the C6414, C6415, and C6416 devices by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names and their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190). Table 4. EMIFA Registers
HEX ADDRESS RANGE 0180 0000 0180 0004 0180 0008 0180 000C 0180 0010 0180 0014 0180 0018 0180 001C 0180 0020 0180 0024 - 0180 003C 0180 0040 0180 0044 0180 0048 0180 004C 0180 0050 0180 0054 0180 0058 - 0183 FFFF ACRONYM GBLCTL CECTL1 CECTL0 - CECTL2 CECTL3 SDCTL SDTIM SDEXT - PDTCTL CESEC1 CESEC0 - CESEC2 CESEC3 - EMIFA global control EMIFA CE1 space control EMIFA CE0 space control Reserved EMIFA CE2 space control EMIFA CE3 space control EMIFA SDRAM control EMIFA SDRAM refresh control EMIFA SDRAM extension Reserved Peripheral device transfer (PDT) control EMIFA CE1 space secondary control EMIFA CE0 space secondary control Reserved EMIFA CE2 space secondary control EMIFA CE3 space secondary control Reserved REGISTER NAME
Table 5. EMIFB Registers
HEX ADDRESS RANGE 01A8 0000 01A8 0004 01A8 0008 01A8 000C 01A8 0010 01A8 0014 01A8 0018 01A8 001C 01A8 0020 01A8 0024 - 01A8 003C 01A8 0040 01A8 0044 01A8 0048 01A8 004C 01A8 0050 01A8 0054 01A8 0058 - 01AB FFFF ACRONYM GBLCTL CECTL1 CECTL0 - CECTL2 CECTL3 SDCTL SDTIM SDEXT - PDTCTL CESEC1 CESEC0 - CESEC2 CESEC3 - EMIFB global control EMIFB CE1 space control EMIFB CE0 space control Reserved EMIFB CE2 space control EMIFB CE3 space control EMIFB SDRAM control EMIFB SDRAM refresh control EMIFB SDRAM extension Reserved Peripheral device transfer (PDT) control EMIFB CE1 space secondary control EMIFB CE0 space secondary control Reserved EMIFB CE2 space secondary control EMIFB CE3 space secondary control Reserved REGISTER NAME
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peripheral register descriptions (continued)
Table 6. L2 Cache Registers
HEX ADDRESS RANGE 0184 0000 0184 0004 - 0184 0FFC 0184 1000 0184 1004 - 0184 1FFC 0184 2000 0184 2004 0184 2008 0184 200C ACRONYM CCFG - EDMAWEIGHT - L2ALLOC0 L2ALLOC1 L2ALLOC2 L2ALLOC3 - L2FBAR L2FWC L2CBAR L2CWC L1PFBAR L1PFWC L1DFBAR L1DFWC - L2FLUSH L2CLEAN - MAR0 to MAR95 MAR96 MAR97 MAR98 MAR99 MAR100 MAR101 MAR102 MAR103 MAR104 MAR105 MAR106 MAR107 MAR108 MAR109 MAR110 MAR111 Reserved L2 EDMA access control register Reserved L2 allocation register 0 L2 allocation register 1 L2 allocation register 2 L2 allocation register 3 Reserved L2 flush base address register L2 flush word count register L2 clean base address register L2 clean word count register L1P flush base address register L1P flush word count register L1D flush base address register L1D flush word count register Reserved L2 flush register L2 clean register Reserved Reserved Controls EMIFB CE0 range 6000 0000 - 60FF FFFF Controls EMIFB CE0 range 6100 0000 - 61FF FFFF Controls EMIFB CE0 range 6200 0000 - 62FF FFFF Controls EMIFB CE0 range 6300 0000 - 63FF FFFF Controls EMIFB CE1 range 6400 0000 - 64FF FFFF Controls EMIFB CE1 range 6500 0000 - 65FF FFFF Controls EMIFB CE1 range 6600 0000 - 66FF FFFF Controls EMIFB CE1 range 6700 0000 - 67FF FFFF Controls EMIFB CE2 range 6800 0000 - 68FF FFFF Controls EMIFB CE2 range 6900 0000 - 69FF FFFF Controls EMIFB CE2 range 6A00 0000 - 6AFF FFFF Controls EMIFB CE2 range 6B00 0000 - 6BFF FFFF Controls EMIFB CE3 range 6C00 0000 - 6CFF FFFF Controls EMIFB CE3 range 6D00 0000 - 6DFF FFFF Controls EMIFB CE3 range 6E00 0000 - 6EFF FFFF Controls EMIFB CE3 range 6F00 0000 - 6FFF FFFF REGISTER NAME Cache configuration register COMMENTS
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0184 2010 - 0184 3FFC 0184 4000 0184 4004 0184 4010 0184 4014 0184 4020 0184 4024 0184 4030 0184 4034 0184 4038 - 0184 4FFC 0184 5000 0184 5004 0184 5008 - 0184 7FFC 0184 8000 - 0184 817C 0184 8180 0184 8184 0184 8188 0184 818C 0184 8190 0184 8194 0184 8198 0184 819C 0184 81A0 0184 81A4 0184 81A8 0184 81AC 0184 81B0 0184 81B4 0184 81B8 0184 81BC
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peripheral register descriptions (continued)
Table 6. L2 Cache Registers (Continued)
HEX ADDRESS RANGE 0184 81C0 - 0184 81FC 0184 8200 0184 8204 0184 8208 0184 820C 0184 8210 0184 8214 0184 8218 0184 821C 0184 8220 0184 8224 0184 8228 0184 822C 0184 8230 0184 8234 0184 8238 0184 823C 0184 8240 0184 8244 0184 8248 0184 824C 0184 8250 0184 8254 0184 8258 0184 825C 0184 8260 0184 8264 0184 8268 0184 826C 0184 8270 0184 8274 0184 8278 0184 827C 0184 8280 0184 8284 0184 8288 0184 828C 0184 8290 0184 8294 0184 8298 0184 829C ACRONYM MAR112 to MAR127 MAR128 MAR129 MAR130 MAR131 MAR132 MAR133 MAR134 MAR135 MAR136 MAR137 MAR138 MAR139 MAR140 MAR141 MAR142 MAR143 MAR144 MAR145 MAR146 MAR147 MAR148 MAR149 MAR150 MAR151 MAR152 MAR153 MAR154 MAR155 MAR156 MAR157 MAR158 MAR159 MAR160 MAR161 MAR162 MAR163 MAR164 MAR165 MAR166 MAR167 Reserved Controls EMIFA CE0 range 8000 0000 - 80FF FFFF Controls EMIFA CE0 range 8100 0000 - 81FF FFFF Controls EMIFA CE0 range 8200 0000 - 82FF FFFF Controls EMIFA CE0 range 8300 0000 - 83FF FFFF Controls EMIFA CE0 range 8400 0000 - 84FF FFFF Controls EMIFA CE0 range 8500 0000 - 85FF FFFF Controls EMIFA CE0 range 8600 0000 - 86FF FFFF Controls EMIFA CE0 range 8700 0000 - 87FF FFFF Controls EMIFA CE0 range 8800 0000 - 88FF FFFF Controls EMIFA CE0 range 8A00 0000 - 8AFF FFFF Controls EMIFA CE0 range 8B00 0000 - 8BFF FFFF Controls EMIFA CE0 range 8C00 0000 - 8CFF FFFF Controls EMIFA CE0 range 8D00 0000 - 8DFF FFFF Controls EMIFA CE0 range 8E00 0000 - 8EFF FFFF Controls EMIFA CE0 range 8F00 0000 - 8FFF FFFF Controls EMIFA CE1 range 9000 0000 - 90FF FFFF Controls EMIFA CE1 range 9100 0000 - 91FF FFFF Controls EMIFA CE1 range 9200 0000 - 92FF FFFF Controls EMIFA CE1 range 9300 0000 - 93FF FFFF Controls EMIFA CE1 range 9400 0000 - 94FF FFFF Controls EMIFA CE1 range 9500 0000 - 95FF FFFF Controls EMIFA CE1 range 9600 0000 - 96FF FFFF Controls EMIFA CE1 range 9700 0000 - 97FF FFFF Controls EMIFA CE1 range 9800 0000 - 98FF FFFF Controls EMIFA CE1 range 9900 0000 - 99FF FFFF Controls EMIFA CE1 range 9A00 0000 - 9AFF FFFF Controls EMIFA CE1 range 9B00 0000 - 9BFF FFFF Controls EMIFA CE1 range 9C00 0000 - 9CFF FFFF Controls EMIFA CE1 range 9D00 0000 - 9DFF FFFF Controls EMIFA CE1 range 9E00 0000 - 9EFF FFFF Controls EMIFA CE1 range 9F00 0000 - 9FFF FFFF Controls EMIFA CE2 range A000 0000 - A0FF FFFF Controls EMIFA CE2 range A100 0000 - A1FF FFFF Controls EMIFA CE2 range A200 0000 - A2FF FFFF Controls EMIFA CE2 range A300 0000 - A3FF FFFF Controls EMIFA CE2 range A400 0000 - A4FF FFFF Controls EMIFA CE2 range A500 0000 - A5FF FFFF Controls EMIFA CE2 range A600 0000 - A6FF FFFF Controls EMIFA CE2 range A700 0000 - A7FF FFFF Controls EMIFA CE0 range 8900 0000 - 89FF FFFF REGISTER NAME COMMENTS
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peripheral register descriptions (continued)
Table 6. L2 Cache Registers (Continued)
HEX ADDRESS RANGE 0184 82A0 0184 82A4 0184 82A8 0184 82AC 0184 82B0 0184 82B4 0184 82B8 0184 82BC 0184 82C0 0184 82C4 0184 82C8 ACRONYM MAR168 MAR169 MAR170 MAR171 MAR172 MAR173 MAR174 MAR175 MAR176 MAR177 MAR178 MAR179 MAR180 MAR181 MAR182 MAR183 MAR184 MAR185 MAR186 MAR187 MAR188 MAR189 MAR190 MAR191 MAR192 to MAR255 - REGISTER NAME Controls EMIFA CE2 range A800 0000 - A8FF FFFF Controls EMIFA CE2 range A900 0000 - A9FF FFFF Controls EMIFA CE2 range AA00 0000 - AAFF FFFF Controls EMIFA CE2 range AB00 0000 - ABFF FFFF Controls EMIFA CE2 range AC00 0000 - ACFF FFFF Controls EMIFA CE2 range AD00 0000 - ADFF FFFF Controls EMIFA CE2 range AE00 0000 - AEFF FFFF Controls EMIFA CE2 range AF00 0000 - AFFF FFFF Controls EMIFA CE3 range B000 0000 - B0FF FFFF Controls EMIFA CE3 range B100 0000 - B1FF FFFF Controls EMIFA CE3 range B200 0000 - B2FF FFFF Controls EMIFA CE3 range B300 0000 - B3FF FFFF Controls EMIFA CE3 range B400 0000 - B4FF FFFF Controls EMIFA CE3 range B500 0000 - B5FF FFFF Controls EMIFA CE3 range B600 0000 - B6FF FFFF Controls EMIFA CE3 range B700 0000 - B7FF FFFF Controls EMIFA CE3 range B800 0000 - B8FF FFFF Controls EMIFA CE3 range B900 0000 - B9FF FFFF Controls EMIFA CE3 range BA00 0000 - BAFF FFFF Controls EMIFA CE3 range BB00 0000 - BBFF FFFF Controls EMIFA CE3 range BC00 0000 - BCFF FFFF Controls EMIFA CE3 range BD00 0000 - BDFF FFFF Controls EMIFA CE3 range BE00 0000 - BEFF FFFF Controls EMIFA CE3 range BF00 0000 - BFFF FFFF Reserved Reserved COMMENTS
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0184 82CC 0184 82D0 0184 82D4 0184 82D8 0184 82DC 0184 82E0 0184 82E4 0184 82E8 0184 82EC 0184 82F0 0184 82F4 0184 82F8 0184 82FC 0184 8300 - 0184 83FC 0184 8400 - 0187 FFFF
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peripheral register descriptions (continued)
Table 7. EDMA Registers
HEX ADDRESS RANGE 01A0 FF9C 01A0 FFA4 01A0 FFA8 01A0 FFAC 01A0 FFB0 01A0 FFB4 01A0 FFB8 01A0 FFBC 01A0 FFC0 01A0 FFC4 01A0 FFC8 01A0 FFCC 01A0 FFDC 01A0 FFE0 01A0 FFE4 01A0 FFE8 01A0 FFEC 01A0 FFF0 01A0 FFF4 01A0 FFF8 01A0 FFFC 01A1 0000 - 01A3 FFFF ACRONYM EPRH CIPRH CIERH CCERH ERH EERH ECRH ESRH PQAR0 PQAR1 PQAR2 PQAR3 EPRL PQSR CIPRL CIERL CCERL ERL EERL ECRL ESRL - REGISTER NAME Event polarity high register Channel interrupt pending high register Channel interrupt enable high register Channel chain enable high register Event high register Event enable high register Event clear high register Event set high register Priority queue allocation register 0 Priority queue allocation register 1 Priority queue allocation register 2 Priority queue allocation register 3 Event polarity low register Priority queue status register Channel interrupt pending low register Channel interrupt enable low register Channel chain enable low register Event low register Event enable low register Event clear low register Event set low register Reserved
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peripheral register descriptions (continued)
Table 8. EDMA Parameter RAM
HEX ADDRESS RANGE 01A0 0000 - 01A0 0017 01A0 0018 - 01A0 002F 01A0 0030 - 01A0 0047 01A0 0048 - 01A0 005F 01A0 0060 - 01A0 0077 01A0 0078 - 01A0 008F 01A0 0090 - 01A0 00A7 01A0 00A8 - 01A0 00BF 01A0 00C0 - 01A0 00D7 01A0 00D8 - 01A0 00EF 01A0 00F0 - 01A0 00107 01A0 0108 - 01A0 011F 01A0 0120 - 01A0 0137 01A0 0138 - 01A0 014F 01A0 0150 - 01A0 0167 01A0 0168 - 01A0 017F 01A0 0150 - 01A0 0167 01A0 0168 - 01A0 017F ... ... 01A0 05D0 - 01A0 05E7 01A0 05E8 - 01A0 05FF 01A0 0600 - 01A0 0617 01A0 0618 - 01A0 062F ... 01A0 07E0 - 01A0 07F7 01A0 07F8 - 01A0 07FF - - - - - - ACRONYM - - - - - - - - - - - - - - - - - - REGISTER NAME Parameters for Event 0 (6 words) Parameters for Event 1 (6 words) Parameters for Event 2 (6 words) Parameters for Event 3 (6 words) Parameters for Event 4 (6 words) Parameters for Event 5 (6 words) Parameters for Event 6 (6 words) Parameters for Event 7 (6 words) Parameters for Event 8 (6 words) Parameters for Event 9 (6 words) Parameters for Event 10 (6 words) Parameters for Event 11 (6 words) Parameters for Event 12 (6 words) Parameters for Event 13 (6 words) Parameters for Event 14 (6 words) Parameters for Event 15 (6 words) Parameters for Event 16 (6 words) Parameters for Event 17 (6 words) ... ... Parameters for Event 62 (6 words) Parameters for Event 63 (6 words) Reload/link parameters for Event M (6 words) Reload/link parameters for Event N (6 words) ... Reload/link parameters for Event Z (6 words) COMMENTS
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Scratch pad area (2 words) The C64x device has twenty-one parameter sets [six (6) words each] that can be used to reload/link EDMA transfers.
Table 9. Quick DMA (QDMA) and Pseudo Registers
HEX ADDRESS RANGE 0200 0000 0200 0004 0200 0008 0200 000C 0200 0010 0200 0014 - 0200 001C 0200 0020 0200 0024 0200 0028 0200 002C 0200 0030 QSOPT QSSRC QSCNT QSDST QSIDX ACRONYM QOPT QSRC QCNT QDST QIDX REGISTER NAME QDMA options parameter register QDMA source address register QDMA frame count register QDMA destination address register QDMA index register Reserved QDMA pseudo options register QDMA pseudo source address register QDMA pseudo frame count register QDMA pseudo destination address register QDMA pseudo index register
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peripheral register descriptions (continued)
Table 10. Interrupt Selector Registers
HEX ADDRESS RANGE 019C 0000 019C 0004 019C 0008 019C 000C - 019C 01FF ACRONYM MUXH MUXL EXTPOL - REGISTER NAME Interrupt multiplexer high Interrupt multiplexer low External interrupt polarity Reserved COMMENTS Selects which interrupts drive CPU interrupts 10-15 (INT10-INT15) Selects which interrupts drive CPU interrupts 4-9 (INT04-INT09) Sets the polarity of the external interrupts (EXT_INT4-EXT_INT7)
Table 11. McBSP 0 Registers
HEX ADDRESS RANGE 018C 0000 0x3000 0000 - 0x33FF FFFF 018C 0004 0x3000 0000 - 0x33FF FFFF 018C 0008 018C 000C 018C 0010 018C 0014 018C 0018 018C 001C 018C 0020 018C 0024 018C 0028 018C 002C 018C 0030 018C 0034 018C 0038 018C 003C 018C 0040 - 018F FFFF ACRONYM DRR0 DRR0 DXR0 DXR0 SPCR0 RCR0 XCR0 SRGR0 MCR0 RCERE00 XCERE00 PCR0 RCERE10 XCERE10 RCERE20 XCERE20 RCERE30 XCERE30 - REGISTER NAME McBSP0 data receive register via Configuration Bus McBSP0 data receive register via Peripheral Bus McBSP0 data transmit register via Configuration Bus McBSP0 data transmit register via Peripheral Bus McBSP0 serial port control register McBSP0 receive control register McBSP0 transmit control register McBSP0 sample rate generator register McBSP0 multichannel control register McBSP0 enhanced receive channel enable register 0 McBSP0 enhanced transmit channel enable register 0 McBSP0 pin control register McBSP0 enhanced receive channel enable register 1 McBSP0 enhanced transmit channel enable register 1 McBSP0 enhanced receive channel enable register 2 McBSP0 enhanced transmit channel enable register 2 McBSP0 enhanced receive channel enable register 3 McBSP0 enhanced transmit channel enable register 3 Reserved COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it.
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peripheral register descriptions (continued)
Table 12. McBSP 1 Registers
HEX ADDRESS RANGE 0190 0000 0x3400 0000 - 0x37FF FFFF 0190 0004 0x3400 0000 - 0x37FF FFFF 0190 0008 0190 000C 0190 0010 0190 0014 0190 0018 0190 001C 0190 0020 ACRONYM DRR1 DRR1 DXR1 DXR1 SPCR1 RCR1 XCR1 SRGR1 MCR1 RCERE01 XCERE01 PCR1 RCERE11 XCERE11 RCERE21 XCERE21 RCERE31 XCERE31 - REGISTER NAME McBSP1 data receive register via Configuration Bus McBSP1 data receive register via Peripheral Bus McBSP1 data transmit register via Configuration Bus McBSP1 data transmit register via Peripheral Bus McBSP1 serial port control register McBSP1 receive control register McBSP1 transmit control register McBSP1 sample rate generator register McBSP1 multichannel control register McBSP1 enhanced receive channel enable register 0 McBSP1 enhanced transmit channel enable register 0 McBSP1 pin control register McBSP1 enhanced receive channel enable register 1 McBSP1 enhanced transmit channel enable register 1 McBSP1 enhanced receive channel enable register 2 McBSP1 enhanced transmit channel enable register 2 McBSP1 enhanced receive channel enable register 3 McBSP1 enhanced transmit channel enable register 3 Reserved COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it.
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0190 0024 0190 0028 0190 002C 0190 0030 0190 0034 0190 0038 0190 003C 0190 0040 - 0193 FFFF
Table 13. McBSP 2 Registers
HEX ADDRESS RANGE 01A4 0000 0x3800 0000 - 0x3BFF FFFF 01A4 0004 0x3800 0000 - 0x3BFF FFFF 01A4 0008 01A4 000C 01A4 0010 01A4 0014 01A4 0018 01A4 001C 01A4 0020 01A4 0024 01A4 0028 01A4 002C 01A4 0030 01A4 0034 01A4 0038 01A4 003C 01A4 0040 - 01A7 FFFF ACRONYM DRR2 DRR2 DXR2 DXR2 SPCR2 RCR2 XCR2 SRGR2 MCR2 RCERE02 XCERE02 PCR2 RCERE12 XCERE12 RCERE22 XCERE22 RCERE32 XCERE32 - REGISTER NAME McBSP2 data receive register via Configuration Bus McBSP2 data receive register via Peripheral Bus McBSP2 data transmit register via Configuration Bus McBSP2 data transmit register via Peripheral Bus McBSP2 serial port control register McBSP2 receive control register McBSP2 transmit control register McBSP2 sample rate generator register McBSP2 multichannel control register McBSP2 enhanced receive channel enable register 0 McBSP2 enhanced transmit channel enable register 0 McBSP2 pin control register McBSP2 enhanced receive channel enable register 1 McBSP2 enhanced transmit channel enable register 1 McBSP2 enhanced receive channel enable register 2 McBSP2 enhanced transmit channel enable register 2 McBSP2 enhanced receive channel enable register 3 McBSP2 enhanced transmit channel enable register 3 Reserved COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it.
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peripheral register descriptions (continued)
Table 14. Timer 0 Registers
HEX ADDRESS RANGE 0194 0000 ACRONYM CTL0 REGISTER NAME Timer 0 control register COMMENTS Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. Contains the current value of the incrementing counter.
0194 0004
PRD0
Timer 0 period register
0194 0008 0194 000C - 0197 FFFF
CNT0 -
Timer 0 counter register Reserved
Table 15. Timer 1 Registers
HEX ADDRESS RANGE 0198 0000 ACRONYM CTL1 REGISTER NAME Timer 1 control register COMMENTS Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. Contains the current value of the incrementing counter.
0198 0004
PRD1
Timer 1 period register
0198 0008 0198 000C - 019B FFFF
CNT1 -
Timer 1 counter register Reserved
Table 16. Timer 2 Registers
HEX ADDRESS RANGE 01AC 0000 ACRONYM CTL2 REGISTER NAME Timer 2 control register COMMENTS Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. Contains the current value of the incrementing counter.
01AC 0004
PRD2
Timer 2 period register
01AC 0008 01AC 000C - 01AF FFFF
CNT2 -
Timer 2 counter register Reserved
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peripheral register descriptions (continued)
Table 17. HPI Registers
HEX ADDRESS RANGE - 0188 0000 0188 0004 0188 0008 0188 000C - 0189 FFFF 018A 0000 018A 0004 - 018B FFFF ACRONYM HPID HPIC HPIA (HPIAW) HPIA (HPIAR) - TRCTL - HPI data register HPI control register HPI address register (Write) HPI address register (Read) Reserved HPI transfer request control register REGISTER NAME COMMENTS Host read/write access only HPIC has both Host/CPU read/write access HPIA has both Host/CPU read/write access
Reserved Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently.
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Table 18. GPIO Registers
HEX ADDRESS RANGE 01B0 0000 01B0 0004 01B0 0008 01B0 000C 01B0 0010 01B0 0014 01B0 0018 01B0 001C 01B0 0020 01B0 0024 01B0 0028 - 01B0 01FF 01B0 0200 01B0 0204 - 01B3 FFFF ACRONYM GPEN GPDIR GPVAL - GPDH GPHM GPDL GPLM GPGC GPPOL - DEVICE_REV - REGISTER NAME GPIO enable register GPIO direction register GPIO value register Reserved GPIO delta high register GPIO high mask register GPIO delta low register GPIO low mask register GPIO global control register GPIO interrupt polarity register Reserved Silicon Revision Identification Register (For more details, see the device characteristics listed in Table 1.) Reserved
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peripheral register descriptions (continued)
Table 19. PCI Peripheral Registers (C6415 and C6416 Only)
HEX ADDRESS RANGE 01C0 0000 01C0 0004 01C0 0008 01C0 000C 01C0 0010 01C0 0014 01C0 0018 01C0 001C 01C0 0020 01C0 0024 01C0 0028 01C0 002C - 01C1 FFEF 0x01C1 FFF0 0x01C1 FFF4 0x01C1 FFF8 0x01C1 FFFC 01C2 0000 01C2 0004 01C2 0008 01C2 000C - 01C2 FFFF 01C3 0000 01C3 0004 - 01C3 FFFF ACRONYM RSTSRC - PCIIS PCIIEN DSPMA PCIMA PCIMC CDSPA CPCIA CCNT - - HSR HDCR DSPP - EEADD EEDAT EECTL - TRCTL - Reserved PCI interrupt source register PCI interrupt enable register DSP master address register PCI master address register PCI master control register Current DSP address register Current PCI address register Current byte count register Reserved Host status register Host-to-DSP control register DSP page register Reserved EEPROM address register EEPROM data register EEPROM control register Reserved PCI transfer request control register Reserved REGISTER NAME DSP Reset source/status register
Reserved These PCI registers are not supported on the C6414 device.
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peripheral register descriptions (continued)
Table 20. UTOPIA (C6415 and C6416 Only)
HEX ADDRESS RANGE 01B4 0000 01B4 0004 01B4 0008 01B4 000C 01B4 0010 01B4 0014 01B4 0018 01B4 001C 01B4 0020 - 01B7 FFFF ACRONYM UCR - - UIER UIPR CDR EIER EIPR - Reserved Reserved UTOPIA interrupt enable register UTOPIA interrupt pending register Clock detect register Error interrupt enable register Error interrupt pending register REGISTER NAME UTOPIA control register
Reserved These UTOPIA registers are not supported on the C6414 device.
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Table 21. UTOPIA QUEUES (C6415 and C6416 Only)
HEX ADDRESS RANGE 3C00 0000 3D00 0000 3D00 0004 - 3FFF FFFF ACRONYM URQ UXQ - REGISTER NAME UTOPIA receive queue UTOPIA transmit queue
Reserved These UTOPIA registers are not supported on the C6414 device.
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peripheral register descriptions (continued)
Table 22. VCP Registers (C6416 Only)
EDMA BUS HEX ADDRESS RANGE 5000 0000 5000 0004 5000 0008 5000 000C 5000 0010 5000 0014 5000 0040 5000 0044 5000 0080 5000 0088 - - - - - PERIPHERAL BUS HEX ADDRESS RANGE 01B8 0000 01B8 0004 01B8 0008 01B8 000C 01B8 0010 01B8 0014 01B8 0024 01B8 0028 - - 01B8 0018 01B8 0020 01B8 0040 01B8 0044 01B8 0050 ACRONYM VCPIC0 VCPIC1 VCPIC2 VCPIC3 VCPIC4 VCPIC5 VCPOUT0 VCPOUT1 VCPWBM VCPRDECS VCPEXE VCPEND VCPSTAT0 VCPSTAT1 VCPERR REGISTER NAME VCP input configuration register 0 VCP input configuration register 1 VCP input configuration register 2 VCP input configuration register 3 VCP input configuration register 4 VCP input configuration register 5 VCP output register 0 VCP output register 1 VCP branch metrics write register VCP execution register VCP endian register VCP status register 0 VCP status register 1 VCP error register
These VCP registers are supported on the C6416 device only.
Table 23. TCP Registers (C6416 Only)
EDMA BUS HEX ADDRESS RANGE 5800 0000 5800 0004 5800 0008 5800 000C 5800 0010 5800 0014 5800 0018 5800 001C 5800 0020 5800 0024 5800 0028 5800 002C 5800 0030 5802 0000 5804 0000 5806 0000 5808 0000 580A 0000 - - - - PERIPHERAL BUS HEX ADDRESS RANGE 01BA 0000 01BA 0004 01BA 0008 01BA 000C 01BA 0010 01BA 0014 01BA 0018 01BA 001C 01BA 0020 01BA 0024 01BA 0028 01BA 002C 01BA 0030 - - - - - 01BA 0038 01BA 0040 01BA 0050 01BA 0058 ACRONYM TCPIC0 TCPIC1 TCPIC2 TCPIC3 TCPIC4 TCPIC5 TCPIC6 TCPIC7 TCPIC8 TCPIC9 TCPIC10 TCPIC11 TCPOUT TCPSP TCPEXT TCPAP TCPINTER TCPHD TCPEXE TCPEND TCPERR TCPSTAT REGISTER NAME TCP input configuration register 0 TCP input configuration register 1 TCP input configuration register 2 TCP input configuration register 3 TCP input configuration register 4 TCP input configuration register 5 TCP input configuration register 6 TCP input configuration register 7 TCP input configuration register 8 TCP input configuration register 9 TCP input configuration register 10 TCP input configuration register 11 TCP output parameters register TCP systematics and parities memory TCP extrinsics memory TCP apriori memory TCP interleaver memory TCP hard decisions memory TCP execution register TCP endian register TCP error register TCP status register
These TCP registers are supported on the C6416 device only.
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EDMA channel synchronization events
The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory. Table 24 lists the source of C64x EDMA synchronization events associated with each of the programmable EDMA channels. For the C64x device, the association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL, EERH). The priority of each event can be specified independently in the transfer parameters stored in the EDMA parameter RAM. For more detailed information on the EDMA module and how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234).
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EDMA channel synchronization events (continued)
Table 24. TMS320C64x EDMA Channel Synchronization Events
EDMA CHANNEL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22-27 28 29 30 31 32 33-39 40 41-47 48 49 50 51 52 53 54 55 56-63
EVENT NAME
DSP_INT TINT0 TINT1 SD_INTA GPINT4/EXT_INT4 GPINT5/EXT_INT5 GPINT6/EXT_INT6 GPINT7/EXT_INT7 GPINT0 GPINT1 GPINT2 GPINT3 XEVT0 REVT0 XEVT1 REVT1 - XEVT2 REVT2 TINT2 SD_INTB - - VCPREVT VCPXEVT TCPREVT TCPXEVT UREVT - UXEVT - GPINT8 GPINT9 GPINT10 GPINT11 GPINT12 GPINT13 GPINT14 GPINT15 -
EVENT DESCRIPTION
HPI/PCI-to-DSP interrupt (PCI peripheral supported on C6415 and C6416 only) Timer 0 interrupt Timer 1 interrupt EMIFA SDRAM timer interrupt GPIO event 4/External interrupt pin 4 GPIO event 5/External interrupt pin 5 GPIO event 6/External interrupt pin 6 GPIO event 7/External interrupt pin 7 GPIO event 0 GPIO event 1 GPIO event 2 GPIO event 3 McBSP0 receive event McBSP1 transmit event McBSP1 receive event None McBSP2 transmit event McBSP2 receive event Timer 2 interrupt EMIFB SDRAM timer interrupt Reserved, for future expansion None VCP receive event (C6416 only) VCP transmit event (C6416 only) TCP receive event (C6416 only) TCP transmit event (C6416 only) UTOPIA receive event (C6415 and C6416 only) None UTOPIA transmit event (C6415 and C6416 only) None GPIO event 8 GPIO event 9 GPIO event 10 GPIO event 11 GPIO event 12 GPIO event 13 GPIO event 14 GPIO event 15 None
In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234). The PCI and UTOPIA peripherals are not supported on the C6414 device; therefore, these EDMA synchronization events are reserved. The VCP/TCP EDMA synchronization events are supported on the C6416 only. For the C6414 and C6415 devices, these events are reserved.
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interrupt sources and interrupt selector
The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 25. The highest-priority interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts (INT_00-INT_03) are non-maskable and fixed. The remaining interrupts (INT_04-INT_15) are maskable and default to the interrupt source specified in Table 25. The interrupt source for interrupts 4-15 can be programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
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interrupt sources and interrupt selector (continued)
Table 25. C64x DSP Interrupts
CPU INTERRUPT NUMBER INT_00 INT_01 INT_02 INT_03 INT_04 INT_05 INT_06 INT_07 INT_08 INT_09 INT_10 INT_11 INT_12 INT_13 INT_14 INT_15 - - - - - - - - - - - - - - - INTERRUPT SELECTOR CONTROL REGISTER - - - - MUXL[4:0] MUXL[9:5] MUXL[14:10] MUXL[20:16] MUXL[25:21] MUXL[30:26] MUXH[4:0] MUXH[9:5] MUXH[14:10] MUXH[20:16] MUXH[25:21] MUXH[30:26] - - - - - - - - - - - - - - - SELECTOR VALUE (BINARY) - - - - 00100 00101 00110 00111 01000 01001 00011 01010 01011 00000 00001 00010 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 - 11101 11110 11111 INTERRUPT EVENT RESET NMI Reserved Reserved GPINT4/EXT_INT4 GPINT5/EXT_INT5 GPINT6/EXT_INT6 GPINT7/EXT_INT7 EDMA_INT EMU_DTDMA SD_INTA EMU_RTDXRX EMU_RTDXTX DSP_INT TINT0 TINT1 XINT0 RINT0 XINT1 RINT1 GPINT0 XINT2 RINT2 TINT2 SD_INTB Reserved Reserved UINT Reserved VCPINT TCPINT Reserved. Do not use. Reserved. Do not use. GPIO interrupt 4/External interrupt pin 4 GPIO interrupt 5/External interrupt pin 5 GPIO interrupt 6/External interrupt pin 6 GPIO interrupt 7/External interrupt pin 7 EDMA channel (0 through 63) interrupt EMU DTDMA EMIFA SDRAM timer interrupt EMU real-time data exchange (RTDX) receive EMU RTDX transmit HPI/PCI-to-DSP interrupt (PCI supported on C6415 and C6416 only) Timer 0 interrupt Timer 1 interrupt McBSP0 transmit interrupt McBSP0 receive interrupt McBSP1 transmit interrupt McBSP1 receive interrupt GPIO interrupt 0 McBSP2 transmit interrupt McBSP2 receive interrupt Timer 2 interrupt EMIFB SDRAM timer interrupt Reserved. Do not use. Reserved. Do not use. UTOPIA interrupt (C6415/C6416 only) Reserved. Do not use. VCP interrupt (C6416 only) TCP interrupt (C6416 only) INTERRUPT SOURCE
Interrupts INT_00 through INT_03 are non-maskable and fixed. Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields. Table 25 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and selection, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646).
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signal groups description
CLKIN CLKOUT4/GP1 CLKOUT6/GP2 CLKMODE1 CLKMODE0 PLLV
Clock/PLL
Reset and Interrupts
RESET NMI GP7/EXT_INT7 GP6/EXT_INT6 GP5/EXT_INT5 GP4/EXT_INT4
ADVANCE INFORMATION
TMS TDO TDI TCK TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 EMU6 EMU7 EMU8 EMU9 EMU10 EMU11
Reserved
RSV RSV RSV RSV RSV RSV
IEEE Standard 1149.1 (JTAG) Emulation
* * *
RSV RSV RSV
Peripheral Control/Status
PCI_EN MCBSP2_EN
Control/Status
GP15/PRST GP14/PCLK GP13/PINTA GP12/PGNT GP11/PREQ GP10/PCBE3 GP9/PIDSEL CLKS2/GP8
GPIO
GP7/EXT_INT7 GP6/EXT_INT6 GP5/EXT_INT5 GP4/EXT_INT4 GP3 CLKOUT6/GP2 CLKOUT4/GP1 GP0
General-Purpose Input/Output (GPIO) Port These pins are muxed with the GPIO port pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6) or McBSP2 clock source (CLKS2). To use these muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly enabled and configured. For more details, see the Device Configurations section of this data sheet. These pins are GPIO pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or GPIO as input-only. For the C6415 and C6416 devices, these GPIO pins are muxed with the PCI peripheral pins. By default, these signals are set up to no function with both the GPIO and PCI pin functions disabled. For more details on these muxed pins, see the Device Configurations section of this data sheet. For the C6414 device, the GPIO peripheral pins are not muxed; the C6414 device does not support the PCI peripheral.
Figure 2. CPU and Peripheral Signals
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signal groups description (continued)
64 AED[63:0] ACE3 ACE2 ACE1 ACE0 20 AEA[22:3] ABE7 ABE6 ABE5 ABE4 ABE3 ABE2 ABE1 ABE0 Byte Enables Memory Map Space Select External Memory I/F Control Data AECLKIN AECLKOUT1 AECLKOUT2 ASDCKE AARE/ASDCAS/ASADS/ASRE AAOE/ASDRAS/ASOE AAWE/ASDWE/ASWE AARDY ASOE3 APDT
Address
EMIFA (64-bit)
16 BED[15:0] Data BECLKIN BECLKOUT1 BECLKOUT2 Memory Map Space Select External Memory I/F Control BARE/BSDCAS/BSADS/BSRE BAOE/BSDRAS/BSOE BAWE/BSDWE/BSWE BARDY BSOE3 BPDT
BCE3 BCE2 BCE1 BCE0 20 BEA[20:1]
Address
BBE1 BBE0
Byte Enables Bus Arbitration EMIFB (16-bit)
BHOLD BHOLDA BBUSREQ
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name.
Figure 3. Peripheral Signals
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Bus Arbitration
AHOLD AHOLDA ABUSREQ
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signal groups description (continued)
HPI (Host-Port Interface) HAS/PPAR HR/W/PCBE2 HCS/PPERR HDS1/PSERR HDS2/PCBE1 HRDY/PIRDY HINT/PFRAME
32 HD[31:0]/AD[31:0]
Data
HCNTL0/PSTOP HCNTL1/PDEVSEL
Register Select Control Half-Word Select
HHWIL/PTRDY (HPI16 ONLY)
32 HD[31:0]/AD[31:0] Data/Address Clock GP14/PCLK
ADVANCE INFORMATION
GP10/PCBE3 HR/W/PCBE2 HDS2/PCBE1 PCBE0
Command Byte Enable
Control
GP9/PIDSEL HCNTL1/PDEVSEL HINT/PFRAME GP13/PINTA HAS/PPAR GP15/PRST HRDY/PIRDY HCNTL0/PSTOP HHWIL/PTRDY
GP12/PGNT GP11/PREQ
Arbitration Error
HDS1/PSERR HCS/PPERR
Serial EEPROM PCI Interface (C6415 and C6416 Only)
DX2/XSP_DO XSP_CS CLKX2/XSP_CLK DR2/XSP_DI
For the C6415 and C6416 devices, these HPI pins are muxed with the PCI peripheral. By default, these signals function as HPI. For more details on these muxed pins, see the Device Configurations section of this data sheet. For the C6414 device, these HPI pins are not muxed; the C6414 device does not support the PCI peripheral. For the C6415 and C6416 devices, these PCI pins (excluding PCBE0 and XSP_CS) are muxed with the HPI, McBSP2, or GPIO peripherals. By default, these signals function as HPI, McBSP2, and no function, respectively. For more details on these muxed pins, see the Device Configurations section of this data sheet. For the C6414 device, the HPI, McBSP2, and GPIO peripheral pins are not muxed; the C6414 device does not support the PCI peripheral. For the C6414 device, these pins are "Reserved (leave unconnected, do not connect to power or ground)."
Figure 3. Peripheral Signals (Continued)
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signal groups description (continued)
McBSP1 CLKX1/URADDR4 FSX1/UXADDR3 DX1/UXADDR4 CLKR1/URADDR2 FSR1/UXADDR2 DR1/UXADDR1 CLKS1/URADDR3 Transmit McBSP0 Transmit CLKX0 FSX0 DX0 CLKR0 FSR0 DR0 Clock Clock CLKS0
Receive
Receive
McBSP2 CLKX2/XSP_CLK FSX2 DX2/XSP_DO CLKR2 FSR2 DR2/XSP_DI CLKS2/GP8 Transmit
Receive
Clock
McBSPs (Multichannel Buffered Serial Ports)
For the C6415 and C6416 devices, these McBSP2 and McBSP1 pins are muxed with the PCI and UTOPIA peripherals, respectively. By default, these signals function as McBSP2 and McBSP1, respectively. For more details on these muxed pins, see the Device Configurations section of this data sheet. For the C6414 device, these McBSP2 and McBSP1 peripheral pins are not muxed; the C6414 device does not support PCI and UTOPIA peripherals. The McBSP2 clock source pin (CLKS2, default) is muxed with the GP8 pin. To use this muxed pin as the GP8 signal, the appropriate GPIO register bits (GP8EN and GP8DIR) must be properly enabled and configured. For more details, see the Device Configurations section of this data sheet.
Figure 3. Peripheral Signals (Continued)
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signal groups description (continued)
UTOPIA (SLAVE) [C6415 and C6416 Only]
URDATA7 URDATA6 URDATA5 URDATA4 URDATA3 URDATA2 URDATA1 URDATA0
Receive
Transmit
UXDATA7 UXDATA6 UXDATA5 UXDATA4 UXDATA3 UXDATA2 UXDATA1 UXDATA0
ADVANCE INFORMATION
URENB CLKX1/URADDR4 CLKS1/URADDR3 CLKR1/URADDR2 URADDR1 URADDR0 URCLAV URSOC
Control/Status
Control/Status
UXENB DX1/UXADDR4 FSX1/UXADDR3 FSR1/UXADDR2 DR1/UXADDR1 UXADDR0 UXCLAV UXSOC
URCLK
Clock
Clock
UXCLK
TOUT1 TINP1 TOUT2 TINP2
Timer 1
Timer 0
TOUT0 TINP0
Timer 2 Timers
For the C6415 and C6416 devices, these UTOPIA pins are muxed with the McBSP1 peripheral. By default, these signals function as McBSP1. For more details on these muxed pins, see the Device Configurations section of this data sheet. For the C6414 device, these McBSP1 peripheral pins are not muxed; the C6414 does not support the UTOPIA peripheral.
Figure 3. Peripheral Signals (Continued)
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DEVICE CONFIGURATIONS
The C6414, C6415, and C6416 peripheral selections and other device configurations are determined by external pullup/pulldown resistors on the following pins (all of which are latched during device reset):
D peripherals selection (C6415 and C6416 devices)
- - - BEA11 (UTOPIA_EN) PCI_EN (for C6415 or C6416, see Table 27 footnotes) MCBSP2_EN (for C6415 or C6416, see Table 27 footnotes)
The C6414 device does not support the PCI and UTOPIA peripherals; for proper operation of the C6414 device, do not oppose the internal pulldowns (IPDs) on the BEA11, PCI_EN, and MCBSP2_EN pins. (For IPUs/IPDs on pins, see the Terminal Functions table of this data sheet.)
D other device configurations (C64x)
- - BEA[20:13, 7]
peripherals selection
Some C6415/C6416 peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., HPI, general-purpose input/output pins GP[15:9], PCI and its internal EEPROM, McBSP1, McBSP2, and UTOPIA). The VCP/TCP coprocessors (C6416 only) and other C64x peripherals (i.e., the Timers, McBSP0, and the GP[8:0] pins), are always available.
D UTOPIA and McBSP1 peripherals
The UTOPIA_EN pin (BEA11) is latched at reset. For C6415 and C6416 devices, this pin selects whether the UTOPIA peripheral or McBSP1 peripheral is functionally enabled (see Table 26). The C6414 device does not support the UTOPIA peripheral; for proper device operation, do not oppose the internal pulldown (IPD) on the BEA11 pin. Table 26. UTOPIA_EN Peripheral Selection (McBSP1 and UTOPIA) (C6415/C6416 Only)
PERIPHERAL SELECTION UTOPIA_EN (BEA11) Pin [D16] 0 PERIPHERALS SELECTED UTOPIA McBSP1 DESCRIPTION McBSP1 is enabled and UTOPIA is disabled [default]. This means all multiplexed McBSP1/UTOPIA pins function as McBSP1 and all other standalone UTOPIA pins are tied-off (Hi-Z). UTOPIA is enabled and McBSP1 is disabled. This means all multiplexed McBSP1/UTOPIA pins now function as UTOPIA and all other standalone McBSP1 pins are tied-off (Hi-Z).
1
D HPI, GP[15:9], PCI, EEPROM (internal to PCI), and McBSP2 peripherals
The PCI_EN and MCBSP2_EN pins are latched at reset. They determine specific peripheral selection for the C6415 and C6416 devices, summarized in Table 27. The C6414 device does not support the PCI peripheral; for proper device operation, do not oppose the internal pulldowns (IPDs) on the PCI_EN and MCBSP2_EN pins.
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DEVICE CONFIGURATIONS (CONTINUED)
Table 27. PCI_EN and MCBSP2_EN Peripheral Selection (HPI, GP[15:9], PCI, and McBSP2)
PERIPHERAL SELECTION PCI_EN Pin [AA4] 0 0 1 1 MCBSP2_EN Pin [AF3] 0 1 0 1 HPI GP[15:9] PERIPHERALS SELECTED PCI EEPROM (Internal to PCI) McBSP2
The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation. The MCBSP2_EN pin must be driven valid at all times and the user can switch values throughout device operation. The only time McBSP2 is disabled is when both PCI_EN = 1 and MCBSP2_EN = 0. This configuration enables, at reset, the auto-initialization of the PCI peripheral through the PCI internal EEPROM [provided the PCI EEPROM Auto-Initialization pin (BEA13) is pulled up (EEAI = 1)]. The user can then enable the McBSP2 peripheral (disabling EEPROM) by dynamically changing MCBSP2_EN to a "1" after the device is initialized (out of reset).
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-
If the PCI is disabled (PCI_EN = 0), the HPI peripheral is enabled and GP[15:9] pins can be programmed as GPIO, provided the GPxEN and GPxDIR bits are properly configured. This means all multiplexed HPI/PCI pins function as HPI and all standalone PCI pins (PCBE0 and XSP_CS) are tied-off (Hi-Z). Also, the multiplexed GPIO/PCI pins can be used as GPIO with the proper software configuration of the GPIO enable and direction registers (for more details, see Table 29).
-
If the PCI is enabled (PCI_EN = 1), the HPI peripheral is disabled. This means all multiplexed HPI/PCI pins function as PCI. Also, the multiplexed GPIO/PCI pins function as PCI pins (for more details, see Table 29).
-
The MCBSP2_EN pin, in combination with the PCI_EN pin, controls the selection of the McBSP2 peripheral and the PCI internal EEPROM (for more details, see Table 27 and its footnotes).
other device configurations
Table 28 describes the C6414, C6415, and C6416 devices configuration pins, which are set up via external pullup/pulldown resistors through the specified EMIFB address bus pins (BEA[20:13, 11, 9:7]) and the HD5 pin. For more details on these device configuration pins, see the Terminal Functions table and the Debugging Considerations section.
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DEVICE CONFIGURATIONS (CONTINUED)
Table 28. Device Configuration Pins (BEA[20:13, 9:7], HD5, and BEA11)
CONFIGURATION PIN BEA20 NO. FUNCTIONAL DESCRIPTION Device Endian mode (LEND) 0 - System operates in Big Endian mode 1 - System operates in Little Endian mode (default) Bootmode [1:0] 00 - No boot 01 - HPI boot 10 - EMIFB 8-bit ROM boot with default timings (default mode) 11 - Reserved EMIFA input clock select Clock mode select for EMIFA (AECLKIN_SEL[1:0]) 00 - AECLKIN (default mode) 01 - CPU/4 Clock Rate 10 - CPU/6 Clock Rate 11 - Reserved EMIFB input clock select Clock mode select for EMIFB (BECLKIN_SEL[1:0]) 00 - BECLKIN (default mode) 01 - CPU/4 Clock Rate 10 - CPU/6 Clock Rate 11 - Reserved PCI EEPROM Auto-Initialization (EEAI) [C6415 and C6416 devices only] [The C6414 device does not support the PCI peripheral; for proper device operation, do not oppose the internal pulldown (IPD) on the BEA13 pin.] PCI auto-initialization via external EEPROM 0 - PCI auto-initialization through EEPROM is disabled; the PCI peripheral uses the specified PCI default values (default). 1 - PCI auto-initialization through EEPROM is enabled; the PCI peripheral is configured through EEPROM provided the PCI peripheral pin is enabled (PCI_EN = 1) and the McBSP2 peripheral pin is disabled (MCBSP2_EN = 0). Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up. For more information on the PCI EEPROM default values, see the TMS320C6000 DSP Peripheral Component Interconnect (PCI) Reference Guide (literature number SPRU581). UTOPIA Enable (UTOPIA_EN) [C6415 and C6416 devices only] [The C6414 device does not support the UTOPIA peripheral; for proper device operation, do not oppose the internal pulldown (IPD) on the BEA11 pin.] UTOPIA peripheral enable (functional) BEA11 D16 0 - UTOPIA peripheral disabled (McBSP1 functions are enabled). [default] This means all multiplexed McBSP1/UTOPIA pins function as McBSP1 and all other standalone UTOPIA pins are tied-off (Hi-Z). 1 - UTOPIA peripheral enabled (McBSP1 functions are disabled). This means all multiplexed McBSP1/UTOPIA pins now function as UTOPIA and all other standalone McBSP1 pins are tied-off (Hi-Z).
E16
BEA[19:18]
[D18, C18]
BEA[17:16]
[B18, A18]
BEA[15:14]
[D17, C17]
BEA13
B17
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DEVICE CONFIGURATIONS (CONTINUED)
Table 28. Device Configuration Pins (BEA[20:13, 9:7], HD5, and BEA11) (Continued)
CONFIGURATION PIN NO. C6414 Devices BEA7 BEA8 BEA9 D15 A16 B16 FUNCTIONAL DESCRIPTION C6415 Devices C6416 Devices Do not oppose IPD Pullup Pullup
Do not oppose internal pulldown (IPD) Pullup Do not oppose IPD Do not oppose IPD Do not oppose IPD Do not oppose IPD
For proper device operation, this pin must be externally pulled up with a 1-k resistor. HPI peripheral bus width (HPI_WIDTH) 0 - HPI operates as an HPI16. (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the Hi-Z state.) 1 - HPI operates as an HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
HD5
Y1
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DEVICE CONFIGURATIONS (CONTINUED) multiplexed pins
Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Some of these pins are configured by software, and the others are configured by external pullup/pulldown resistors only at reset. Those muxed pins that are configured by software can be programmed to switch functionalities at any time. Those muxed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. Table 29 identifies the multiplexed pins on the C6414, C6415, and C6416 devices; shows the default (primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to configure specific multiplexed functions.
debugging considerations
It is recommended that external connections be provided to device configuration pins, including CLKMODE[1:0], BEA[20:13, 11, 9:7], HD5/AD5, PCI_EN, and MCBSP2_EN. Although internal pullup/pulldown resistors exist on these pins (except for HD5/AD5), providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes. Internal pullup/pulldown resistors also exist on the non-configuration pins on the BEA bus (BEA[12, 10, 6:1]). Do not oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown resistors. If an external controller provides signals to these non-configuration pins, these signals must be driven to the default state of the pins at reset, or not be driven at all. For the internal pullup/pulldown resistors on the C6414, C6415, and C6416 device pins, see the terminal functions table.
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DEVICE CONFIGURATIONS (CONTINUED)
Table 29. C6414, C6415, and C6416 Device Multiplexed Pins
MULTIPLEXED PINS NAME CLKOUT4/GP1 NO. AE6 DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION These pins are software-configurable. To use these pins as GPIO pins, the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input GPxDIR = 1: GPx pin is an output To use GP[15:9] as GPIO pins, the PCI needs to be disabled (PCI_EN = 0), the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input GPxDIR = 1: GPx pin is an output
CLKOUT4
GP1EN = 0 (disabled)
CLKOUT6/GP2
AD6
CLKOUT6
GP2EN = 0 (disabled)
CLKS2/GP8 GP9/PIDSEL GP10/PCBE3 GP11/PREQ
AE4 M3 L2 F1 J3 G4 F2 G3 AB11 AB13 AC9 AF11 AB12 AC8 AC10 AC2 AB3 AA2 T3 R1 T4 T1 T2 P1 R3 R4 R2
CLKS2
GP8EN = 0 (disabled)
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GP12/PGNT GP13/PINTA GP14/PCLK GP15/PRST DX1/UXADDR4 FSX1/UXADDR3 FSR1/UXADDR2 DR1/UXADDR1 CLKX1/URADDR4 CLKS1/URADDR3 CLKR1/URADDR2 CLKX2/XSP_CLK DR2/XSP_DI DX2/XSP_DO HD[31:0]/AD[31:0] HAS/PPAR HCNTL1/PDEVSEL HCNTL0/PSTOP HDS1/PSERR HDS2/PCBE1 HR/W/PCBE2 HHWIL/PTRDY HINT/PFRAME HCS/PPERR
None
GPxEN = 0 (disabled) PCI_EN = 0 (disabled)
DX1 FSX1 FSR1 DR1 CLKX1 CLKS1 CLKR1 CLKX2 DR2 DX2 HD[31:0] HAS HCNTL1 HCNTL0 HDS1 HDS2 HR/W HHWIL (HPI16 only) HINT HCS PCI_EN = 0 (disabled) By default, HPI is enabled upon reset (PCI is disabled). To enable the PCI peripheral an external pullup resistor (1 k) must be provided k) on the PCI_EN pin (setting PCI_EN = 1 at reset). UTOPIA_EN (BEA11) = 0 (disabled) By default, McBSP1 is enabled upon reset (UTOPIA is disabled). To enable the UTOPIA peripheral, an external pullup resistor (1 k) must be provided on the BEA11 pin (setting UTOPIA_EN = 1 at reset).
HRDY/PIRDY P4 HRDY For the C6415 and C6416 devices, all other standalone UTOPIA and PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled [UTOPIA_EN (BEA11) = 0 or PCI_EN = 0]. The C6414 device does not support the PCI and UTOPIA peripherals. These are the only multiplexed pins on the C6414 device, all other pins are standalone peripheral functions and are not muxed. For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table.
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Terminal Functions
SIGNAL NAME NO. TYPE IPD/ IPU CLOCK/PLL CONFIGURATION CLKIN CLKOUT4/GP1 CLKOUT6/GP2 CLKMODE1 CLKMODE0 PLLV TMS TDO TDI TCK TRST EMU11 EMU10 EMU9 EMU8 EMU7 EMU6 EMU5 EMU4 EMU3 EMU2 H4 AE6 AD6 G1 H2 J6 AB16 AE19 AF18 AF16 AB15 AC18 AD18 AE18 AC17 AF17 AD17 AE17 AC16 AD16 AE16 I I/O/Z I/O/Z I I A# I O/Z I I I I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z IPU IPU IPU IPU IPD IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPD IPD IPD IPD IPD Clock Input. This clock is the input to the on-chip PLL. Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 1 pin (I/O/Z). Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 2 pin (I/O/Z). Clock mode select * Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x6, or x12. For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this data sheet. PLL voltage supply JTAG EMULATION JTAG test-port mode select JTAG test-port data in JTAG test-port clock JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG Compatibility Statement section of this data sheet. Emulation pin 11. Reserved for future use, leave unconnected. Emulation pin 10. Reserved for future use, leave unconnected. Emulation pin 9. Reserved for future use, leave unconnected. Emulation pin 8. Reserved for future use, leave unconnected. Emulation pin 7. Reserved for future use, leave unconnected. Emulation pin 6. Reserved for future use, leave unconnected. Emulation pin 5. Reserved for future use, leave unconnected. Emulation pin 4. Reserved for future use, leave unconnected. Emulation pin 3. Reserved for future use, leave unconnected. Emulation pin 2. Reserved for future use, leave unconnected. Emulation [1:0] pins * Select the device functional mode of operation Operation EMU[1:0] 00 Boundary Scan/Normal Mode (see Note) 01 Reserved 10 Reserved 11 Emulation/Normal Mode [default] (see the IEEE 1149.1 JTAG Compatibility Statement section of this data sheet) Normal mode refers to the DSPs normal operational mode, when the DSP is free running. The DSP can be placed in normal operational mode when the EMU[1:0] pins are configured for either Boundary Scan or Emulation. Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the internal pulldown (IPD) on the TRST signal must not be opposed in order to operate in Normal mode. For the Boundary Scan mode pulldown EMU[1:0] pins with a dedicated 1-k resister. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin. # A = Analog signal (PLL Filter) JTAG test-port data out DESCRIPTION
EMU1 EMU0
AC15 AF15
I/O/Z
IPU
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Terminal Functions (Continued)
SIGNAL NAME RESET NMI GP7/EXT_INT7 GP6/EXT_INT6 GP5/EXT_INT5 GP4/EXT_INT4 GP15/PRST GP14/PCLK GP13/PINTA GP12/PGNT GP11/PREQ NO. AC7 B4 AF4 AD5 AE5 AF5 G3 F2 G4 J3 F1 L2 M3 AC6 IPD I/O/Z I/O/Z IPU TYPE IPD/ IPU DESCRIPTION
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS I I IPD Device reset Nonmaskable interrupt, edge-driven (rising edge) General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The default after reset setting is GPIO enabled as input-only. * When these pins function as External Interrupts [by selecting the corresponding interrupt enable register bit (IER.[7:4])], they are edge-driven and the polarity can be independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]). General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default. GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default. GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default. GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default. GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default. GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default. GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default. GPIO 3 pin (I/O/Z). The default after reset setting is GPIO 3 enabled as input-only. GPIO 0 pin. The general-purpose I/O 0 pin (GPIO 0) (I/O/Z) can be programmed as GPIO 0 (input only) [default] or as GPIO 0 (output only) pin or output as a general-purpose interrupt (GP0INT) signal (output only). McBSP2 external clock source (CLKS2) [input only] [default] or this pin can be programmed as a GPIO 8 pin (I/O/Z). Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 2 pin (I/O/Z). Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 1 pin (I/O/Z).
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GP10/PCBE3 GP9/PIDSEL GP3
GP0
AF6
IPD
CLKS2/GP8 CLKOUT6/GP2 CLKOUT4/GP1
AE4 AD6 AE6
I/O/Z I/O/Z I/O/Z
IPD IPD IPD
HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 or C6416 devices only] PCI enable pin. This pin controls the selection (enable/disable) of the HPI and GP[15:9], or PCI peripherals (for the C6415 and C6416 devices). This pin works in conjunction with the MCBSP2_EN pin to enable/disable other peripherals (for more details, see the Device Configurations section of this data sheet). The C6414 device does not support the PCI peripheral; for proper device operation, do not oppose the internal pulldown (IPD) on this pin. HINT/PFRAME HCNTL1/ PDEVSEL HCNTL0/ PSTOP HHWIL/PTRDY R4 R1 T4 R3 I/O/Z I/O/Z I/O/Z I/O/Z Host interrupt from DSP to host (O) [default] or PCI frame (I/O/Z) Host control - selects between control, address, or data registers (I) [default] or PCI device select (I/O/Z). Host control - selects between control, address, or data registers (I) [default] or PCI stop (I/O/Z) Host half-word select - first or second half-word (not necessarily high or low order) [For HPI16 bus width selection only] (I) [default] or PCI target ready (I/O/Z)
PCI_EN
AA4
I
IPD
HR/W/PCBE2 P1 I/O/Z Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions for this device. For the C6414 device, only these pins are multiplexed pins.
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Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION
HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 or C6416 devices only] (CONTINUED) HAS/PPAR HCS/PPERR HDS1/PSERR HDS2/PCBE1 HRDY/PIRDY HD31/AD31 HD30/AD30 HD29/AD29 HD28/AD28 HD27/AD27 HD26/AD26 HD25/AD25 HD24/AD24 HD23/AD23 HD22/AD22 HD21/AD21 HD20/AD20 HD19/AD19 HD18/AD18 HD17/AD17 HD16/AD16 HD15/AD15 HD14/AD14 HD13/AD13 HD12/AD12 HD11/AD11 HD10/AD10 HD9/AD9 HD8/AD8 HD7/AD7 HD6/AD6 HD5/AD5 HD4/AD4 HD3/AD3 HD2/AD2 HD1/AD1 HD0/AD0 T3 R2 T1 T2 P4 J2 K3 J1 K4 K2 K1 L4 L1 M4 M2 N4 M1 N5 N1 P5 U4 U1 U3 U2 V4 V1 V3 V2 W2 W4 Y1 Y3 Y2 Y4 AA1 I/O/Z Host-port data (I/O/Z) [default] (C64x) or PCI data-address bus (I/O/Z) [C6415 and C6416] As HPI data bus (PCI_EN pin = 0) * Used for transfer of data, address, and control * Host-Port bus width user-configurable at device reset via a 10-k resistor pullup/pulldown resistor on the HD5 pin: HD5 pin = 0: HPI operates as an HPI16. (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the high-impedance state.) HD5 pin = 1: HPI operates as an HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.) As PCI data-address bus (PCI_EN pin = 1) [C6415 and C6416 devices only] * Used for transfer of data and address The C6414 device does not support the PCI peripheral; therefore, the HPI peripheral pins are standalone peripheral functions, not muxed. L3 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Host address strobe (I) [default] or PCI parity (I/O/Z) Host chip select (I) [default] or PCI parity error (I/O/Z) Host data strobe 1 (I) [default] or PCI system error (I/O/Z) Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z) Host ready from DSP to host (O) [default] or PCI initiator ready (I/O/Z).
AA3 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions for this device.
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Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION
HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 or C6416 devices only] (CONTINUED) PCBE0 W3 I/O/Z PCI command/byte enable 0 (I/O/Z). When PCI is disabled (PCI_EN = 0), this pin is tied-off. For the C6414 device this pin is "Reserved (leave unconnected, do not connect to power or ground)." IPD PCI serial interface chip select (O). When PCI is disabled (PCI_EN = 0), this pin is tied-off. For the C6414 device this pin is "Reserved (leave unconnected, do not connect to power or ground)." McBSP2 transmit clock (I/O/Z) [default] or PCI serial interface clock (O) (PCI_EN = 1). McBSP2 receive data (I) [default] or PCI serial interface data in (I). In PCI mode (PCI_EN = 1), this pin is connected to the output data pin of the serial PROM. McBSP2 transmit data (O/Z) [default] or PCI serial interface data out (O). In PCI mode (PCI_EN = 1), this pin is connected to the input data pin of the serial PROM. General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default. GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default. GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default. I/O/Z GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default. GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default. GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default. GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default. EMIFA (64-bit) - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY||k O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU EMIFA byte-enable control * Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory. * Byte-write enables for most types of memory * Can be directly connected to SDRAM read and write mask signal (SDQM) EMIFA memory space enables * Enabled by bits 28 through 31 of the word address * Only one pin is asserted during any external data access
XSP_CS CLKX2/ XSP_CLK DR2/XSP_DI DX2/XSP_DO
AD1
O
AC2 AB3 AA2 G3 F2 G4 J3 F1 L2 M3 L26 K23 K24 K25 T23 T24 R25 R26 M25 M26 L23 L24
I/O/Z I O/Z
IPD IPU IPU
ADVANCE INFORMATION
GP15/PRST GP14/PCLK GP13/PINTA GP12/PGNT GP11/PREQ GP10/PCBE3 GP9/PIDSEL ACE3 ACE2 ACE1 ACE0 ABE7 ABE6 ABE5 ABE4 ABE3 ABE2 ABE1 ABE0
APDT M22 O/Z IPU EMIFA peripheral data transfer, allows direct transfer between external peripherals I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions for this device. || These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. kTo maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL NAME AHOLDA AHOLD ABUSREQ NO. N22 V23 P22 TYPE IPD/ IPU DESCRIPTION EMIFA (64-BIT) - BUS ARBITRATION||k O I O IPU IPU IPU EMIFA hold-request-acknowledge to the host EMIFA hold request from the host EMIFA bus request output EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the BEA[17:16] pins. AECLKIN is the default for the EMIFA input clock. EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) frequency divided-by-1, -2, or -4. EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) frequency].
EMIFA (64-BIT) - ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL||k AECLKIN H25 I IPD
AECLKOUT2 AECLKOUT1
J23 J26
O/Z O/Z
IPD IPD
AARE/ ASDCAS/ ASADS/ASRE
J25
O/Z
IPU
AAOE/ ASDRAS/ ASOE AAWE/ ASDWE/ ASWE ASDCKE ASOE3 AARDY AEA22 AEA21 AEA20 AEA19 AEA18 AEA17 AEA16 AEA15 AEA14 AEA13 AEA12
J24
O/Z
IPU
EMIFA asynchronous memory output-enable/SDRAM row-address strobe/programmable synchronous interface output-enable EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable synchronous interface write-enable EMIFA SDRAM clock-enable (used for self-refresh mode). [EMIFA module only.] * If SDRAM is not in system, ASDCKE can be used as a general-purpose output. EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO interface) Asynchronous memory ready input EMIFA (64-BIT) - ADDRESS||k
K26
O/Z
IPU
L25 R22 L22 T22 V24 V25 V26 U23 U24 U25 U26 T25 T26 R23
O/Z O/Z I
IPU IPU IPU
O/Z
IPD
EMIFA external address (doubleword address)
AEA11 R24 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) || These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. kTo maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
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ADVANCE INFORMATION
EMIFA asynchronous memory read-enable/SDRAM column-address strobe/programmable synchronous interface-address strobe or read-enable * For programmable synchronous interface, the RENEN field in the CE Space Secondary Control Register (CExSEC) selects between ASADS and ASRE: If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal. If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal.
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL NAME AEA10 AEA9 AEA8 AEA7 AEA6 AEA5 AEA4 AEA3 AED63 AED62 AED61 AED60 AED59 AED58 AED57 AED56 AED55 AED54 AED53 AED52 AED51 AED50 AED49 AED48 AED47 AED46 AED45 AED44 AED43 AED42 AED41 AED40 AED39 AED38 NO. P23 P24 P26 N23 N24 N26 M23 M24 EMIFA (64-bit) - DATA||k AF24 AF23 AE23 AE22 AD22 AF22 AD21 AE21 AC21 AF21 AD20 AE20 AC20 AF20 AC19 AD19 W24 W23 Y26 Y23 Y25 Y24 AA26 AA23 AA25 AA24 I/O/Z IPU EMIFA external data O/Z IPD EMIFA external address (doubleword address) TYPE IPD/ IPU DESCRIPTION EMIFA (64-BIT) - ADDRESS||k (CONTINUED)
ADVANCE INFORMATION
AED37 AB26 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) || These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. kTo maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL NAME AED36 AED35 AED34 AED33 AED32 AED31 AED30 AED29 AED28 AED27 AED26 AED25 AED24 AED23 AED22 AED21 AED20 AED19 AED18 AED17 AED16 AED15 AED14 AED13 AED12 AED11 AED10 AED9 AED8 AED7 AED6 AED5 AED4 AED3 AED2 AED1 NO. AB24 AB25 AC25 AC26 AD26 C26 D26 D25 E25 E24 E26 F25 F23 F26 G24 G25 G23 G26 H23 H24 C19 D19 A20 D20 B20 C20 A21 D21 B21 C21 A22 C22 B22 B23 A23 I/O/Z IPU EMIFA external data F24 TYPE IPD/ IPU DESCRIPTION EMIFA (64-bit) - DATA||k (CONTINUED)
AED0 A24 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) || These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. kTo maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
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ADVANCE INFORMATION
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL NAME BCE3 BCE2 BCE1 BCE0 BBE1 BBE0 BPDT BHOLDA NO. A13 C12 B12 A12 D13 C13 E12 E13 B19 E14 TYPE IPD/ IPU DESCRIPTION
EMIFB (16-bit) - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY||k O/Z O/Z O/Z O/Z O/Z O/Z O/Z O I O IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU EMIFB byte-enable control * Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory. * Byte-write enables for most types of memory * Can be directly connected to SDRAM read and write mask signal (SDQM) EMIFB peripheral data transfer, allows direct transfer between external peripherals EMIFB (16-BIT) - BUS ARBITRATION||k EMIFB hold-request-acknowledge to the host EMIFB hold request from the host EMIFB bus request output EMIFB external input clock. The EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the BEA[15:14] pins. BECLKIN is the default for the EMIFB input clock. EMIFB output clock 2. Programmable to be EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock) frequency divided by 1, 2, or 4. EMIFB output clock 1 [at EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock) frequency]. EMIFB asynchronous memory read-enable/SDRAM column-address strobe/programmable synchronous interface-address strobe or read-enable * For programmable synchronous interface, the RENEN field in the CE Space Secondary Control Register (CExSEC) selects between BSADS and BSRE: If RENEN = 0, then the BSADS/BSRE signal functions as the BSADS signal. If RENEN = 1, then the BSADS/BSRE signal functions as the BSRE signal. EMIFB asynchronous memory output-enable/SDRAM row-address strobe/programmable synchronous interface output-enable EMIFB asynchronous memory write-enable/SDRAM write-enable/programmable synchronous interface write-enable EMIFB synchronous memory output enable for BCE3 (for glueless FIFO interface) EMIFB memory space enables * Enabled by bits 26 through 31 of the word address * Only one pin is asserted during any external data access
ADVANCE INFORMATION
BHOLD BBUSREQ
EMIFB (16-BIT) - ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL||k BECLKIN A11 I IPD
BECLKOUT2 BECLKOUT1
D11 D12
O/Z O/Z
IPD IPD
BARE/ BSDCAS/ BSADS/BSRE
A10
O/Z
IPU
BAOE/ BSDRAS/ BSOE BAWE/BSDWE/ BSWE BSOE3
B11
O/Z
IPU
C11 E15
O/Z O/Z
IPU IPU
BARDY E11 I IPU EMIFB asynchronous memory ready input I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) || These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. kTo maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU EMIFB (16-BIT) - ADDRESS||k BEA20 BEA19 BEA18 BEA17 BEA16 BEA15 BEA14 BEA13 BEA12 BEA11 BEA10 BEA9 BEA8 BEA7 BEA6 BEA5 BEA4 BEA3 BEA2 BEA1 E16 D18 C18 B18 A18 D17 C17 B17 A17 D16 C16 I/O/Z B16 A16 D15 C15 B15 A15 D14 C14 A14 Also for proper C6414 device operation, do not oppose the IPDs on the BEA7, BEA8, and BEA9 pins. For proper C6415 device operation, the BEA7 pin must be externally pulled up with a 1-k 1-k resistor. For proper C6416 device operation, the BEA8 and BEA9 pins must be externally pulled up with a 1-k resistor. IPD IPU IPU EMIFB external address (half-word address) (O/Z) * Also controls initialization of DSP modes at reset (I) via pullup/pulldown resistors - Device Endian mode BEA20: 0 - Big Endian 1 - Little Endian (default mode) - Boot mode BEA[19:18]: 00 - No boot 01 - HPI boot 10 - EMIFB 8-bit ROM boot with default timings (default mode) 11 - Reserved - EMIF clock select BEA[17:16]: Clock mode select for EMIFA (AECLKIN_SEL[1:0]) 00 - AECLKIN (default mode) 01 - CPU/4 Clock Rate 10 - CPU/6 Clock Rate 11 - Reserved BEA[15:14]: Clock mode select for EMIFB (BECLKIN_SEL[1:0]) 00 - BECLKIN (default mode) 01 - CPU/4 Clock Rate 10 - CPU/6 Clock Rate 11 - Reserved - PCI EEPROM Auto-Initialization (EEAI) [C6415 and C6416 devices only] BEA13: PCI auto-initialization via external EEPROM If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up. 0 - PCI auto-initialization through EEPROM is disabled (default). 1 - PCI auto-initialization through EEPROM is enabled. - UTOPIA Enable (UTOPIA_EN) [C6415 and C6416 devices only] BEA11: UTOPIA peripheral enable (functional) 0 - UTOPIA disabled (McBSP1 enabled) [default] 1 - UTOPIA enabled (McBSP1 disabled) The C6414 device does not support the PCI and UTOPIA peripherals; for proper device operation, do not oppose the internal pulldowns (IPDs) on the BEA13 and BEA11 pins. DESCRIPTION
For more details, see the Device Configurations section of this data sheet. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) || These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. kTo maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL NAME BED15 BED14 BED13 BED12 BED11 BED10 BED9 BED8 BED7 BED6 BED5 BED4 BED3 BED2 BED1 BED0 NO. D7 B6 C7 A6 D8 B7 C8 A7 C9 B8 D9 B9 C10 A9 D10 B10 MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2) MCBSP2_EN CLKS2/GP8 CLKR2 CLKX2/ XSP_CLK DR2/XSP_DI DX2/XSP_DO FSR2 FSX2 AF3 AE4 AB1 AC2 AB3 AA2 AC1 AB2 I I/O/Z I/O/Z I/O/Z I O/Z I/O/Z I/O/Z IPD IPD IPD IPD IPU IPU IPD IPD McBSP2 enable pin. This pin works in conjunction with the PCI_EN pin to enable/disable other peripherals (for more details, see the Device Configurations section of this data sheet). McBSP2 external clock source (CLKS2) [input only] [default] or this pin can also be programmed as a GPIO 8 pin (I/O/Z). McBSP2 receive clock. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin = 0), this pin is tied-off. McBSP2 transmit clock (I/O/Z) [default] or PCI serial interface clock (O). McBSP2 receive data (I) [default] or PCI serial interface data in (I). In PCI mode, this pin is connected to the output data pin of the serial PROM. McBSP2 transmit data (O/Z) [default] or PCI serial interface data out (O). In PCI mode, this pin is connected to the input data pin of the serial PROM. McBSP2 receive frame sync. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin = 0), this pin is tied-off. McBSP2 transmit frame sync. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin = 0), this pin is tied-off. I/O/Z IPU EMIFB external data TYPE IPD/ IPU EMIFB (16-bit) - DATA||k DESCRIPTION
ADVANCE INFORMATION
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins except CLKS2/GP8 are standalone peripheral functions for this device. || These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. kTo maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL NAME CLKS1/ URADDR3 CLKR1/ URADDR2 CLKX1/ URADDR4 DR1/ UXADDR1 DX1/ UXADDR4 FSR1/ UXADDR2 FSX1/ UXADDR3 NO. TYPE IPD/ IPU DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) AC8 AC10 AB12 AF11 AB11 AC9 AB13 I I/O/Z I/O/Z I I/O/Z I/O/Z I/O/Z McBSP1 external clock source (as opposed to internal) (I) [default] or UTOPIA receive address 3 pin (I) McBSP1 receive clock (I/O/Z) [default] or UTOPIA receive address 2 pin (I) McBSP1 transmit clock (I/O/Z) [default] or UTOPIA receive address 4 pin (I) McBSP1 receive data (I) [default] or UTOPIA transmit address 1 pin (I) McBSP1 transmit data (O/Z) [default] or UTOPIA transmit address 4 pin (I) McBSP1 receive frame sync (I/O/Z) [default] or UTOPIA transmit address 2 pin (I) McBSP1 transmit frame sync (I/O/Z) [default] or UTOPIA transmit address 3 pin (I) MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 CLKR0 CLKX0 DR0 DX0 FSR0 FSX0 TOUT2 TINP2 TOUT1 TINP1 TOUT0 F4 D1 E1 D2 E2 C1 E3 A4 C5 B5 A5 D6 I I/O/Z I/O/Z I O/Z I/O/Z I/O/Z O/Z I O/Z I O/Z IPD IPD IPD IPU IPU IPD IPD IPD IPD IPD IPD IPD McBSP0 external clock source (as opposed to internal) McBSP0 receive clock McBSP0 transmit clock McBSP0 receive data McBSP0 transmit data McBSP0 receive frame sync McBSP0 transmit frame sync TIMER 2 Timer 2 or general-purpose output Timer 2 or general-purpose input TIMER 1 Timer 1 or general-purpose output Timer 1 or general-purpose input TIMER 0 Timer 0 or general-purpose output TINP0 C6 I IPD Timer 0 or general-purpose input I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions for this device.
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ADVANCE INFORMATION
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION
UNIVERSAL TEST AND OPERATIONS PHY INTERFACE FOR ASYNCHRONOUS TRANSFER MODE (ATM) [UTOPIA SLAVE] [C6415 and C6416 devices only] UTOPIA SLAVE (ATM CONTROLLER) - TRANSMIT INTERFACE UXCLKY AD11 I h Source clock for UTOPIA transmit driven by Master ATM Controller. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. Transmit cell available status output signal from UTOPIA Slave. 0 indicates a complete cell is NOT available for transmit 1 indicates a complete cell is available for transmit When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. UXENBY UTOPIA transmit interface enable input signal. Asserted by the Master ATM Controller to indicate that the UTOPIA Slave should put out on the Transmit Data Bus the first byte of valid data and the UXSOC signal in the next clock cycle. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. Transmit Start-of-Cell signal. This signal is output by the UTOPIA Slave on the rising edge of the UXCLK, indicating that the first valid byte of the cell is available on the 8-bit Transmit Data Bus (UXDATA[7:0]). When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. McBSP1 [default] or UTOPIA transmit address pins As UTOPIA transmit address pins UXADDR[4:0] (I), UTOPIA_EN (BEA11 pin) = 1: * 5-bit Slave transmit address input pins driven by the Master ATM Controller to identify and select one of the Slave devices (up to 31 possible) in the ATM System. AB11 I/O/Z * UXADDR0 pin is tied off when the UTOPIA peripheral is disabled [UTOPIA_EN (BEA11 pin) = 0]
UXCLAVY
AC14
O/Z
AE15
I
ADVANCE INFORMATION
UXSOCY
AC13
O/Z
DX1/ UXADDR4
For the McBSP1 pin functions (UTOPIA_EN (BEA11 pin) = 0 [default]), see the MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) section of this table. FSX1/ UXADDR3 FSR1/ UXADDR2 DR1/ UXADDR1 UXADDR0Y AB13 I/O/Z McBSP1 [default] or UTOPIA transmit address pins As UTOPIA transmit address pins UXADDR[4:0] (I), UTOPIA_EN (BEA11 pin) = 1: * 5-bit Slave transmit address input pins driven by the Master ATM Controller to identify and select one of the Slave devices (up to 31 possible) in the ATM System. * UXADDR0 pin is tied off when the UTOPIA peripheral is disabled [UTOPIA_EN (BEA11 pin) = 0]
AC9
I/O/Z
AF11 AE9
I I

For the McBSP1 pin functions (UTOPIA_EN (BEA11 pin) = 0 [default]), see the MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) section of this table. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions for this device. hFor the C6415 and C6416 devices, external pulldowns required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-k resistor must be used to externally pull down each of these pins. If these pins are "no connects", then only UXCLK and URCLK need to be pulled down and other pulldowns are not necessary. For the C6415 and C6416 devices, external pullups required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-k resistor must be used to externally pull up each of these pins. If these pins are "no connects", then the pullups are not necessary. The C6414 device does not support the UTOPIA peripheral; therefore, these standalone UTOPIA pins are Reserved (leave unconnected, do not connect to power or ground) with the exception of UXCLK and URCLK which should be connected to a 10-k pulldown resistor (see the square [h] footnote).
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL NAME UXDATA7Y UXDATA6Y UXDATA5Y UXDATA4Y UXDATA3Y UXDATA2Y UXDATA1Y UXDATA0Y NO. AD10 AD9 AD8 AE8 AF9 AF7 AE7 AD7 UTOPIA SLAVE (ATM CONTROLLER) - RECEIVE INTERFACE URCLKY AD12 I h Source clock for UTOPIA receive driven by Master ATM Controller. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. O/Z 8-bit Transmit Data Bus Using the Transmit Data Bus, the UTOPIA Slave (on the rising edge of the UXCLK) transmits the 8-bit ATM cells to the Master ATM Controller. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), these pins are tiedoff. TYPE IPD/ IPU DESCRIPTION
UTOPIA SLAVE (ATM CONTROLLER) - TRANSMIT INTERFACE (CONTINUED)
URCLAVY
AF14
O/Z
When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. URENBY UTOPIA receive interface enable input signal. Asserted by the Master ATM Controller to indicate to the UTOPIA Slave to sample the Receive Data Bus (URDATA[7:0]) and URSOC signal in the next clock cycle or thereafter. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. Receive Start-of-Cell signal. This signal is output by the Master ATM Controller to indicate to the UTOPIA Slave that the first valid byte of the cell is available to sample on the 8-bit Receive Data Bus (URDATA[7:0]). When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. McBSP1 [default] or UTOPIA receive address pins As UTOPIA receive address pins URADDR[4:0] (I), UTOPIA_EN (BEA11 pin) = 1: * 5-bit Slave receive address input pins driven by the Master ATM Controller to identify and select one of the Slave devices (up to 31 possible) in the ATM System. * URADDR1 and URADDR0 pins are tied off when the UTOPIA peripheral is disabled [UTOPIA_EN (BEA11 pin) = 0]
AD15
I
URSOCY
AB14
I
h
CLKX1/ URADDR4 CLKS1/ URADDR3 CLKR1/ URADDR2 URADDR1Y URADDR0Y
AB12 AC8 AC10 AF10 AE10
I/O/Z I I/O/Z I I

For the McBSP1 pin functions (UTOPIA_EN (BEA11 pin) = 0 [default]), see the MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) section of this table. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. hExternal pulldowns required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-k resistor must be used to externally pull down each of these pins. If these pins are "no connects", then only UXCLK and URCLK need to be pulled down and other pulldowns are not necessary. External pullups required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-k resistor must be used to externally pull up each of these pins. If these pins are "no connects", then the pullups are not necessary. The C6414 device does not support the UTOPIA peripheral; therefore, these standalone UTOPIA pins are Reserved (leave unconnected, do not connect to power or ground) with the exception of UXCLK and URCLK which should be connected to a 10-k pulldown resistor (see the square [h] footnote).
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Receive cell available status output signal from UTOPIA Slave. 0 indicates NO space is available to receive a cell from Master ATM Controller 1 indicates space is available to receive a cell from Master ATM Controller
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
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Terminal Functions (Continued)
SIGNAL NAME URDATA7Y URDATA6Y URDATA5Y URDATA4Y URDATA3Y URDATA2Y URDATA1Y URDATA0Y NO. AF12 AE11 AF13 AC11 AC12 AE12 AD14 AD13 RESERVED FOR TEST G14 H7 N20 P7 Y13 RSV R6 A3 G2 H3 J4 RSV K6 N3 P3 W25 IPD I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) hExternal pulldowns required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-k resistor must be used to externally pull down each of these pins. If these pins are "no connects", then only UXCLK and URCLK need to be pulled down and other pulldowns are not necessary. The C6414 device does not support the UTOPIA peripheral; therefore, these standalone UTOPIA pins are Reserved (leave unconnected, do not connect to power or ground) with the exception of UXCLK and URCLK which should be connected to a 10-k pulldown resistor (see the square [h] footnote). Reserved (leave unconnected, do not connect to power or ground) Reserved. This pin must be connected directly to DVDD for proper device operation. I h 8-bit Receive Data Bus. Using the Receive Data Bus, the UTOPIA Slave (on the rising edge of the URCLK) can receive the 8-bit ATM cell data from the Master ATM Controller. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), these pins are tiedoff. TYPE IPD/ IPU DESCRIPTION
UTOPIA SLAVE (ATM CONTROLLER) - RECEIVE INTERFACE (CONTINUED)
ADVANCE INFORMATION
RSV
Reserved. These pins must be connected directly to CVDD for proper device operation.
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Terminal Functions (Continued)
SIGNAL NAME NO. A2 A25 B1 B14 B26 E7 E8 E10 E17 E19 E20 F9 F12 F15 F18 G5 G22 H5 H22 DVDD J21 K5 K22 L5 M5 M6 M21 N2 P25 R5 R21 T5 U5 U22 V6 V21 W5 W22 Y5 Y22 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground S 3.3-V supply voltage (see the Power-Supply Decoupling section of this data sheet) F3 TYPE DESCRIPTION SUPPLY VOLTAGE PINS
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Terminal Functions (Continued)
SIGNAL NAME NO. AA9 AA12 AA15 AA18 AB7 AB8 AB10 DVDD AB17 AB19 AB20 AE1 AE13 AE26 AF2 AF25 A1 A26 B2 B25 C3 C24 D4 D23 E5 E22 F6 F7 CVDD F20 F21 G6 G7 G8 G10 G11 G13 G16 G17 G19 G20 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground 1.2-V supply voltage (-5E0 device) 1.25-V supply voltage (A-5E0 device) 1.4 V supply voltage (-6E3, A-6E3, -7E3 devices) (see the Power-Supply Decoupling section of this data sheet) S 3.3-V supply voltage (see the Power-Supply Decoupling section of this data sheet) TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED)
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Terminal Functions (Continued)
SIGNAL NAME NO. G21 H20 K7 K20 L7 L20 N7 P20 T7 T20 U7 W7 W20 Y6 Y7 Y8 Y10 Y11 CVDD Y14 Y16 Y17 Y19 Y20 Y21 AA6 AA7 AA20 AA21 AB5 AB22 AC4 AC23 AD3 AD24 AE2 AE25 AF1 AF26 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground S 1.2-V supply voltage (-5E0 device) 1.25-V supply voltage (A-5E0 device) 1.4 V supply voltage (-6E3, A-6E3, -7E3 devices) (see the Power-Supply Decoupling section of this data sheet) U20 TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED)
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Terminal Functions (Continued)
SIGNAL NAME NO. A8 A19 B3 B13 B24 C2 C4 C23 C25 D3 D5 D22 D24 E4 E6 E9 E18 E21 E23 VSS F5 F8 F10 F11 F13 F14 F16 F17 F19 F22 G9 G12 G15 G18 H1 H6 H21 H26 J5 J7 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground GND Ground pins TYPE GROUND PINS DESCRIPTION
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Terminal Functions (Continued)
SIGNAL NAME NO. J20 J22 K21 L6 L21 M7 M20 N6 N21 N25 P2 P21 R7 R20 T6 T21 U6 U21 VSS V5 V7 V20 V22 W1 W6 W21 W26 Y9 Y12 Y15 Y18 AA5 AA8 AA10 AA11 AA13 AA14 AA16 AA17 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground GND Ground pins P6 TYPE DESCRIPTION GROUND PINS (CONTINUED)
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Terminal Functions (Continued)
SIGNAL NAME NO. AA19 AA22 AB4 AB6 AB9 AB18 AB21 AB23 AC3 AC5 VSS AC22 AC24 AD2 AD4 AD23 AD25 AE3 AE14 AE24 AF8 AF19 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground GND Ground pins TYPE DESCRIPTION GROUND PINS (CONTINUED)
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development support
TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug) EVM (Evaluation Module) For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, DSP/BIOS, and XDS are trademarks of Texas Instruments.
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device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification Fully qualified production device
TMP
TMS
ADVANCE INFORMATION
Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. Fully qualified development-support product
TMDS
TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers describing their limitations and intended uses. Experimental devices (TMX) may not be representative of a final product and Texas Instruments reserves the right to change or discontinue these products without notice. TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GLZ), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -6E3 is 600-MHz CPU, 133-MHz EMIFA). Figure 4 provides a legend for reading the complete device name for any TMS320C64x DSP generation member. Table 30 displays the device part numbers and ordering information for TMS320C6414/C6415/C6416 in the GLZ package type. The ZLZ package is a 532-pin plastic BGA, with lead free balls. The ZLZ package type is available upon request. Please contact your TI sales representative for ordering information.
Table 30. TMS320C6414/C6415/C6416 Device Part Numbers (P/Ns) and Ordering Information
OPERATING CASE TEMPERATURE RANGE
DEVICE ORDERABLE P/N C6414 TMS32C6414EGLZ7E3 TMS32C6414EGLZ6E3
DEVICE SPEED, EMIF SPEED, SILICON REVISION
CVDD (CORE VOLTAGE)
DVDD (I/O VOLTAGE)
720 MHz/5760 MIPS, 133-MHz EMIFA, Silicon Rev. 2.0 600 MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. 2.0
1.4 V 1.4 V
3.3 V 3.3 V
0_C to 90_C 0_C to 90_C
TMS320 is a trademark of Texas Instruments.
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Table 30. TMS320C6414/C6415/C6416 Device Part Numbers (P/Ns) and Ordering Information (Continued)
DEVICE ORDERABLE P/N TMX2C6414EGLZA6E3 TMS32C6414EGLZ5E0 TMX32C6414EGLZA5E0 TMS32C6414DGLZ7E3 TMS32C6414DGLZ6E3 TMS32C6414DGLZA6E3 TMS32C6414DGLZ5E0 TMS32C6414DGLZA5E0 TMS32C6414CGLZ6E3 TMS32C6414CGLZ5E0 C6415 TMS32C6415EGLZ7E3 TMS32C6415EGLZ6E3 TMX32C6415EGLZA6E3 TMS32C6415EGLZ5E0 TMX32C6415EGLZA5E0 TMS32C6415DGLZ7E3 TMS32C6415DGLZ6E3 TMS32C6415DGLZA6E3 TMS32C6415DGLZ5E0 TMS32C6415DGLZA5E0 TMS32C6415CGLZ6E3 TMS32C6415CGLZ5E0 C6416 TMS32C6416EGLZ7E3 TMS32C6416EGLZ6E3 TMX32C6416EGLZA6E3 720 MHz/5760 MIPS, 133-MHz EMIFA, Silicon Rev. 2.0 600 MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. 2.0 600 MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. 2.0 1.4 V 1.4 V 1.4 V 3.3 V 3.3 V 3.3 V 0_C to 90_C 0_C to 90_C -40_C to 105_C 720 MHz/5760 MIPS, 133-MHz EMIFA, Silicon Rev. 2.0 600 MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. 2.0 600 MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. 2.0 500 MHz/4000 MIPS, 100-MHz EMIF, Silicon Rev. 2.0 500 MHz/4000 MIPS, 100-MHz EMIF, Silicon Rev. 2.0 720 MHz/5760 MIPS, 133-MHz EMIFA, Silicon Rev. 1.1 600 MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. 1.1 600 MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. 1.1 500 MHz/4000 MIPS, 100-MHz EMIF, Silicon Rev. 1.1 500 MHz/4000 MIPS, 100-MHz EMIF, Silicon Rev. 1.1 600 MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. 1.03 500 MHz/4000 MIPS, 100-MHz EMIF, Silicon Rev. 1.03 1.4 V 1.4 V 1.4 V 1.2 V 1.25 V 1.4 V 1.4 V 1.4 V 1.2 V 1.25 V 1.4 V 1.2 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 0_C to 90_C 0_C to 90_C -40_C to 105_C 0_C to 90_C -40_C to 105_C 0_C to 90_C 0_C to 90_C -40_C to 105_C 0_C to 90_C -40_C to 105_C 0_C to 90_C 0_C to 90_C DEVICE SPEED, EMIF SPEED, SILICON REVISION 600 MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. 2.0 500 MHz/4000 MIPS, 100-MHz EMIF, Silicon Rev. 2.0 500 MHz/4000 MIPS, 100-MHz EMIF, Silicon Rev. 2.0 720 MHz/5760 MIPS, 133-MHz EMIFA, Silicon Rev. 1.1 600 MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. 1.1 600 MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. 1.1 500 MHz/4000 MIPS, 100-MHz EMIF, Silicon Rev. 1.1 500 MHz/4000 MIPS, 100-MHz EMIF, Silicon Rev. 1.1 600 MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. 1.03 500 MHz/4000 MIPS, 100-MHz EMIF, Silicon Rev. 1.03 CVDD (CORE VOLTAGE) 1.4 V 1.2 V 1.25 V 1.4 V 1.4 V 1.4 V 1.2 V 1.25 V 1.4 V 1.2 V DVDD (I/O VOLTAGE) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V OPERATING CASE TEMPERATURE RANGE -40_C to 105_C 0_C to 90_C -40_C to 105_C 0_C to 90_C 0_C to 90_C -40_C to 105_C 0_C to 90_C -40_C to 105_C 0_C to 90_C 0_C to 90_C
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Table 30. TMS320C6414/C6415/C6416 Device Part Numbers (P/Ns) and Ordering Information (Continued)
DEVICE ORDERABLE P/N TMS32C6416EGLZ5E0 TMX32C6416EGLZA5E0 TMS32C6416DGLZ7E3 TMS32C6416DGLZ6E3 TMS32C6416DGLZA6E3 TMS32C6416DGLZ5E0 DEVICE SPEED, EMIF SPEED, SILICON REVISION 500 MHz/4000 MIPS, 100-MHz EMIF, Silicon Rev. 2.0 500 MHz/4000 MIPS, 100-MHz EMIF, Silicon Rev. 2.0 720 MHz/5760 MIPS, 133-MHz EMIFA, Silicon Rev. 1.1 600 MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. 1.1 600 MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. 1.1 500 MHz/4000 MIPS, 100-MHz EMIF, Silicon Rev. 1.1 500 MHz/4000 MIPS, 100-MHz EMIF, Silicon Rev. 1.1 600 MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. 1.03 500 MHz/4000 MIPS, 100-MHz EMIF, Silicon Rev. 1.03 TMS 32 PREFIX TMX = TMP = TMS = SMX= SMJ = SM = Experimental device Prototype device Qualified device Experimental device, MIL MIL-PRF-38535, QML High Rel (non-38535) C 6415E GLZ () CVDD (CORE VOLTAGE) 1.2 V 1.25 V 1.4 V 1.4 V 1.4 V 1.2 V 1.25 V 1.4 V 1.2 V DVDD (I/O VOLTAGE) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V OPERATING CASE TEMPERATURE RANGE 0_C to 90_C -40_C to 105_C 0_C to 90_C 0_C to 90_C -40_C to 105_C 0_C to 90_C -40_C to 105_C 0_C to 90_C 0_C to 90_C
ADVANCE INFORMATION
TMS32C6416DGLZA5E0 TMS32C6416CGLZ6E3 TMS32C6416CGLZ5E0
6E3 DEVICE SPEED RANGE 300 5E0 (500-MHz CPU, 100-MHz EMIF) 6E3 (600-MHz CPU, 133-MHz EMIFA) 7E3 (720-MHz CPU, 133-MHz EMIFA) TEMPERATURE RANGE (DEFAULT: 0C TO 90C) Blank = 0C to 90C, commercial temperature A = -40C to 105C, extended temperature PACKAGE TYPE GLZ = 532-pin plastic BGA ZLZ = 532-pin plastic BGA, with lead free balls DEVICE C64x DSP: 6411 6414E 6415E 6416E
DEVICE FAMILY 3 or 32 or 320 = TMS320t DSP family
TECHNOLOGY C = CMOS
6414D 6415D 6416D
6414C 6415C 6416C
See the Recommended Operating Conditions section of this data sheet for more details. The extended temperature "A version" devices may have different operating conditions than the commercial temperature devices. See the Recommended Operating Conditions section of this data sheet for more details. BGA = Ball Grid Array For the actual device part numbers (P/Ns) and ordering information, see Table 30 of this data sheet.
Figure 4. TMS320C64x DSP Device Nomenclature (Including the C6414, C6415, and C6416 Devices)
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documentation support
Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user's reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6000 DSP devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000 DSP CPU (core) architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) provides an overview and briefly describes the functionality of the peripherals available on the C6000 DSP platform of devices. This document also includes a table listing the peripherals available on the C6000 devices along with literature numbers and hyperlinks to the associated peripheral documents. The TMS320C64x Technical Overview (literature number SPRU395) gives an introduction to the C64x digital signal processor, and discusses the application areas that are enhanced by the C64x DSP VelociTI.2 VLIW architecture. The TMS320C6414, TMS320C6415, and TMS320C6416 Digital Signal Processors Silicon Errata (literature number SPRZ011) describes the known exceptions to the functional specifications for the TMS320C6414, TMS320C6415, and TMS320C6416 devices. The TMS320C6414/15/16 Power Consumption Summary application report (literature number SPRA811) discusses the power consumption for user applications with the TMS320C6414, TMS320C6415, and TMS320C6416 DSP devices. The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to properly use IBIS models to attain accurate timing analysis for a given system. The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). See the Worldwide Web URL for the How To Begin Development Today With the TMS320C6414, TMS320C6415, and TMS320C6416 DSPs application report (literature number SPRA718), which describes in more details the compatibility and similarities/differences among the C6414, C6415, C6416, and C6211 devices.
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clock PLL
Most of the internal C64x DSP clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock. To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5 shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes. To minimize the clock jitter, a single clean power supply should power both the C64x DSP device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and output clocks electricals section. Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended ranges of supply voltage and operating case temperature table and the input and output clocks electricals section). Table 31 lists some examples of compatible CLKIN external clock sources: Table 31. Compatible CLKIN External Clock Sources
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COMPATIBLE PARTS FOR EXTERNAL CLOCK SOURCES (CLKIN)
PART NUMBER JITO-2 STA series, ST4100 series
MANUFACTURER Fox Electronix SaRonix Corporation Epson America Corning Frequency Control Integrated Circuit Systems
Oscillators
SG-636 342 ICS525-02 MK1714
PLL Spread Spectrum Clock Generator
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clock PLL (continued)
3.3 V CPU Clock EMI filter C1 10 F C2 0.1 F /8 PLLV /4 CLKMODE0 CLKMODE1 CLKOUT4, McBSP Internal Clock CLKOUT6 Timer Internal Clock /2 Peripheral Bus
PLLMULT PLL x6, x12
/6
CLKIN
PLLCLK
1 0
00 01 10
/4
/2 ECLKIN Internal to C64x EMIF 00 01 10 EK2RATE (GBLCTL.[19,18])
(For the PLL Options, CLKMODE Pins Setup, and PLL Clock Frequency Ranges, see Table 32.)
ECLKOUT1
ECLKOUT2
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000 DSP device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI Filter). C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
Figure 5. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
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ECLKIN_SEL (DEVCFG.[17,16] and DEVCFG.[15,14])
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
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clock PLL (continued)
Table 32. TMS320C64x PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time
GLZ and ZLZ PACKAGE - 23 x 23 mm BGA CLKMODE1 CLKMODE0 0 0 1 0 1 0 CLKMODE (PLL MULTIPLY FACTORS) Bypass (x1) x6 x12 CLKIN RANGE (MHz) 30-75.75 30-75.75 30-60.6 CPU CLOCK FREQUENCY RANGE (MHz) 30-75.75 180-454.5 360-727.2 CLKOUT4 RANGE (MHz) 7.5-18.9 45-113.6 90-181.8 CLKOUT6 RANGE (MHz) 5-12.6 30-75.75 60-121.2 75 TYPICAL LOCK TIME (s) N/A
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1 1 Reserved - - - - - These clock frequency range values are applicable to a C64x-6E3 speed device. For -5E0 and -7E3 device speed values, see the CLKIN timing requirements table for the specific device speed. Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the C64x device to one of the valid PLL multiply clock modes (x6 or x12). With internal pulldown resistors on the CLKMODE pins (CLKMODE1, CLKMODE0), the default clock mode is x1 (bypass). Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 s, the maximum value may be as long as 250 s.
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general-purpose input/output (GPIO)
To use the GP[15:0] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register and the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured. GPxEN = GPxDIR = GPxDIR = 1 0 1 GP[x] pin is enabled GP[x] pin is an input GP[x] pin is an output
where "x" represents one of the 15 through 0 GPIO pins Figure 6 shows the GPIO enable bits in the GPEN register for the C6414/C6415/C6416 device. To use any of the GPx pins as general-purpose input/output functions, the corresponding GPxEN bit must be set to "1" (enabled). Default values are device-specific, so refer to Figure 6 for the C6414/15/16 default configuration.
31 24 23 Reserved 16
15 GP15 EN R/W-0
14 GP14 EN R/W-0
13 GP13 EN R/W-0
12 GP12 EN R/W-0
11 GP11 EN R/W-0
10 GP10 EN R/W-0
9 GP9 EN R/W-0
8 GP8 EN R/W-0
7 GP7 EN R/W-1
6 GP6 EN R/W-1
5 GP5 EN R/W-1
4 GP4 EN R/W-1
3 GP3 EN R/W-1
2 GP2 EN R/W-0
1 GP1 EN R/W-0
0 GP0 EN R/W-1
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
Figure 6. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000] Figure 7 shows the GPIO direction bits in the GPDIR register. This register determines if a given GPIO pin is an input or an output providing the corresponding GPxEN bit is enabled (set to "1") in the GPEN register. By default, all the GPIO pins are configured as input pins.
31 24 23 Reserved R-0 15 GP15 DIR R/W-0 14 GP14 DIR R/W-0 13 GP13 DIR R/W-0 12 GP12 DIR R/W-0 11 GP11 DIR R/W-0 10 GP10 DIR R/W-0 9 GP9 DIR R/W-0 8 GP8 DIR R/W-0 7 GP7 DIR R/W-0 6 GP6 DIR R/W-0 5 GP5 DIR R/W-0 4 GP4 DIR R/W-0 3 GP3 DIR R/W-0 2 GP2 DIR R/W-0 1 GP1 DIR R/W-0 0 GP0 DIR R/W-0 16
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
Figure 7. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004] For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).
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power-down mode logic
Figure 8 shows the power-down mode logic on the C6414/C6415/C6416.
CLKOUT4 CLKOUT6
Internal Clock Tree Clock Distribution and Dividers PD1
PD2
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Clock PLL
PowerDown Logic
IFR IER PWRD CSR CPU Internal Peripherals
PD3 TMS320C6414/15/16 CLKIN RESET
External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic.
Figure 8. Power-Down Mode Logic triggering, wake-up, and effects The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15-10) of the control status register (CSR). The PWRD field of the CSR is shown in Figure 9 and described in Table 33. When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
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31
16
15 Reserved R/W-0 7
14 Enable or Non-Enabled Interrupt Wake R/W-0
13 Enabled Interrupt Wake R/W-0
12 PD3 R/W-0
11 PD2 R/W-0
10 PD1 R/W-0
9
8
0
Figure 9. PWRD Field of the CSR Register A delay of up to nine cycles may occur after the instruction that sets the PWRD bits in the CSR before the PD mode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in the CSR to account for this delay. If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed first, then the program execution returns to the instruction where PD1 took effect. In the case with an enabled interrupt, the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order for the interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect upon PD1 mode termination by an enabled interrupt. PD2 and PD3 modes can only be aborted by device reset. Table 33 summarizes all the power-down modes. Table 33. Characteristics of the Power-Down Modes
PRWD FIELD (BITS 15-10) 000000 001001 010001 POWER-DOWN MODE No power-down PD1 PD1 WAKE-UP METHOD -- Wake by an enabled interrupt Wake by an enabled or non-enabled interrupt EFFECT ON CHIP'S OPERATION -- CPU halted (except for the interrupt logic) Power-down mode blocks the internal clock inputs at the boundary of the CPU, preventing most of the CPU's logic from switching. During PD1, EDMA transactions can proceed between peripherals and internal memory. Output clock from PLL is halted, stopping the internal clock structure from switching and resulting in the entire chip being halted. All register and internal RAM contents are preserved. All functional I/O "freeze" in the last state when the PLL clock is turned off.
011010
PD2
Wake by a device reset
When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions, peripherals will not operate according to specifications.
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Legend: R/W-x = Read/write reset value NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
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Table 33. Characteristics of the Power-Down Modes
PRWD FIELD (BITS 15-10) POWER-DOWN MODE WAKE-UP METHOD EFFECT ON CHIP'S OPERATION Input clock to the PLL stops generating clocks. All register and internal RAM contents are preserved. All functional I/O "freeze" in the last state when the PLL clock is turned off. Following reset, the PLL needs time to re-lock, just as it does following power-up. Wake-up from PD3 takes longer than wake-up from PD2 because the PLL needs to be re-locked, just as it does following power-up.
011100
PD3
Wake by a device reset
All others Reserved -- -- When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions, peripherals will not operate according to specifications.
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C64x power-down mode with an emulator If user power-down modes are programmed, and an emulator is attached, the modes will be masked to allow the emulator access to the system. This condition prevails until the emulator is reset or the cable is removed from the header. If power measurements are to be performed when in a power-down mode, the emulator cable should be removed. When the DSP is in power-down mode PD2 or PD3, emulation logic will force any emulation execution command (such as Step or Run) to spin in IDLE. For this reason, PC writes (such as loading code) will fail. A DSP reset will be required to get the DSP out of PD2/PD3.
power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time (>1 second) if the other supply is below the proper operating voltage. power-supply design considerations
I/O Supply DVDD Schottky Diode Core Supply C6000 DSP CVDD
VSS
GND
Figure 10. Schottky Diode Diagram Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
power-supply decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the core supply and 30 for the I/O supply. These caps need to be close to the DSP, no more than 1.25 cm maximum distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest available capacitance value. As with the selection of any component, verification of capacitor availability over the product's production lifetime should be considered.
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A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 10).
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
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IEEE 1149.1 JTAG compatibility statement
The TMS320C6414/15/16 DSP requires that both TRST and RESET be asserted upon power up to be properly initialized. While RESET initializes the DSP core, TRST initializes the DSP's emulation logic. Both resets are required for proper operation. While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface and DSP's emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG controller to debug the DSP or exercise the DSP's boundary scan functionality. RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan instructions work correctly independant of current state RESET. For maximum reliability, the TMS320C6414/15/16 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be properly initialized.
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JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan operations. Following the release of RESET, the low-to-high transition of TRST must be "seen" to latch the state of EMU1 and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see the terminal functions section of this data sheet.
EMIF device speed
The rated EMIF speed, referring to both EMIFA and EMIFB, of these devices only applies to the SDRAM interface when in a system that meets the following requirements: - - - - - 1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF up to 1 CE space of buffers connected to EMIF EMIF trace lengths between 1 and 3 inches 166-MHz SDRAM for 133-MHz operation (applies only to EMIFA) 143-MHz SDRAM for 100-MHz operation
Other configurations may be possible, but timing analysis must be done to verify all AC timings are met. Verification of AC timings is mandatory when using configurations other than those specified above. TI recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see the Terminal Functions table for the EMIF output signals).
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bootmode
The C6414/15/16 device resets using the active-low signal RESET. While RESET is low, the device is held in reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and states of device pins during reset. The release of RESET starts the processor running with the prescribed device configuration and boot mode. The C6414/C6415/C6416 has three types of boot modes:
D Host boot
If host boot is selected, upon release of RESET, the CPU is internally "stalled" while the remainder of the device is released. During this period, an external host can initialize the CPU's memory space as necessary through the host interface, including internal configuration registers, such as those that control the EMIF or other peripherals. For the C6414 device, the HPI peripheral is used for host boot. For the C6415/C6416 device, the HPI peripheral is used for host boot if PCI_EN = 0, and the PCI peripheral is used for host boot if PCI_EN = 1. Once the host is finished with all necessary initialization, it must set the DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration logic to bring the CPU out of the "stalled" state. The CPU then begins execution from address 0. The DSPINT condition is not latched by the CPU, because it occurs while the CPU is still internally "stalled". Also, DSPINT brings the CPU out of the "stalled" state only if the host boot process is selected. All memory may be written to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is out of the "stalled" state, the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.
D EMIF boot (using default ROM timings)
Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0 by the EDMA using the default ROM timings, while the CPU is internally "stalled". The data should be stored in the endian format that the system is using. In this case, the EMIF automatically assembles consecutive 8-bit bytes to form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU is released from the "stalled" state and starts running from address 0.
D No boot
With no boot, the CPU begins direct execution from the memory located at address 0. Note: operation is undefined if invalid code is located at address 0.
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absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage ranges: CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 1.8 V DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Input voltage ranges: (except PCI), VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V (PCI), VIP [C6415 and C6416 only] . . . . . . . . . . . . . . . . . . . . . -0.5 V to DVDD + 0.5 V Output voltage ranges: (except PCI), VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V (PCI), VOP [C6415 and C6416 only] . . . . . . . . . . . . . . . . . . . . -0.5 V to DVDD + 0.5 V Operating case temperature ranges, TC: (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C (A version) [A-5E0, A-6E3] . . . . . . . . . . . . . . . . -40_C to105_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65_C to 150_C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
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MIN CVDD CVDD CVDD DVDD VSS VIH VIL VIP VIHP VILP VOS TC Supply voltage, Core (-5E0 device) Supply voltage, Core (A-5E0 device) Supply voltage, Core (-6E3, A-6E3, -7E3 devices) Supply voltage, I/O Supply ground High-level input voltage (except PCI) Low-level input voltage (except PCI) Input voltage (PCI) [C6415 and C6416 only] High-level input voltage (PCI) [C6415 and C6416 only] Low-level input voltage (PCI) [C6415 and C6416 only] Maximum voltage during overshoot/undershoot Operating case temperature Default -0.5 0.5DVDD -0.5 -1.0 0 1.14 1.19 1.36 3.14 0 2
NOM 1.2 1.25 1.4 3.3 0
MAX 1.26 1.31 1.44 3.46 0 0.8 DVDD + 0.5 DVDD + 0.5 0.3DVDD 4.3 90
UNIT V V V V V V V V V V V _C
A version (C6414/15/16GLZA-5E0 and GLZA-6E3 only) -40 105 _C Future variants of the C641x DSPs may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.2 V, 1.25 V, 1.3 V, 1.35 V, 1.4 V with 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Examples of such supplies include the PT4660, PT5500, PT5520, PT6440, and PT6930 series from Power Trends, a subsidiary of Texas Instruments. Not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of C641x devices. The absolute maximum ratings should not be exceeded for more than 30% of the cycle period.
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electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)
PARAMETER VOH VOHP VOL VOLP High-level output voltage (except PCI) High-level output voltage (PCI) [C6415/C6416 only] Low-level output voltage (except PCI) Low-level output voltage (PCI) [C6415/C6416 only] TEST CONDITIONS DVDD = MIN, IOHP = -0.5 mA, DVDD = MIN, IOLP = 1.5 mA, IOH = MAX DVDD = 3.3 V IOL = MAX DVDD = 3.3 V MIN 2.4 0.9DVDD 0.4 0.1DVDD 10 50 -150 100 -100 150 -50 10 -16 -8 -0.5 16 8 1.5 10 900 750 550 125 10 TYP MAX UNIT V V V V uA uA uA
VI = VSS to DVDD no opposing internal resistor II Input current (except PCI) VI = VSS to DVDD opposing internal pullup resistor VI = VSS to DVDD opposing internal pulldown resistor IIP Input leakage current (PCI) [C6415/C6416 only] 0 < VIP < DVDD = 3.3 V EMIF, CLKOUT4, CLKOUT6, EMUx IOH High-level output current Timer, UTOPIA, TDO, GPIO (Excluding GP[15:9, 2, 1]), McBSP PCI/HPI EMIF, CLKOUT4, CLKOUT6, EMUx IOL Low-level output current Timer, UTOPIA, TDO, GPIO (Excluding GP[15:9, 2, 1]), McBSP PCI/HPI IOZ ICDD IDDD Ci Off-state output current Core supply current# I/O supply current# Input capacitance VO = DVDD or 0 V CVDD = 1.4 V, CPU clock = 720 MHz CVDD = 1.4 V, CPU clock = 600 MHz CVDD = 1.2 V, CPU clock = 500 MHz DVDD = 3.3 V, CPU clock = 600 MHz
mA mA mA mA mA mA uA mA mA mA mA pF
Co Output capacitance 10 pF For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs. These rated numbers are from the PCI specification version 2.3. The DC specification and AC specification are defined in Tables 4-3 and 4-4, respectively. # Measured with average activity (50% high/50% low power). The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6414/15/16 Power Consumption Summary application report (literature number SPRA811).
recommended clock and control signal transition behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
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PARAMETER MEASUREMENT INFORMATION
Tester Pin Electronics
Data Sheet Timing Reference Point
42 W
3.5 nH Transmission Line Z0 = 50 W (see note)
Output Under Test
Device Pin (see note)
4.0 pF
1.85 pF
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NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 11. Test Load Circuit for AC Timing Measurements The tester load circuit is for characterization and measurement of AC timing signals. This load does not indicate the maximum load the device is capable of driving.
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels.
Vref = 1.5 V
Figure 12. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH MIN for output clocks, VILP MAX and VIHP MIN for PCI input clocks, and VOLP MAX and VOHP MIN for PCI output clocks.
Vref = VIH MIN (or VOH MIN or VIHP MIN or VOHP MIN) Vref = VIL MAX (or VOL MAX or VILP MAX or VOLP MAX)
Figure 13. Rise and Fall Transition Time Voltage Reference Levels
signal transition rates
All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).
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PARAMETER MEASUREMENT INFORMATION (CONTINUED) timing parameters and board routing analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers may be used to compensate any timing differences. For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see Table 34 and Figure 14). Figure 14 represents a general transfer between the DSP and an external device. The figure also represents board route delays and how they are perceived by the DSP and the external device. Table 34. Board-Level Timings Example (see Figure 14)
NO. 1 2 3 4 5 6 7 8 9 10 11 ECLKOUTx (Output from DSP) 1 ECLKOUTx (Input to External Device) Control Signals (Output from DSP) 3 4 5 Control Signals (Input to External Device) Data Signals (Output from External Device) Data Signals (Input to DSP) Control signals include data for Writes. Data signals are generated during Reads from an external device. 6 7 8 2 DESCRIPTION Clock route delay Minimum DSP hold time Minimum DSP setup time External device hold time requirement External device setup time requirement Control signal route delay External device hold time External device access time DSP hold time requirement DSP setup time requirement Data route delay
10 11
9
Figure 14. Board-Level Input/Output Timings
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INPUT AND OUTPUT CLOCKS timing requirements for CLKIN for -5E0 devices (see Figure 15)
-5E0 A-5E0 NO. PLL MODE x12 MIN 1 2 3 4 5 tc(CLKIN) tw(CLKINH) tw(CLKINL) tt(CLKIN) Cycle time, CLKIN Pulse duration, CLKIN high Pulse duration, CLKIN low Transition time, CLKIN 24 0.4C 0.4C 5 MAX 33.3 PLL MODE x6 MIN 13.3 0.4C 0.4C 5 0.02C MAX 33.3 x1 (BYPASS) MIN 13.3 0.45C 0.45C 1 0.02C MAX 33.3 ns ns ns ns ns UNIT
tJ(CLKIN) Period jitter, CLKIN 0.02C The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet. C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
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timing requirements for CLKIN for -6E3 devices (see Figure 15)
-6E3, A-6E3 NO. 1 2 3 4 tc(CLKIN) tw(CLKINH) tw(CLKINL) tt(CLKIN) Cycle time, CLKIN Pulse duration, CLKIN high Pulse duration, CLKIN low Transition time, CLKIN PLL MODE x12 MIN 20 0.4C 0.4C 5 MAX 33.3 PLL MODE x6 MIN 13.3 0.4C 0.4C 5 0.02C MAX 33.3 x1 (BYPASS) MIN 13.3 0.45C 0.45C 1 0.02C MAX 33.3 ns ns ns ns ns UNIT
5 tJ(CLKIN) Period jitter, CLKIN 0.02C The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet. C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
timing requirements for CLKIN for -7E3 devices (see Figure 15)
-7E3 NO. 1 2 3 4 tc(CLKIN) tw(CLKINH) tw(CLKINL) tt(CLKIN) Cycle time, CLKIN Pulse duration, CLKIN high Pulse duration, CLKIN low Transition time, CLKIN PLL MODE x12 MIN 16.6 0.4C 0.4C 5 MAX 33.3 PLL MODE x6 MIN 13.3 0.4C 0.4C 5 0.02C MAX 33.3 x1 (BYPASS) MIN 13.3 0.45C 0.45C 1 0.02C MAX 33.3 ns ns ns ns ns UNIT
5 tJ(CLKIN) Period jitter, CLKIN 0.02C The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet. C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. 5 2 CLKIN 3 1 4
4
Figure 15. CLKIN Timing
82
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for CLKOUT4 (see Figure 16)
-5E0, A-5E0, -6E3, A-6E3, -7E3 CLKMODE = x1, x6, x12 MIN 1 2 3 4 tJ(CKO4) tw(CKO4H) tw(CKO4L) tt(CKO4) Period jitter, CLKOUT4 Pulse duration, CLKOUT4 high Pulse duration, CLKOUT4 low Transition time, CLKOUT4 0 2P - 0.7 2P - 0.7 MAX 175 2P + 0.7 2P + 0.7 1 ps ns ns ns
NO.
PARAMETER
UNIT
The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. P = 1/CPU clock frequency in nanoseconds (ns) 1 2 CLKOUT4 3 4 4
Figure 16. CLKOUT4 Timing
switching characteristics over recommended operating conditions for CLKOUT6 (see Figure 17)
-5E0, A-5E0, -6E3, A-6E3, -7E3 CLKMODE = x1, x6, x12 MIN 1 2 3 tJ(CKO6) tw(CKO6H) tw(CKO6L) tt(CKO6) Period jitter, CLKOUT6 Pulse duration, CLKOUT6 high Pulse duration, CLKOUT6 low 0 3P - 0.7 3P - 0.7 MAX 175 3P + 0.7 3P + 0.7 1 ps ns ns ns
NO.
PARAMETER
UNIT
4 Transition time, CLKOUT6 The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. P = 1/CPU clock frequency in nanoseconds (ns) 1 2 CLKOUT6 3 4
4
Figure 17. CLKOUT6 Timing
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ADVANCE INFORMATION
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
INPUT AND OUTPUT CLOCKS (CONTINUED) timing requirements for ECLKIN for EMIFA and EMIFB (see Figure 18)
NO. -5E0, A-5E0, -6E3, A-6E3, -7E3 tc(EKI) tw(EKIH) tw(EKIL) tt(EKI) Cycle time, ECLKIN Pulse duration, ECLKIN high Pulse duration, ECLKIN low Transition time, ECLKIN MIN 6# 2.7 2.7 2 MAX 16P ns ns ns ns UNIT
1 2 3 4
ADVANCE INFORMATION
5 tJ(EKI) Period jitter, ECLKIN 0.02E ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted. E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. # Minimum ECLKIN cycle times must be met, even when ECLKIN is generated by an internal clock source. Minimum ECLKIN times are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. On the 7E3 and 6E3 devices, 133-MHz operation is achievable if the requirements of the EMIF Device Speed section are met. On the 5E0 devices, 100-MHz operation is achievable if the requirements of the EMIF Device Speed section are met. 5 2 ECLKIN 3 4 1 4
Figure 18. ECLKIN Timing for EMIFA and EMIFB
switching characteristics over recommended operating conditions for ECLKOUT1 for EMIFA and EMIFB modules||k (see Figure 19)
-5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 1 2 3 4 5 6 tJ(EKO1) tw(EKO1H) tw(EKO1L) tt(EKO1) td(EKIH-EKO1H) td(EKIL-EKO1L) Period jitter, ECLKOUT1 Pulse duration, ECLKOUT1 high Pulse duration, ECLKOUT1 low Transition time, ECLKOUT1 Delay time, ECLKIN high to ECLKOUT1 high Delay time, ECLKIN low to ECLKOUT1 low 1 1 0 EH - 0.7 EL - 0.7 MAX 175h EH + 0.7 EL + 0.7 1 8 8
NO.
PARAMETER
UNIT
ps ns ns ns ns
ns These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted. E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. || The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. kEH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA or EMIFB. hThis cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
INPUT AND OUTPUT CLOCKS (CONTINUED)
ECLKIN 1 5 ECLKOUT1 6 2
3
4
4
Figure 19. ECLKOUT1 Timing for EMIFA and EMIFB Modules
switching characteristics over recommended operating conditions for ECLKOUT2 for the EMIFA and EMIFB modules (see Figure 20)
NO.
PARAMETER
UNIT MAX
MIN 1 2 3 4 5 tJ(EKO2) tw(EKO2H) tw(EKO2L) tt(EKO2) Period jitter, ECLKOUT2 Pulse duration, ECLKOUT2 high Pulse duration, ECLKOUT2 low Transition time, ECLKOUT2 1 0 0.5NE - 0.7 0.5NE - 0.7
175 0.5NE + 0.7 0.5NE + 0.7 1 8
ps ns ns ns ns
6 1 8 ns The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted. E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. N = the EMIF input clock divider; N = 1, 2, or 4. This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
td(EKIH-EKO2H) Delay time, ECLKIN high to ECLKOUT2 high td(EKIH-EKO2L) Delay time, ECLKIN high to ECLKOUT2 low
5 ECLKIN 1
6
3 2 4 4
ECLKOUT2
Figure 20. ECLKOUT2 Timing for the EMIFA and EMIFB Modules
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ADVANCE INFORMATION
-5E0, A-5E0, -6E3, A-6E3, -7E3
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles for EMIFA module (see Figure 21 and Figure 22)
-5E0 -6E3 -7E3 MIN 3 4 6 7 tsu(EDV-AREH) th(AREH-EDV) tsu(ARDY-EKO1H) th(EKO1H-ARDY) Setup time, EDx valid before ARE high Hold time, EDx valid after ARE high Setup time, ARDY valid before ECLKOUTx high Hold time, ARDY valid after ECLKOUTx high 6.5 1 3 1 MAX A-5E0 A-6E3 MIN 6.5 1 3 1.5 MAX ns ns ns
NO.
UNIT
ADVANCE INFORMATION
ns To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is only recognized two cycles before the end of the programmed strobe time and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is recognized low, the end of the strobe time is two cycles after ARDY is recognized high. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)].
switching characteristics over recommended operating conditions for asynchronous memory cycles for EMIFA module# (see Figure 21 and Figure 22)
-5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 1 2 5 8 9 tosu(SELV-AREL) toh(AREH-SELIV) td(EKO1H-AREV) tosu(SELV-AWEL) toh(AWEH-SELIV) td(EKO1H-AWEV) Output setup time, select signals valid to ARE low Output hold time, ARE high to select signals invalid Delay time, ECLKOUTx high to ARE valid Output setup time, select signals valid to AWE low Output hold time, AWE high to select signals invalid RS * E - 1.5 RH * E - 1.9 1 WS * E - 1.7 WH * E - 1.8 7 MAX ns ns ns ns ns
NO.
PARAMETER
UNIT
10 Delay time, ECLKOUTx high to AWE valid 1.3 7.1 ns RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. E = ECLKOUT1 period in ns for EMIFA or EMIFB # Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0]. Select signals EMIFB include: BCEx, BBE[1:0], BEA[20:1], BAOE; and for EMIFB writes, include BED[15:0].
86
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
ASYNCHRONOUS MEMORY TIMING (CONTINUED) timing requirements for asynchronous memory cycles for EMIFB module (see Figure 21 and Figure 22)
-5E0 -6E3 -7E3 MIN 3 4 6 tsu(EDV-AREH) th(AREH-EDV) tsu(ARDY-EKO1H) th(EKO1H-ARDY) Setup time, EDx valid before ARE high Hold time, EDx valid after ARE high Setup time, ARDY valid before ECLKOUTx high 6.2 1 3 MAX A-5E0 A-6E3 MIN 6.2 1 3 MAX ns ns ns
NO.
UNIT
switching characteristics over recommended operating conditions for asynchronous memory cycles for EMIFB module# (see Figure 21 and Figure 22)
-5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 1 2 5 8 9 10 tosu(SELV-AREL) toh(AREH-SELIV) td(EKO1H-AREV) tosu(SELV-AWEL) toh(AWEH-SELIV) td(EKO1H-AWEV) Output setup time, select signals valid to ARE low Output hold time, ARE high to select signals invalid Delay time, ECLKOUTx high to ARE valid Output setup time, select signals valid to AWE low Output hold time, AWE high to select signals invalid Delay time, ECLKOUTx high to AWE valid RS * E - 1.6 RH * E - 1.7 0.8 WS * E - 1.9 WH * E - 1.7 0.9 6.7 6.6 MAX ns ns ns ns ns
NO.
PARAMETER
UNIT
ns RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. E = ECLKOUT1 period in ns for EMIFA or EMIFB # Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0]. Select signals EMIFB include: BCEx, BBE[1:0], BEA[20:1], BAOE; and for EMIFB writes, include BED[15:0].
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ADVANCE INFORMATION
7 Hold time, ARDY valid after ECLKOUTx high 1.2 1.7 ns To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is only recognized two cycles before the end of the programmed strobe time and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is recognized low, the end of the strobe time is two cycles after ARDY is recognized high. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)].
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 ECLKOUTx 1 CEx 1 ABE[7:0] or BBE[1:0] 1 AEA[22:3] or BEA[20:1] Address 3 4 AED[63:0] or BED[15:0] 1 Read Data 5 ARE/SDCAS/SADS/SRE AWE/SDWE/SWE 6 ARDY These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. 7 6 5 2 BE 2 2 2 Strobe = 3 Not Ready Hold = 2
ADVANCE INFORMATION
AOE/SDRAS/SOE
7
Figure 21. Asynchronous Memory Read Timing for EMIFA and EMIFB
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 ECLKOUTx 8 CEx 8 ABE[7:0] or BBE[1:0] 8 AEA[22:3] or BEA[20:1] 8 AED[63:0] or BED[15:0] AOE/SDRAS/SOE Write Data Address 9 BE 9 9 9 Strobe = 3 Not Ready Hold = 2
10 AWE/SDWE/SWE 7 6 ARDY 6 7
10
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses.
Figure 22. Asynchronous Memory Write Timing for EMIFA and EMIFB
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ADVANCE INFORMATION
ARE/SDCAS/SADS/SRE
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING timing requirements for programmable synchronous interface cycles for EMIFA module (see Figure 23)
-5E0 A-5E0 MIN 6 7 tsu(EDV-EKOxH) th(EKOxH-EDV) Setup time, read EDx valid before ECLKOUTx high Hold time, read EDx valid after ECLKOUTx high 3.1 1.5 MAX -6E3 A-6E3 -7E3 MIN 2 1.5 MAX ns
NO.
UNIT
ns These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].
ADVANCE INFORMATION
switching characteristics over recommended operating conditions for synchronous interface cycles for EMIFA module (see Figure 23-Figure 25)
-5E0 A-5E0 MIN 1 2 3 4 5 8 9 10 11 12 td(EKOxH-CEV) td(EKOxH-BEV) td(EKOxH-BEIV) td(EKOxH-EAV) td(EKOxH-EAIV) td(EKOxH-ADSV) td(EKOxH-OEV) td(EKOxH-EDV) td(EKOxH-EDIV) td(EKOxH-WEV) Delay time, ECLKOUTx high to CEx valid Delay time, ECLKOUTx high to BEx valid Delay time, ECLKOUTx high to BEx invalid Delay time, ECLKOUTx high to EAx valid Delay time, ECLKOUTx high to EAx invalid Delay time, ECLKOUTx high to SADS/SRE valid Delay time, ECLKOUTx high to, SOE valid Delay time, ECLKOUTx high to EDx valid Delay time, ECLKOUTx high to EDx invalid Delay time, ECLKOUTx high to SWE valid 1.3 1.3 6.4 1.3 1.3 1.3 6.4 6.4 6.4 1.3 6.4 1.3 MAX 6.4 6.4
programmable
-6E3 A-6E3 -7E3 MIN 1.3 1.3 4.9 1.3 1.3 1.3 1.3 1.3 4.9 4.9 4.9 4.9 MAX 4.9 4.9 ns ns ns ns ns ns ns ns ns
NO.
PARAMETER
UNIT
ns These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)]. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). - Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
90
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED) timing requirements for programmable synchronous interface cycles for EMIFB module (see Figure 23)
-5E0 A-5E0 MIN 6 7 tsu(EDV-EKOxH) th(EKOxH-EDV) Setup time, read EDx valid before ECLKOUTx high Hold time, read EDx valid after ECLKOUTx high 3.1 1.5 MAX -6E3 A-6E3 -7E3 MIN 3.1 1.5 MAX ns
NO.
UNIT
ns These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].
NO.
PARAMETER
-5E0 A-5E0 MIN MAX 6.4 6.4 1.3 6.4 1.3 1.3 1.3 1.3 1.3 6.4 6.4 6.4 6.4
-6E3 A-6E3 -7E3 MIN 1.3 1.3 6.4 1.3 1.3 1.3 1.3 1.3 6.4 6.4 6.4 6.4 MAX 6.4 6.4
UNIT
1 2 3 4 5 8 9 10 11 12
td(EKOxH-CEV) td(EKOxH-BEV) td(EKOxH-BEIV) td(EKOxH-EAV) td(EKOxH-EAIV) td(EKOxH-ADSV) td(EKOxH-OEV) td(EKOxH-EDV) td(EKOxH-EDIV) td(EKOxH-WEV)
Delay time, ECLKOUTx high to CEx valid Delay time, ECLKOUTx high to BEx valid Delay time, ECLKOUTx high to BEx invalid Delay time, ECLKOUTx high to EAx valid Delay time, ECLKOUTx high to EAx invalid Delay time, ECLKOUTx high to SADS/SRE valid Delay time, ECLKOUTx high to, SOE valid Delay time, ECLKOUTx high to EDx valid Delay time, ECLKOUTx high to EDx invalid Delay time, ECLKOUTx high to SWE valid
1.3
ns ns ns ns ns ns ns ns ns
ns These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)]. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). - Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
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ADVANCE INFORMATION
switching characteristics over recommended operating conditions for synchronous interface cycles for EMIFB module (see Figure 23-Figure 25)
programmable
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)
READ latency = 2 ECLKOUTx 1 CEx ABE[7:0] or BBE[1:0] AEA[22:3] or BEA[20:1] 2 BE1 4 EA1 EA2 6 AED[63:0] or BED[15:0] 8 ARE/SDCAS/SADS/SRE Q1 EA3 EA4 7 Q2 Q3 Q4 8 3 BE2 BE3 BE4 5 1
ADVANCE INFORMATION
9 AOE/SDRAS/SOE AWE/SDWE/SWE
9
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)]. The read latency and the length of CEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIFx CE Space Secondary Control register (CExSEC). In this figure, SYNCRL = 2 and CEEXT = 0. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). - Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during programmable synchronous interface accesses.
Figure 23. Programmable Synchronous Interface Read Timing for EMIFA and EMIFB (With Read Latency = 2)
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SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)
ECLKOUTx 1 CEx 2 BE1 4 EA1 10 AED[63:0] or BED[15:0] ARE/SDCAS/SADS/SRE AOE/SDRAS/SOE 12 AWE/SDWE/SWE 12 10 Q1 8 3 BE2 BE3 BE4 5 EA2 EA3 EA4 11 Q2 Q3 Q4 8 1
ABE[7:0] or BBE[1:0]
AEA[22:3] or BEA[20:1]
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)]. The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFx CE Space Secondary Control register (CExSEC). In this figure, SYNCWL = 0 and CEEXT = 0. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). - Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during programmable synchronous interface accesses.
Figure 24. Programmable Synchronous Interface Write Timing for EMIFA and EMIFB (With Write Latency = 0)
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PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)
Write Latency = 1 ECLKOUTx 1 CEx ABE[7:0] or BBE[1:0] AEA[22:3] or BEA[20:1] AED[63:0] or BED[15:0] 8 ARE/SDCAS/SADS/SRE AOE/SDRAS/SOE 12 AWE/SDWE/SWE 12 2 BE1 4 EA1 10 3 BE2 EA2 10 Q1 BE3 EA3 Q2 BE4 5 EA4 11 Q3 Q4 8 1
ADVANCE INFORMATION
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)]. The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFx CE Space Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). - Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during programmable synchronous interface accesses.
Figure 25. Programmable Synchronous Interface Write Timing for EMIFA and EMIFB (With Write Latency = 1)
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles for EMIFA module (see Figure 26)
-5E0 A-5E0 MIN 6 7 tsu(EDV-EKO1H) th(EKO1H-EDV) Setup time, read EDx valid before ECLKOUTx high Hold time, read EDx valid after ECLKOUTx high 2.1 2.5 MAX -6E3 A-6E3 -7E3 MIN 0.6 1.8 MAX ns
NO.
UNIT
ns These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
switching characteristics over recommended operating conditions for synchronous DRAM cycles for EMIFA module (see Figure 26-Figure 33)
-5E0 A-5E0 MIN 1 2 3 4 5 8 9 10 11 12 13 14 td(EKO1H-CEV) td(EKO1H-BEV) td(EKO1H-BEIV) td(EKO1H-EAV) td(EKO1H-EAIV) td(EKO1H-CASV) td(EKO1H-EDV) td(EKO1H-EDIV) td(EKO1H-WEV) td(EKO1H-RAS) td(EKO1H-ACKEV) Delay time, ECLKOUTx high to CEx valid Delay time, ECLKOUTx high to BEx valid Delay time, ECLKOUTx high to BEx invalid Delay time, ECLKOUTx high to EAx valid Delay time, ECLKOUTx high to EAx invalid Delay time, ECLKOUTx high to SDCAS valid Delay time, ECLKOUTx high to EDx valid Delay time, ECLKOUTx high to EDx invalid Delay time, ECLKOUTx high to SDWE valid Delay time, ECLKOUTx high to SDRAS valid Delay time, ECLKOUTx high to ASDCKE valid (EMIFA only) 1.3 1.3 1.3 1.3 6.4 6.4 6.4 1.3 1.3 6.4 6.4 1.3 1.3 1.3 1.3 4.9 4.9 4.9 1.3 6.4 1.3 1.3 4.9 4.9 1.3 MAX 6.4 6.4 1.3 4.9 -6E3 A-6E3 -7E3 MIN 1.3 MAX 4.9 4.9 ns ns ns ns ns ns ns ns ns ns ns
NO.
PARAMETER
UNIT
td(EKO1H-PDTV) Delay time, ECLKOUTx high to PDT valid 1.3 6.4 1.3 4.9 ns These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
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SYNCHRONOUS DRAM TIMING (CONTINUED) timing requirements for synchronous DRAM cycles for EMIFB module (see Figure 26)
-5E0 A-5E0 MIN 6 7 tsu(EDV-EKO1H) th(EKO1H-EDV) Setup time, read EDx valid before ECLKOUTx high Hold time, read EDx valid after ECLKOUTx high 2.1 2.5 MAX -6E3 A-6E3 -7E3 MIN 2.1 2.5 MAX ns
NO.
UNIT
ns These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
switching characteristics over recommended operating conditions for synchronous DRAM cycles for EMIFB module (see Figure 26-Figure 33)
ADVANCE INFORMATION
NO.
PARAMETER
-5E0 A-5E0 MIN MAX 6.4 6.4 1.3 6.4 1.3 1.3 1.3 1.3 1.3 1.3 6.4 6.4 6.4 6.4 6.4
-6E3 A-6E3 -7E3 MIN 1.3 1.3 6.4 1.3 1.3 1.3 1.3 1.3 1.3 6.4 6.4 6.4 6.4 6.4 MAX 6.4 6.4
UNIT
1 2 3 4 5 8 9 10 11 12 13 14
td(EKO1H-CEV) td(EKO1H-BEV) td(EKO1H-BEIV) td(EKO1H-EAV) td(EKO1H-EAIV) td(EKO1H-CASV) td(EKO1H-EDV) td(EKO1H-EDIV) td(EKO1H-WEV) td(EKO1H-RAS) td(EKO1H-ACKEV)
Delay time, ECLKOUTx high to CEx valid Delay time, ECLKOUTx high to BEx valid Delay time, ECLKOUTx high to BEx invalid Delay time, ECLKOUTx high to EAx valid Delay time, ECLKOUTx high to EAx invalid Delay time, ECLKOUTx high to SDCAS valid Delay time, ECLKOUTx high to EDx valid Delay time, ECLKOUTx high to EDx invalid Delay time, ECLKOUTx high to SDWE valid Delay time, ECLKOUTx high to SDRAS valid Delay time, ECLKOUTx high to ASDCKE valid (EMIFA only)
1.3
ns ns ns ns ns ns ns ns ns ns ns
td(EKO1H-PDTV) Delay time, ECLKOUTx high to PDT valid 1.3 6.4 1.3 6.4 ns These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ ECLKOUTx 1 CEx ABE[7:0] or BBE[1:0] 4 Bank 4 Column 4 AEA13 or BEA11 AED[63:0] or BED[15:0] AOE/SDRAS/SOE 8 ARE/SDCAS/SADS/SRE AWE/SDWE/SWE 14 PDT These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For PDT read, data is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data phase of a read transaction. The latency of the PDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11, respectively. PDTRL equals 00 (zero latency) in Figure 26. 14 8 D1 D3 D4 2 BE1 5 3 BE2 BE3 BE4 1
AEA[22:14] or BEA[20:12] AEA[12:3] or BEA[10:1]
5
5 6
Figure 26. SDRAM Read Command (CAS Latency 3) for EMIFA and EMIFB
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7 D2
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
WRITE ECLKOUTx 1 CEx 2 ABE[7:0] or BBE[1:0] 4 AEA[22:14] or BEA[20:12] 4 AEA[12:3] or BEA[10:1] 4 AEA13 or BEA11 Column 5 Bank 5 BE1 5 4 BE2 BE3 BE4 3 2
ADVANCE INFORMATION
9 AED[63:0] or BED[15:0] AOE/SDRAS/SOE 8 ARE/SDCAS/SADS/SRE 11 AWE/SDWE/SWE 14 PDT D1
9 D2 D3 D4
10
8
11
14
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data phase of a write transaction. The latency of the PDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00, 01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 27.
Figure 27. SDRAM Write Command for EMIFA and EMIFB
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SYNCHRONOUS DRAM TIMING (CONTINUED)
ACTV ECLKOUTx 1 CEx ABE[7:0] or BBE[1:0] 4 Bank Activate 4 Row Address 4 Row Address 5 1
AEA[22:14] or BEA[20:12] AEA[12:3] or BEA[10:1]
5
5
AEA13 or BEA11 AED[63:0] or BED[15:0]
12 AOE/SDRAS/SOE ARE/SDCAS/SADS/SRE AWE/SDWE/SWE
12
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.
Figure 28. SDRAM ACTV Command for EMIFA and EMFB
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
DCAB ECLKOUTx 1 CEx ABE[7:0] or BBE[1:0] AEA[22:14, 12:3] or BEA[20:12, 10:1] AEA13 or BEA11 AED[63:0] or BED[15:0] 12 AOE/SDRAS/SOE 12 1
4
5
ADVANCE INFORMATION
ARE/SDCAS/SADS/SRE 11 AWE/SDWE/SWE These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 11
Figure 29. SDRAM DCAB Command for EMIFA and EMIFB
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SYNCHRONOUS DRAM TIMING (CONTINUED)
DEAC ECLKOUTx 1 CEx ABE[7:0] or BBE[1:0] 4 AEA[22:14] or BEA[20:12] AEA[12:3] or BEA[10:1] 4 AEA13 or BEA11 AED[63:0] or BED[15:0] AOE/SDRAS/SOE ARE/SDCAS/SADS/SRE 11 AWE/SDWE/SWE These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 11 5 Bank 5 1
Figure 30. SDRAM DEAC Command for EMIFA and EMIFB
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ADVANCE INFORMATION
12
12
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
REFR ECLKOUTx 1 CEx ABE[7:0] or BBE[1:0] AEA[22:14, 12:3] or BEA[20:12, 10:1] AEA13 or BEA11 AED[63:0] or BED[15:0] 12 12 AOE/SDRAS/SOE 8 ARE/SDCAS/SADS/SRE AWE/SDWE/SWE These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 8 1
ADVANCE INFORMATION
Figure 31. SDRAM REFR Command for EMIFA and EMIFB
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SYNCHRONOUS DRAM TIMING (CONTINUED)
MRS ECLKOUTx 1 CEx ABE[7:0] or BBE[1:0] 4 MRS value 5 1
AEA[22:3] or BEA[20:1] AED[63:0] or BED[15:0]
12 AOE/SDRAS/SOE 8 ARE/SDCAS/SADS/SRE 11 AWE/SDWE/SWE
12
8
11
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.
Figure 32. SDRAM MRS Command for EMIFA and EMIFB
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
TRAS cycles Self Refresh AECLKOUTx ACEx ABE[7:0] AEA[22:14, 12:3] AEA13 AED[63:0] AAOE/ASDRAS/ASOE End Self-Refresh
ADVANCE INFORMATION
AARE/ASDCAS/ASADS/ ASRE AAWE/ASDWE/ASWE 13 ASDCKE These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. 13
Figure 33. SDRAM Self-Refresh Timing for EMIFA Only
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HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles for EMIFA and EMIFB modules (see Figure 34)
NO. -5E0 A-5E0 MIN toh(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. 3 E MAX -6E3 A-6E3 -7E3 MIN E MAX ns UNIT
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles for EMIFA and EMIFB modules (see Figure 34)
NO. PARAMETER -5E0 A-5E0 MIN 1 2 4 5 6 td(HOLDL-EMHZ) td(EMHZ-HOLDAL) td(HOLDH-EMLZ) td(EMLZ-HOLDAH) td(HOLDL-EKOHZ) td(HOLDH-EKOLZ) Delay time, HOLD low to EMIF Bus high impedance Delay time, EMIF Bus high impedance to HOLDA low Delay time, HOLD high to EMIF Bus low impedance Delay time, EMIF Bus low impedance to HOLDA high Delay time, HOLD low to ECLKOUTx high impedance 2E 0 2E 0 2E MAX 2E 7E 2E -6E3 A-6E3 -7E3 MIN 2E 0 2E 0 2E MAX 2E 7E 2E UNIT
ns ns ns ns ns
7 Delay time, HOLD high to ECLKOUTx low impedance 2E 7E 2E 7E ns E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT. For EMIFB, EMIF Bus consists of: BCE[3:0], BBE[1:0], BED[15:0], BEA[20:1], BARE/BSDCAS/BSADS/BSRE, BAOE/BSDRAS/BSOE, and BAWE/BSDWE/BSWE, BSOE3, and BPDT. The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0, ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 34. All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. DSP Owns Bus External Requestor Owns Bus 3 HOLD 2 HOLDA EMIF Bus ECLKOUTx (EKxHZ = 0) ECLKOUTx (EKxHZ = 1) 6 7 1 C64x 4 C64x 5 DSP Owns Bus
For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT. For EMIFB, EMIF Bus consists of: BCE[3:0], BBE[1:0], BED[15:0], BEA[20:1], BARE/BSDCAS/BSADS/BSRE, BAOE/BSDRAS/BSOE, and BAWE/BSDWE/BSWE, BSOE3, and BPDT. The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0, ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 34.
Figure 34. HOLD/HOLDA Timing for EMIFA and EMIFB
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BUSREQ TIMING switching characteristics over recommended operating conditions for the BUSREQ cycles for EMIFA and EMIFB modules (see Figure 35)
-5E0 A-5E0 MIN 1 2 td(AEKO1H-ABUSRV) td(BEKO1H-BBUSRV) Delay time, AECLKOUTx high to ABUSREQ valid Delay time, BECLKOUTx high to BBUSREQ valid 0.6 0.5 MAX 7.1 6.9 -6E3 A-6E3 -7E3 MIN 1 0.9 MAX 5.5 5.5 ns ns
NO.
PARAMETER
UNIT
ECLKOUTx
1
1
ADVANCE INFORMATION
ABUSREQ 2 BBUSREQ 2
Figure 35. BUSREQ Timing for EMIFA and EMIFB
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RESET TIMING timing requirements for reset (see Figure 36)
NO. -5E0, A-5E0, -6E3, A-6E3, -7E3 MIN Width of the RESET pulse (PLL stable) 1 16 17 tw(RST) tsu(boot) th(boot) Width of the RESET pulse (PLL needs to sync up) Setup time, boot configuration bits valid before RESET high Hold time, boot configuration bits valid after RESET high 10P 250 4P 4P MAX ns s ns UNIT
ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x6, x12 when CLKIN and PLL are stable. This parameter applies to CLKMODE x6, x12 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 s to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times. EMIFB address pins BEA[20:13, 11, 7] are the boot configuration pins during device reset.
NO. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 td(RSTL-ECKI) td(RSTH-ECKI) td(RSTL-ECKO1HZ) td(RSTH-ECKO1V) td(RSTL-EMIFZHZ) td(RSTH-EMIFZV) td(RSTL-EMIFHIV) td(RSTH-EMIFHV) td(RSTL-EMIFLIV) td(RSTH-EMIFLV) td(RSTL-LOWIV) td(RSTH-LOWV) td(RSTL-ZHZ) td(RSTH-ZV)
PARAMETER Delay time, RESET low to ECLKIN synchronized internally Delay time, RESET high to ECLKIN synchronized internally Delay time, RESET low to ECLKOUT1 high impedance Delay time, RESET high to ECLKOUT1 valid Delay time, RESET low to EMIF Z high impedance Delay time, RESET high to EMIF Z valid Delay time, RESET low to EMIF high group invalid Delay time, RESET high to EMIF high group valid Delay time, RESET low to EMIF low group invalid Delay time, RESET high to EMIF low group valid Delay time, RESET low to low group invalid Delay time, RESET high to low group valid Delay time, RESET low to Z group high impedance Delay time, RESET high to Z group valid
-5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 2E 2E 2E 8P + 20E 2E 16E 2E 8P + 20E 2E 8P + 20E 0 11P 0 2P 8P 3P + 4E 8P + 20E MAX 3P + 20E 8P + 20E
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns
18 td(PCLK-RSTH) Delay time, PCLK active to RESET high|| 32N ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. # E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. || N = the PCI input clock (PCLK) period in ns. When PCI is enabled (PCI_EN = 1), this parameter must be met. kEMIF Z group consists of: AEA[22:3], BEA[20:1], AED[63:0], BED[15:0], CE[3:0], ABE[7:0], BBE[1:0], ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE, SOE3, ASDCKE, and PDT. EMIF high group consists of: AHOLDA and BHOLDA (when the corresponding HOLD input is high) EMIF low group consists of: ABUSREQ and BBUSREQ; AHOLDA and BHOLDA (when the corresponding HOLD input is low) Low group consists of: XSP_CS, CLKX2/XSP_CLK, and DX2/XSP_DO; all of which apply only when PCI EEPROM (BEA13) is enabled (with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the CLKX2/XSP_CLK and DX2/XSP_DO pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations section of this data sheet. Z group consists of: HD[31:0]/AD[31:0], CLKX0, CLKX1/URADDR4, CLKX2/XSP_CLK, FSX0, FSX1/UXADDR3, FSX2, DX0, DX1/UXADDR4, DX2/XSP_DO, CLKR0, CLKR1/URADDR2, CLKR2, FSR0, FSR1/UXADDR2, FSR2, TOUT0, TOUT1, TOUT2, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP13/PINTA, GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP, HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME, UXDATA[7:0], UXSOC, UXCLAV, and URCLAV.
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switching characteristics over recommended operating conditions during reset#k (see Figure 36)
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
RESET TIMING (CONTINUED)
CLKOUT4 CLKOUT6 1 RESET 18 PCLK 2 ECLKIN 4 ECLKOUT1 ECLKOUT2 6 EMIF Z Group 8 EMIF High Group 10 EMIF Low Group 12 Low Group 14 Z Group Boot and Device Configuration Inputs 16 13 11 9 7 5 3
ADVANCE INFORMATION
15 17
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., ECLKIN, ECLKOUT1, and ECLKOUT2]. EMIF Z group consists of: AEA[22:3], BEA[20:1], AED[63:0], BED[15:0], CE[3:0], ABE[7:0], BBE[1:0], ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE, SOE3, ASDCKE, and PDT. EMIF high group consists of: AHOLDA and BHOLDA (when the corresponding HOLD input is high) EMIF low group consists of: ABUSREQ and BBUSREQ; AHOLDA and BHOLDA (when the corresponding HOLD input is low) Low group consists of: XSP_CS, CLKX2/XSP_CLK, and DX2/XSP_DO; all of which apply only when PCI EEPROM (BEA13) is enabled (with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the CLKX2/XSP_CLK and DX2/XSP_DO pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations section of this data sheet. Z group consists of: HD[31:0]/AD[31:0], CLKX0, CLKX1/URADDR4, CLKX2/XSP_CLK, FSX0, FSX1/UXADDR3, FSX2, DX0, DX1/UXADDR4, DX2/XSP_DO, CLKR0, CLKR1/URADDR2, CLKR2, FSR0, FSR1/UXADDR2, FSR2, TOUT0, TOUT1, TOUT2, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP13/PINTA, GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP, HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME, UXDATA[7:0], UXSOC, UXCLAV, and URCLAV. If BEA[20:13, 11, 7] and HD5/AD5 pins are actively driven, care must be taken to ensure no timing contention between parameters 6, 7, 14, 15, 16, and 17. Boot and Device Configurations Inputs (during reset) include: EMIFB address pins BEA[20:13, 11, 7] and HD5/AD5. The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation. The MCBSP2_EN pin must be driven valid at all times and the user can switch values throughout device operation.
Figure 36. Reset Timing
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EXTERNAL INTERRUPT TIMING timing requirements for external interrupts (see Figure 37)
NO. -5E0, A-5E0, -6E3, A-6E3, -7E3 MIN Width of the NMI interrupt pulse low 1 2 tw(ILOW) tw(IHIGH) Width of the EXT_INT interrupt pulse low Width of the NMI interrupt pulse high Width of the EXT_INT interrupt pulse high P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. 2 4P 8P 4P 8P MAX ns ns ns ns UNIT
1 EXT_INTx, NMI
Figure 37. External/NMI Interrupt Timing
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HOST-PORT INTERFACE (HPI) TIMING timing requirements for host-port interface cycles (see Figure 38 through Figure 45)
NO. -5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 1 2 3 4 10 11 12 13 tsu(SELV-HSTBL) th(HSTBL-SELV) tw(HSTBL) tw(HSTBH) tsu(SELV-HASL) th(HASL-SELV) tsu(HDV-HSTBH) th(HSTBH-HDV) th(HRDYL-HSTBL) tsu(HASL-HSTBL) th(HSTBL-HASL) Setup time, select signals valid before HSTROBE low Hold time, select signals valid after HSTROBE low Pulse duration, HSTROBE low Pulse duration, HSTROBE high between consecutive accesses Setup time, select signals valid before HAS low Hold time, select signals valid after HAS low Setup time, host data valid before HSTROBE high Hold time, host data valid after HSTROBE high Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. Setup time, HAS low before HSTROBE low Hold time, HAS low after HSTROBE low 5 2.4 4P 4P 5 2 5 2.8 2 2 2.1 MAX ns ns ns ns ns ns ns ns ns ns ns UNIT
ADVANCE INFORMATION
14 18 19
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL. Select the parameter value of 4P or 12.5 ns, whichever is greater.
switching characteristics over recommended operating conditions during host-port interface cycles (see Figure 38 through Figure 45)
NO. PARAMETER MIN 6 7 8 9 15 td(HSTBL-HRDYH) td(HSTBL-HDLZ) td(HDV-HRDYL) toh(HSTBH-HDV) td(HSTBH-HDHZ) Delay time, HSTROBE low to HRDY high# Delay time, HSTROBE low to HD low impedance for an HPI read Delay time, HD valid to HRDY low Output hold time, HD valid after HSTROBE high Delay time, HSTROBE high to HD high impedance 1.3 2 -3 1.5 12 -5E0 -6E3 -7E3 MAX 4P + 8 MIN 1.3 2 -3 1.5 12 A-5E0 A-6E3 MAX 4P + 9 ns ns ns ns ns UNIT
16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid (HPI16 only) 4P + 8 4P + 8 ns HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. # This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16) on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is full.
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HOST-PORT INTERFACE (HPI) TIMING (CONTINUED)
HAS 1 HCNTL[1:0] 1 HR/W 1 HHWIL HSTROBE HCS 7 HD[15:0] (output) 6 1st half-word 8 2nd half-word 15 9 16 15 9 3 4 3 2 1 2 2 1 2 1 2 2
HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 38. HPI16 Read Timing (HAS Not Used, Tied High)
HAS 10 HCNTL[1:0] 11 10 HR/W 11 10 HHWIL HSTROBE HCS 7 HD[15:0] (output) 6 1st half-word 8 2nd half-word 18 15 9 16 9 3 4 18 15 10 11 10 11 19 11 10 19 11
HRDY For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 39. HPI16 Read Timing (HAS Used)
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HOST-PORT INTERFACE (HPI) TIMING (CONTINUED)
HAS 1 2 HCNTL[1:0] 1 HR/W 1 HHWIL 3 4 HSTROBE HCS 12 HD[15:0] (input) 13 2nd half-word 14 12 13 3 2 1 2 2 1 2
1 2
ADVANCE INFORMATION
1st half-word 6
HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 40. HPI16 Write Timing (HAS Not Used, Tied High)
19 HAS 10 HCNTL[1:0] 11 10 HR/W 11 10 HHWIL 3 4 HSTROBE HCS HD[15:0] (input) 1st half-word 6 HRDY 14 18 12 10 10 11 10
19 11
11
11
18 13 2nd half-word 12 13
For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 41. HPI16 Write Timing (HAS Used)
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HOST-PORT INTERFACE (HPI) TIMING (CONTINUED)
HAS 1 HCNTL[1:0] 1 HR/W HSTROBE HCS 7 HD[31:0] (output) 6 HRDY 8 9 15 3 2 2
Figure 42. HPI32 Read Timing (HAS Not Used, Tied High)
19 HAS 11 10 HCNTL[1:0] 11 10 HR/W 18 HSTROBE HCS 7 HD[31:0] (output) 6 HRDY For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 8 9 15 3
Figure 43. HPI32 Read Timing (HAS Used)
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HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
HOST-PORT INTERFACE (HPI) TIMING (CONTINUED)
HAS 1 HCNTL[1:0] 1 HR/W 3 HSTROBE HCS 12 HD[31:0] (input) 6 14 13 2 2
ADVANCE INFORMATION
HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 44. HPI32 Write Timing (HAS Not Used, Tied High)
19 HAS 11 10 HCNTL[1:0] 11 10 HR/W 3 18 HSTROBE HCS 12 HD[31:0] (input) 6 HRDY For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 14 13
Figure 45. HPI32 Write Timing (HAS Used)
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PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415 AND C6416 ONLY] timing requirements for PCLK (see Figure 46)
NO. -5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 1 2 3 4 tc(PCLK) tw(PCLKH) tw(PCLKL) tsr(PCLK) Cycle time, PCLK Pulse duration, PCLK high Pulse duration, PCLK low v/t slew rate, PCLK 30 (or 8P) 11 11 1 4 MAX ns ns ns V/ns UNIT
For 3.3-V operation, the reference points for the rise and fall transitions are measured at VILP MAX and VIHP MIN. P = 1/CPU clock frequency in ns. For example when running parts at 600 MHz, use P = 1.67 ns. Select the parameter value of 30 ns or 8P, whichever is greater.
2 PCLK 3
4
4
Figure 46. PCLK Timing
timing requirements for PCI reset (see Figure 47)
NO. -5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 1 2 tw(PRST) tsu(PCLKA-PRSTH) Pulse duration, PRST Setup time, PCLK active before PRST high PCLK 1 PRST 2 1 100 MAX ms s UNIT
Figure 47. PCI Reset (PRST) Timing
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1
0.4 DVDD V MIN Peak to Peak for 3.3V signaling
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415 AND C6416 ONLY] (CONTINUED) timing requirements for PCI inputs (see Figure 48)
NO. -5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 5 6 tsu(IV-PCLKH) th(IV-PCLKH) Setup time, input valid before PCLK high Hold time, input valid after PCLK high 7 0 MAX ns ns UNIT
switching characteristics over recommended operating conditions for PCI outputs (see Figure 48)
NO. PARAMETER -5E0, A-5E0, -6E3, A-6E3, -7E3 MIN MAX 11 2 2 28 ns ns ns ns UNIT
ADVANCE INFORMATION
1 2 3 4
td(PCLKH-OV) td(PCLKH-OIV) td(PCLKH-OLZ) td(PCLKH-OHZ)
Delay time, PCLK high to output valid Delay time, PCLK high to output invalid Delay time, PCLK high to output low impedance Delay time, PCLK high to output high impedance PCLK 1 2 PCI Output 3 4 PCI Input 5 6 Valid Valid
Figure 48. PCI Input/Output Timing
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timing requirements for serial EEPROM interface (see Figure 49)
NO. -5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 8 9 tsu(DIV-CLKH) th(CLKH-DIV) Setup time, XSP_DI valid before XSP_CLK high Hold time, XSP_DI valid after XSP_CLK high 50 0 MAX ns ns UNIT
switching characteristics over recommended operating conditions for serial EEPROM interface (see Figure 49)
-5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 1 2 3 4 5 6 tw(CSL) td(CLKL-CSL) td(CSH-CLKH) tw(CLKH) tw(CLKL) tosu(DOV-CLKH) Pulse duration, XSP_CS low Delay time, XSP_CLK low to XSP_CS low Delay time, XSP_CS high to XSP_CLK high Pulse duration, XSP_CLK high Pulse duration, XSP_CLK low Output setup time, XSP_DO valid after XSP_CLK high TYP 4092P 0 2046P 2046P 2046P 2046P 2046P MAX ns ns ns ns ns ns ns
NO.
PARAMETER
UNIT
7 toh(CLKH-DOV) Output hold time, XSP_DO valid after XSP_CLK high P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. 2
1 XSP_CS 3 XSP_CLK 6 XSP_DO 8 XSP_DI 9 7 4 5
Figure 49. PCI Serial EEPROM Interface Timing
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MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING timing requirements for McBSP (see Figure 50)
-5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 2 3 5 6 7 tc(CKRX) tw(CKRX) tsu(FRH-CKRL) th(CKRL-FRH) tsu(DRV-CKRL) th(CKRL-DRV) tsu(FXH-CKXL) th(CKXL-FXH) Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low Setup time, external FSR high before CLKR low Hold time, external FSR high after CLKR low Setup time, DR valid before CLKR low Hold time, DR valid after CLKR low Setup time, external FSX high before CLKX low Hold time, external FSX high after CLKX low CLKR/X ext CLKR/X ext CLKR int CLKR ext CLKR int CLKR ext CLKR int CLKR ext CLKR int 8 10 11 CLKR ext CLKX int CLKX ext CLKX int CLKX ext 4P or 6.67 0.5tc(CKRX) - 1# 9 1.3 6 3 8 0.9 3 3.1 9 1.3 6 3 ns ns ns ns ns ns MAX ns ns
NO.
UNIT
ADVANCE INFORMATION
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. Use whichever value is greater. # This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
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SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP (see Figure 50)
-5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 1 2 3 4 9 12 13 td(CKSH-CKRXH) tc(CKRX) tw(CKRX) td(CKRH-FRV) td(CKXH-FXV) tdis(CKXH-DXHZ) td(CKXH-DXV) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low Delay time, CLKR high to internal FSR valid Delay time, CLKX high to internal FSX valid Disable time, DX high impedance following last data bit from CLKX high Delay time, CLKX high to DX valid Delay time, FSX high to DX valid 14 td(FXH-DXV) ONLY applies when in data delay 0 (XDATDLY = 00b) mode CLKR/X int CLKR/X int CLKR int CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext FSX int FSX ext 1.4 4P or 6.67# C - 1|| -2.1 -1.7 1.7 -3.9 -2.1 -3.9 + D1k -2.1 + D1k -2.3 1.9 MAX 10 ns ns C + 1|| 3 3 9 4 4 + D2k 9 + D2k 5.6 ns 9 ns 9 ns ns ns ns
NO.
PARAMETER
UNIT
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum delay times also represent minimum output hold times. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. # Use whichever value is greater. || C = H or L S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see footnote above). kExtra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 4P, D2 = 8P
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
CLKS 1 3 3 CLKR 4 FSR (int) 5 FSR (ext) 7 DR 2 3 CLKX 3 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) (n-3) Bit(n-1) 8 (n-2) (n-3) 6 4 2
ADVANCE INFORMATION
Figure 50. McBSP Timing
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 51)
NO. -5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 1 2 tsu(FRH-CKSH) th(CKSH-FRH) Setup time, FSR high before CLKS high Hold time, FSR high after CLKS high 4 4 MAX ns ns UNIT
CLKS 1 FSR external CLKR/X (no need to resync) CLKR/X (needs resync) 2
Figure 51. FSR Timing When GSYNC = 1
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (see Figure 52)
-5E0, A-5E0, -6E3, A-6E3, -7E3 MASTER MIN 4 5 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low Hold time, DR valid after CLKX low 12 4 MAX SLAVE MIN 2 - 12P 5 + 24P MAX ns ns
NO.
UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (see Figure 52)
ADVANCE INFORMATION
NO.
PARAMETER
-5E0, A-5E0, -6E3, A-6E3, -7E3 MASTER SLAVE MIN MAX T+3 L+3 4 L+3 4P + 3 12P + 17 12P + 2.8 20P + 17 MIN MAX T-2 L-2 -2 L-2
UNIT
1 2 3 6 7
th(CKXL-FXL) td(FXL-CKXH) td(CKXH-DXV) tdis(CKXL-DXHZ) tdis(FXH-DXHZ)
Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX low Disable time, DX high impedance following last data bit from FSX high
ns ns ns ns ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 8P + 1.8 16P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX).
122
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
CLKX 1 FSX 7 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 8 3 Bit(n-1) 5 (n-2) (n-3) (n-4) (n-2) (n-3) (n-4) 2
Figure 52. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (see Figure 53)
-5E0, A-5E0, -6E3, A-6E3, -7E3 MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high 12 4 MAX SLAVE MIN 2 - 12P 5 + 24P MAX ns ns
NO.
UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (see Figure 53)
-5E0, A-5E0, -6E3, A-6E3, -7E3 MASTER SLAVE MIN 1 2 3 6 th(CKXL-FXL) td(FXL-CKXH) td(CKXL-DXV) tdis(CKXL-DXHZ) Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# Delay time, CLKX low to DX valid Disable time, DX high impedance following last data bit from CLKX low L-2 T-2 -2 -2 MAX L+3 T+3 4 12P + 4 4 12P + 3 20P + 17 20P + 17 MIN MAX ns ns ns ns
ADVANCE INFORMATION
NO.
PARAMETER
UNIT
7 td(FXL-DXV) Delay time, FSX low to DX valid H-2 H+4 8P + 2 16P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). CLKX 1 FSX 6 Bit 0 7 Bit(n-1) 4 DR Bit 0 Bit(n-1) 3 (n-2) 5 (n-2) (n-3) (n-4) (n-3) (n-4) 2
DX
Figure 53. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 54)
-5E0, A-5E0, -6E3, A-6E3, -7E3 MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high 12 4 MAX SLAVE MIN 2 - 12P 5 + 24P MAX ns ns
NO.
UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 54)
NO.
PARAMETER
UNIT MAX ns ns
MIN 1 2 3 6 7 th(CKXH-FXL) td(FXL-CKXL) td(CKXL-DXV) tdis(CKXH-DXHZ) tdis(FXH-DXHZ) Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# Delay time, CLKX low to DX valid Disable time, DX high impedance following last data bit from CLKX high Disable time, DX high impedance following last data bit from FSX high T-2 H-2 -2 H-2
MAX T+3 H+3
MIN
4 12P + 4 H+3 4P + 3
20P + 17
ns ns
12P + 17
ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 8P + 2 16P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX).
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-5E0, A-5E0, -6E3, A-6E3, -7E3 MASTER SLAVE
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
CLKX 1 FSX 7 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 8 Bit(n-1) 5 (n-2) (n-3) (n-4) 3 (n-2) (n-3) (n-4) 2
Figure 54. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
ADVANCE INFORMATION
126
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 55)
-5E0, A-5E0, -6E3, A-6E3, -7E3 MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high 12 4 MAX SLAVE MIN 2 - 12P 5 + 24P MAX ns ns
NO.
UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 55)
NO.
PARAMETER
UNIT MAX ns ns
MIN 1 2 3 6 th(CKXH-FXL) td(FXL-CKXL) td(CKXH-DXV) tdis(CKXH-DXHZ) Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX high H-2 T-2 -2 -2
MAX H+3 T+1
MIN
4 12P + 4 4 12P + 3
20P + 17 20P + 17
ns ns
7 td(FXL-DXV) Delay time, FSX low to DX valid L-2 L+4 8P + 2 16P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX).
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-5E0, A-5E0, -6E3, A-6E3, -7E3 MASTER SLAVE
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
CLKX 1 FSX 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 7 Bit(n-1) 3 (n-2) 5 (n-2) (n-3) (n-4) (n-3) (n-4) 2
Figure 55. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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128
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
UTOPIA SLAVE TIMING [C6415 AND C6416 ONLY] timing requirements for UXCLK (see Figure 56)
NO. -5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 1 2 3 4 tc(UXCK) tw(UXCKH) tw(UXCKL) tt(UXCK) Cycle time, UXCLK Pulse duration, UXCLK high Pulse duration, UXCLK low Transition time, UXCLK 20 0.4tc(UXCK) 0.4tc(UXCK) 0.6tc(UXCK) 0.6tc(UXCK) 2 MAX ns ns ns ns UNIT
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
1 2 UXCLK 3
4
4
Figure 56. UXCLK Timing
timing requirements for URCLK (see Figure 57)
NO. -5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 1 2 3 4 tc(URCK) tw(URCKH) tw(URCKL) tt(URCK) Cycle time, URCLK Pulse duration, URCLK high Pulse duration, URCLK low Transition time, URCLK 20 0.4tc(URCK) 0.4tc(URCK) 0.6tc(URCK) 0.6tc(URCK) 2 MAX ns ns ns ns UNIT
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
1 2 URCLK 3
4
4
Figure 57. URCLK Timing
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
UTOPIA SLAVE TIMING [C6415 AND C6416 ONLY] (CONTINUED) timing requirements for UTOPIA Slave transmit (see Figure 58)
-5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 2 3 8 9 tsu(UXAV-UXCH) th(UXCH-UXAV) tsu(UXENBL-UXCH) th(UXCH-UXENBL) Setup time, UXADDR valid before UXCLK high Hold time, UXADDR valid after UXCLK high Setup time, UXENB low before UXCLK high Hold time, UXENB low after UXCLK high 4 1 4 1 MAX ns ns ns ns
NO.
UNIT
switching characteristics over recommended operating conditions for UTOPIA Slave transmit (see Figure 58)
ADVANCE INFORMATION
NO.
PARAMETER
-5E0, A-5E0, -6E3, A-6E3, -7E3 MIN MAX 12 12 12 18.5 12 3 3 3 9 3 3
UNIT
1 4 5 6 7 10
td(UXCH-UXDV) td(UXCH-UXCLAV) td(UXCH-UXCLAVL) td(UXCH-UXCLAVHZ) tw(UXCLAVL-UXCLAVHZ) td(UXCH-UXSV)
Delay time, UXCLK high to UXDATA valid Delay time, UXCLK high to UXCLAV driven active value Delay time, UXCLK high to UXCLAV driven inactive low Delay time, UXCLK high to UXCLAV going Hi-Z Pulse duration (low), UXCLAV low to UXCLAV Hi-Z Delay time, UXCLK high to UXSOC valid
ns ns ns ns ns ns
UXCLK 1 UXDATA[7:0] P45 P46 P47 P48 3 2 UXADDR[4:0] 0 x1F N 0x1F N 0x1F 6 7 4 UXCLAV N 9 UXENB 10 UXSOC The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLAV and UXSOC signals). 8 N 5 N+1 0x1F H1
Figure 58. UTOPIA Slave Transmit Timing
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
UTOPIA SLAVE TIMING [C6415 AND C6416 ONLY] (CONTINUED) timing requirements for UTOPIA Slave receive (see Figure 59)
NO. -5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 1 2 3 4 9 10 11 12 tsu(URDV-URCH) th(URCH-URDV) tsu(URAV-URCH) th(URCH-URAV) tsu(URENBL-URCH) th(URCH-URENBL) tsu(URSH-URCH) th(URCH-URSH) Setup time, URDATA valid before URCLK high Hold time, URDATA valid after URCLK high Setup time, URADDR valid before URCLK high Hold time, URADDR valid after URCLK high Setup time, URENB low before URCLK high Hold time, URENB low after URCLK high Setup time, URSOC high before URCLK high Hold time, URSOC high after URCLK high 4 1 4 1 4 1 4 1 MAX ns ns ns ns ns ns ns ns UNIT
NO.
PARAMETER
-5E0, A-5E0, -6E3, A-6E3, -7E3 MIN MAX 12 12 18.5 3 3 9 3
UNIT
5 6 7 8
td(URCH-URCLAV) td(URCH-URCLAVL) td(URCH-URCLAVHZ) tw(URCLAVL-URCLAVHZ) URCLK
Delay time, URCLK high to URCLAV driven active value Delay time, URCLK high to URCLAV driven inactive low Delay time, URCLK high to URCLAV going Hi-Z Pulse duration (low), URCLAV low to URCLAV Hi-Z
ns ns ns ns
2 1 URDATA[7:0] P48 4 3 URADDR[4:0] N 0x1F N+1 0x1F 7 5 URCLAV N 10 URENB 11 URSOC The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLAV and URSOC signals). 12 9 N+1 6 8 N+2 N+2 0x1F H1 H2 H3
Figure 59. UTOPIA Slave Receive Timing
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ADVANCE INFORMATION
switching characteristics over recommended operating conditions for UTOPIA Slave receive (see Figure 59)
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
TIMER TIMING timing requirements for timer inputs (see Figure 60)
NO. -5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 1 2 Pulse duration, TINP low P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. tw(TINPH) tw(TINPL) Pulse duration, TINP high 8P 8P MAX ns ns UNIT
switching characteristics over recommended operating conditions for timer outputs (see Figure 60)
-5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 3 4 tw(TOUTH) tw(TOUTL) Pulse duration, TOUT high Pulse duration, TOUT low 8P -3 8P -3 MAX ns ns
NO.
PARAMETER
UNIT
ADVANCE INFORMATION
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. 2 1 TINPx 3 TOUTx 4
Figure 60. Timer Timing
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING timing requirements for GPIO inputs (see Figure 61)
NO. -5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 1 tw(GPIH) tw(GPIL) Pulse duration, GPIx high 8P MAX ns UNIT
2 Pulse duration, GPIx low 8P ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to at least 12P to allow the DSP enough time to access the GPIO register through the CFGBUS.
switching characteristics over recommended operating conditions for GPIO outputs (see Figure 61)
-5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 3 4 Pulse duration, GPOx low P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. 2 1 GPIx 3 GPOx 4 tw(GPOH) tw(GPOL) Pulse duration, GPOx high 32P 32P MAX ns ns
NO.
PARAMETER
UNIT
Figure 61. GPIO Port Timing
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133
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 62)
NO. -5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 1 3 4 tc(TCK) tsu(TDIV-TCKH) th(TCKH-TDIV) Cycle time, TCK Setup time, TDI/TMS/TRST valid before TCK high Hold time, TDI/TMS/TRST valid after TCK high 35 10 9 MAX ns ns ns UNIT
switching characteristics over recommended operating conditions for JTAG test port (see Figure 62)
-5E0, A-5E0, -6E3, A-6E3, -7E3 MIN 2 td(TCKL-TDOV) Delay time, TCK low to TDO valid 0 MAX 18 ns
ADVANCE INFORMATION
NO.
PARAMETER
UNIT
1 TCK 2 TDO 4 3 TDI/TMS/TRST 2
Figure 62. JTAG Test-Port Timing
134
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TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
MECHANICAL DATA
GLZ and ZLZ (S-PBGA-N532)
23,10 22,90
PLASTIC BALL GRID ARRAY
SQ 0,80
20,00 TYP 0,40
AF AE AD AC AB AA Y V U T R P
A1 Corner
N K J H G F E D C B A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26
Heat Slug 3,30 MAX 1,00 NOM
Bottom View
Seating Plane 0,55 0,45 0,10 M
0,45 0,35
0,12 4201884/C 11/01
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Thermally enhanced plastic package with heat slug (HSL) Flip chip application only
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0,40
L
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M
0,80
W
TMS320C6414, TMS320C6415, TMS320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
SPRS146K - FEBRUARY 2001 - REVISED MARCH 2004
thermal resistance characteristics (S-PBGA package)
NO 1 2 3 4 5 6 7 RJC RJB RJA RJA RJA RJA PsiJT Junction-to-case Junction-to-board Junction-to-free air Junction-to-free air Junction-to-free air Junction-to-free air Junction-to-package top Air Flow (m/s) N/A N/A 0.00 0.5 1.0 2.00 N/A C/W 1.55 9.1 17.9 15.02 13.4 11.89 0.5 C/W (with Heat Sink) 1.0 9.0 13.8 8.95 7.35 6.46 0.5
8 PsiJB Junction-to-board N/A 7.4 7.4 m/s = meters per second These thermal resistance numbers were modeled using a heat sink, part number 374024B00035, manufactured by AAVID Thermalloy. AAVID Thermalloy also manufactures a similar epoxy-mounted heat sink, part number 374024B00000. When operating at 720 MHz, a heat sink should be used to reduce the thermal resistance characteristics of the package. TI recommends a passive, laminar heat sink, similar to the part numbers mentioned above.
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