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| x CMOS x Maximum Output Current: 100mA (VOUT=5.0V) x Highly Accurate Output Voltage: 2% x Output Voltage Range: 2.0V~ 6.0V x Highly Accurate Voltage Detection: 2% x No Load Supply Current: 3.2A(5.0V) x SOT-25 Package s Applications q Battery use q Battery life & charge detection q Memory battery back-up circuits q Microprocessor reset circuitry q Power failure detection q Voltage Sources Reference q Cameras, Video Cameras q Various Portable Devices w s General Description The XC66D series consists of a voltage detector and voltage regulator built into the one chip and is, essentially, a voltage regulator with voltage detect capabilities. Low power consumption and high accuracy is achieved through CMOS and laser trimming technologies. The detector features an output driver, hysteresis circuit, comparator and extremely accurate standard voltage. The regulator features an error correction circuit, output driver with current limiter functions, minimal input-output voltage differential and similary accurate standard voltage. SOT-25 (150mW) package is available. s Features Max. output current: 100mA (Within max. continuous total power dissipation, VOUT=5.0V) Output voltage range: 2.0V ~ 6.0V programmable in 0.1V steps (Standard 5.0V) Highly accurate output voltage: Set-up voltage accuracy 2% Output voltage temp. characteristics: Typ. 100ppm/: Detect voltage range: 1.8V ~ 6.0V programmable in 0.1V steps Highly accurate detect voltage: Set-up voltage accuracy 2% Low power consumption: Typ. 3.2A (VOUT= 5.0V) Detect voltage temp. characteristics: Typ. 100ppm/: Detect voltage output configuration: N-ch open drain CMOS (High level =VOUT) Input stability: Typ. 0.1%/V Ultra small package: SOT- 25 (150mW) mini-mold s Pin Configuration VOUT VIN s Pin Assignment PIN NUMBER PIN NAME VDOUT VSS VDIN VIN VOUT FUNCTION Voltage Detect Output Ground Voltage Detect Input Power Supply Voltage Regulator Output 4 5 1 2 3 1 VDOUT 2 VSS 3 -VDIN 4 5 SOT-25 (TOP VIEW) s Block Diagram (1) XC66DC CMOS output (High level =VOUT) (2) XC66DN N-ch open drain VIN Voltage Limiter VOUT VIN Voltage Limiter VOUT Vref Vref VDIN VDOUT VDIN VDOUT VSS VSS s Absolute Maximum Ratings PARAMETER Regulator Input Voltage Regulator Output Current Regulator Output Voltage SYMBOL VIN IOUT VOUT VDIN IDOUT VDOUT CMOS output (High level =VOUT) Pd Topr Tstg VSS -0.3 ~ VIN +0.3 150 -30 ~ +80 -40 ~ +125 RATINGS VSS -0.3 ~ 12 150 VSS -0.3 ~ VIN +0.3 VSS -0.3 ~ 12 50 VSS -0.3 ~ 12 Ta=25: UNITS V mA V V mA V w Detector Output Voltage Detector Input Voltage Detector Output Current N-ch open drain output Continuous Total Power Dissipation Operating Ambient Temperature Storage Temperature mW : : Note: Please ensure that {(VIN -VOUT ) x IOUT} + {IDOUT x VDOUT} + {VIN x ISS} does not exceed the stated Pd values. s Electrical Characteristics VDF =1.8V ~ 6.0V, VOUT(T) (Note1) =5V PARAMETER Detect Voltage Hysteresis Range Operating Voltage SYMBOL VDF VHYS VIN N-ch DETECTOR Output Curret IDOUT P-ch VDS=0.5V VSS=1.5V =2.0V =3.0V =4.0V =5.0V VDS=0.9V VIN=VDIN=VOUT=8V (CMOS) VDIN=10V -30C Topr 80C CONDITIONS VIN = VDIN VIN = VDIN MIN (VDF) x 0.98 TYP VDF MAX (VDF) x 1.02 V V V Ta=25: UNITS CIRCUIT 1 1 - VDF VDF VDF x 0.02 x 0.05 x 0.08 1.5 0.3 3.0 5.0 6.0 7.0 4.9 100 10V 2.2 7.7 10.1 11.5 13.0 -5 0.4 100 5 20 260 0.1 100 3.2 10.0 -2 1.0 5.1 80 520 0.3 10.0 8.6 2 mA 6 A ppm/: V mA mV mV %/V ppm/: V mA 3 1 4 4 4 4 4 4 5 VDIN Input Current Detect Voltage Temp. Characteristics Output Voltage Maximum Output Current Load Stability REGULATOR Input - Output Voltage Differential Input Stability Output Voltage Temp. Characteristics Input Voltage Supply Current IDIN VOUT Topr * VDF VOUT (E) (Note2) IOUTmax VOUT Vdif (Note3) VOUT VIN * VOUT VOUT Topr * VOUT VIN ISS IOUT=10mA VIN = VOUT(T) + 1V VIN= VOUT(T) + 1V VOUT(T) x0.9 VOUT(E) VIN= VOUT(T) + 1V IOUT 80mA 1mA IOUT =60mA IOUT=10mA VIN VOUT(T) + 1V IOUT =10mA Topr 80C -30C VIN = VOUT(T) +1V - Note: 1. VOUT(T) : User specified output voltage. 2. VOUT(E) : Effective output voltage. (i.e. the output voltage when a stable (VOUT(T) + 1.0V) is provided, while maintaining a certain IOUT value.) 3. Vdif : Vdif = {VIN1 - VOUT1} VOUT1 : The voltage equal to 98% of the output voltage whenever a stable (VOUT(T) +1.0V) is provided at IOUT. VIN1 : The input voltage when the output is equal to VOUT(E) x 98%. s Timing Chart (Nch open drain pull up voltage =Input voltage VIN) Regulator Input Voltage (VIN) Regulator Set-up Voltage (VOUT(T)) 6 Min. Operating Voltage (VMIN) Ground Voltage (VSS) Detector Input Voltage (VDIN) Regulator Set-up Voltage (VOUT(T)) Release Voltage (VDR) Detect Voltage (VDF) Min. Operating Voltage (VMIN) Ground Voltage (VSS) Output Voltage (VDOUT) CMOS(High Level=VOUT) w 6 Min. Operating Voltage (VMIN) Ground Voltage (VSS) Output Voltage (VDOUT) Nch Open Drain 6 Min. Operating Voltage (VMIN) Ground Voltage (VSS) 1 2 3 A 4 5 1 2 3 B 4 5 s Operational Notes [Detector : CMOS Output ('High' level = VOUT)] Timing Chart A (VIN=VDIN) 1. When a voltage greater than the release voltage (VDR) is applied to the voltage input pin (VIN, VDIN), input voltage (VIN, VDIN) will gradually fall. When a voltage greater than the detect voltage (VDF) is applied to the voltage input pin (VIN, VDIN), the output pin(VDOUT) voltage will be equal to the regulator's output voltage (VOUT). * With Nch open drain configurations a state of high impedance means that should the pin be pulled up, voltage will be equal to pull up voltage. When input voltage (VIN, VDIN) fall below detect voltage (VDF), output voltage (VDOUT) will be equal to ground level (VSS). Should input voltage (VIN, VDIN) fall below the minimum operational voltage (VMIN), output will become unstable. Should VDIN fall below VMIN, voltage at the output pin (VDOUT) will be equal to ground level (VSS) . *With Nch open drain configurations output will equal pull up voltage as the output pin is generally pulled up. Should input voltage (VIN, VDIN) rise above ground voltage (VSS), output voltage (VDOUT) will equal ground level until the release voltage level (VDR) is reached. The output pin voltage (VDOUT) will be equal to the regulator output voltage (VOUT) when input voltage (VIN, VDIN) rises above release voltage. *With Nch open drain configurations it will be equal to the voltage dependent on pull up. 2. 3. 4. 5. Timing Chart B (VIN=voltages above set-up voltage + input/output voltage differential, VDIN = sweep voltage) Because a voltage higher than the minimum operating voltage is applied to the voltage input pin (VIN), ground voltage will be output at the output pin (VDOUT) during stage 3. (Stages 1, 2, 4, 5 are the same as in A above). Note : The difference between release voltage (VDR) and detect voltage (VDF) is the Hysteresis Range (6). s Standard Circuit CMOS Output (High Level =VOUT) VIN w 1F + (Tantalum) VDIN VOUT VDOUT VSS 1F + (Tantalum) Nch Open Drain VIN 1F + (Tantalum) VDIN VOUT VDOUT VSS 100k 1F + (Tantalum) s Notes on Use 1. In cases where there is no capacitance (CL), or the capacitance is small, or where a capacitor with an extremely low ESR value is used (e.g. ceramic), please use a capacitor (CL = 1.0F [Tantalum]) in order to stop oscillation that may occur as the phase margin becomes smaller. 2. To reduce impedance between the power supply and the IC's input pin, which in turn will stop oscillation resulting from input voltage changes, connect a capacitor (CIN = more than 1.0F, ESR low) to the input side of the IC. Further, operation may become unstable and oscillation may occur shoud impedance up to the IC's input be high (a state which could be brought about by several factors including which devices are added to the input side, the surrounding wiring and/or the input power supply.) Stability can be improved by regulating increases in input capacitance and by reducing impedance. 3. The regulator's input pin (VIN) and power supply pin are the same. Also, the voltage detector's power supply and the voltage regulator's power supply are the same. Therefore, to have the voltage detector operating normally, it is necessary to apply a voltage larger than the minimum operating voltage (1.5V) to the power supply input pin (VIN). 4. With CMOS output, the detector's output voltage equals the regulator's output voltage following release. Possible changes in the regulator's output voltage (VROUT), following regulator load changes, will be output at the detector's output pin (VDOUT). 5. As the operations of the detector will momentarily respond when steep rise and fall time voltages are input at the power supply pin (VIN), please ensure that the VIN(VDIN) pin's input frequency's rise and fall time is more than 5 sec/V. 6. When using with the detector input pin (VDIN) connected to the regulator output pin (VOUT), the detector will momentarily respond as a result of transient output voltage changes brought about by the regulator's load changes. With large load currents and/or large load transitions from 1mA to 80mA for example, output voltage will momentarily drop, so please add a capacitor where CL=more than 4.7mF. s Ordering Information XC66Dxxxxxxx ab c de DESIGNATOR a DESCRIPTION Detector Output Configuration C=CMOS(High level=VOUT) N=N-ch open drain Detect Voltage (VDF) 25=2.5V 35=3.8V DESIGNATOR d DESCRIPTION Package Type M=SOT-25 w b e c Regulator Output Voltage (VOUT) 33=3.3V 50=5.0V Device Orientation R=Embossed Tape (Orientation of Device:Right) L=Embossed Tape (Orientation of Device:Left) s Measuring Circuits Circuit 1 Circuit 2 100k w VIN VIN 1F + VDIN VOUT VDOUT VSS V 1F + VIN VIN VDIN VOUT VDOUT VSS A Circuit 3 Circuit 4 A VIN VIN VDIN VOUT VDOUT VSS 1F + VIN VIN VDIN VOUT VDOUT VSS 1F + V A Circuit 5 Circuit 6 VIN A VDIN VOUT VDOUT VIN VIN VDIN VOUT VDOUT VSS A VIN VSS (1) SUPPLY CURRENT vs. REGULATOR INPUT VOLTAGE (2) SUPPLY CURRENT vs. DETECTOR INPUT VOLTAGE (3) SUPPLY CURRENT vs. REGULATOR, DETECTOR INPUT VOLTAGE SUPPLY CURRENT:ISS(A) SUPPLY CURRENT:ISS(A) SUPPLY CURRENT:ISS(A) w REGULATOR INPUT VOLTAGE:VIN(V) REGULATOR INPUT VOLTAGE:VIN(V) INPUT VOLTAGE:VIN,VDIN(V) (4) DETECT VOLTAGE, RELEASE VOLTAGE vs. AMBIENT TEMP. DETECT, RELEASE VOLTAGE :VDF, VDR(V) (5) DETECTOR OUTPUT VOLTAGE vs. DETECTOR INPUT VOLTAGE DETECTOR OUTPUT VOLTAGE :VDOUT(V) (6) DETECTOR Nch DRIVER OUTPUT CURRENT vs. VDS DETECTOR Nch DRIVER OUTPUT CURRENT:IDOUTNch (mA) AMBIENT TEMP. :Topr(:) DETECTOR INPUT VOLTAGE :VDIN(V) DETECTOR INPUT VOLTAGE:VDIN (V) (7) DETECTOR Nch DRIVER OUTPUT CURRENT vs. DETECTOR INPUT VOLTAGE DETECTOR Nch DRIVER OUTPUT CURRENT:IDOUTNch (mA) DETECTOR INPUT VOLTAGE:VDS (V) DETECTOR Nch DRIVER OUTPUT CURRENT:IDOUTNch (mA) DETECTOR INPUT VOLTAGE:VDS (V) VIN=3.2V CIN=1F(Tanatlum), CL=1F(Tanatlum) (8) REGULATOR OUTPUT VOLTAGE vs. REGULATOR OUTPUT CURRENT REGULATOR OUTPUT VOLTAGE:VOUT (V) REGULATOR OUTPUT VOLTAGE:VOUT (V) VIN=3.2V CIN=1F(Tanatlum), CL=1F(Tanatlum) REGULATOR OUTPUT CURRENT:IOUT (mA) REGULATOR OUTPUT CURRENT:IOUT (mA) s XC66D Electrical Characteristics (9) REGULATOR OUTPUT VOLTAGE vs. REGULATOR INPUT VOLTAGE Ta=25: CIN=1F (Tanatlum), CL=1F (Tantlum) Ta=25: CIN=1F (Tanatlum), CL=1F (Tantlum) w REGULATOR OUTPUT VOLTAGE:VOUT (V) REGULATOR INPUT VOLTAGE:VIN (V) REGULATOR OUTPUT VOLTAGE:VOUT (V) REGULATOR INPUT VOLTAGE:VIN (V) (10) INPUT/OUTPUT VOLTAGE DIFFERENTIAL vs. REGULATOR OUTPUT CURRENT VIN=3.2V CIN=1F(Tanatalum), CL=1F(Tantalum) (11) REGULATOR OUTPUT VOLTAGE vs. AMBIENT TEMP. VIN=3.2V CIN=1F(Tanatalum), CL=1F(Tantalum) REGULATOR OUTPUT CURRENT:IOUT (mA) REGULATOR OUTPUT VOLTAGE:VOUT (V) INPUT/OUTPUT VOLTAGE DIFF.:Vdif (V) AMBIENT TEMP.:Topr (C) (12) INPUT TRANSIENT RESPONSE 1 REGULATOR OUTPUT VOLTAGE:VOUT(T) REGULATOR INPUT VOLTAGE:VIN(V) Input Voltage Input Voltage Output Voltage Output Voltage TIME (0.4msec/div) TIME (0.4msec/div) REGULATOR OUTPUT VOLTAGE:VOUT(T) IOUT=1mA CIN, CL=1F (Tanatlum) REGULATOR INPUT VOLTAGE:VIN(V) IOUT=10mA CIN, CL=1F (Tanatlum) s XC66D Electrical Characteristics (13) INPUT TRANSIENT RESPONSE 2 REGULATOR OUTPUT VOLTAGE:VOUT(T) REGULATOR INPUT VOLTAGE:VIN(V) IOUT=1mA CIN, CL=1F (Tanatlum) IOUT=10mA CIN, CL=1F (Tanatlum) Input Voltage Input Voltage REGULATOR OUTPUT VOLTAGE:VOUT(T) REGULATOR INPUT VOLTAGE:VIN(V) w Output Voltage Output Voltage TIME (1msec/div) TIME (1msec/div) (14) LOAD TRANSIENT RESPONSE (15) RIPPLE REJECTION RATE REGULATOR OUTPUT VOLTAGE:VOUT(V) VIN=3.2V, CL=1F (Tanatlum) Output Voltage Output Current TIME (1msec/div) REGULATOR OUTPUT CURRENT:IOUT(mA) RIPPLE REJECTION RATE:RR (dB) VIN=3.2VDC+1Vp-pAC IOUT=10mA, CL=1F(Tanatlum) RIPPLE FREQUENCY:f (kHz) |
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