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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
WIDE INPUT SYNCHRONOUS BUCK CONTROLLER
FEATURES D D D D
Operating Input Voltage 8 V to 40 V Input Voltage Feed-Forward Compensation < 1 % Internal 0.7-V Reference Programmable Fixed-Frequency Up to 1 MHz Voltage Mode Controller Synchronous N-Channel MOSFETs
DESCRIPTION
The TPS4005x is a family of high-voltage, wide input (8 V to 40 V), synchronous, step-down converters. The TPS4005x family offers design flexibility with a variety of user programmable functions, including soft-start, UVLO, operating frequency, voltage feed-forward, high-side current limit, and loop compensation. The TPS4005x are also synchronizable to an external supply. They incorporate MOSFET gate drivers for external N-channel high-side and synchronous rectifier (SR) MOSFETs. Gate drive logic incorporates anti-cross conduction circuitry to prevent simultaneous high-side and synchronous rectifier conduction. The TPS40051 and TPS40053 permit the output to sink current by allowing the synchronous rectifier to turn on without the switch node (SW) first collapsing. The TPS4005x uses voltage feed-forward control techniques to provide good line regulation over the wide (4:1) input voltage range, and fast response to input line transients with near constant gain with input variation which eases loop compensation. The externally programmable current limit provides pulse-by-pulse current limit, as well as hiccup mode operation utilizing an internal fault counter for longer duration overloads.
UDG-02130
D Internal Gate Drive Outputs for High-Side and D D D D D D D D D D D D
16-Pin PowerPADt Package (JC = 2C/W) Thermal Shutdown Externally Synchronizable Programmable High-Side Current Limit Programmable Closed-Loop Soft-Start TPS40050 Source Only TPS40051 Source/Sink TPS40053 Source/Sink With VOUT Prebias
APPLICATIONS
Networking Equipment Telecom Equipment Base Stations Servers
SIMPLIFIED APPLICATION
TPS40050PWP 1 2 VIN 3 4 5 6 7 8 KFF RT BP5 SYNC SGND SS/SD VFB COMP ILIM 16 VIN 15 BOOST 14 HDRV 13 SW 12 BP10 11 LDRV 10 PGND 9 VOUT - +
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPADt is trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, 2003, Texas Instruments Incorporated
TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA -40C to 85C 40 C 85 C LOAD CURRENT SOURCE SOURCE/SINK SOURCE/SINK(2) PACKAGE Plastic HTSSOP (PWP)(1) Plastic HTSSOP (PWP)(1) Plastic HTSSOP (PWP)(1) PART NUMBER TPS40050PWP TPS40051PWP TPS40053PWP
(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40050PWPR). See the application section of the data sheet for PowerPAD drawing and layout information. (2) Source only mode (DCM) during soft-start only. Source/sink during normal operation.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) TPS40050 TPS40051 TPS40053 VIN VFB, KFF, SS, SYNC Input voltage range, VI range SW SW, transient < 50 ns Output voltage range, VO Output current, IOUT Operating virtual junction temperature range, TJ Storage temperature, Tstg COMP, KFF, RT, SS RT 45 -0.3 to 6 -0.3 to 45 -2.5 -0.3 to 6 200 -40 to 125 -55 to 150 C C A V UNIT
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN Input voltage, VI Operating free-air temperature, TA PWP PACKAGE(3)(4) (TOP VIEW) 8 -40 NOM MAX 40 85 UNIT V C
KFF RT BP5 SYNC SGND SS/SD VFB COMP
1 2 3 4 5 6 7 8
THERMAL PAD
16 15 14 13 12 11 10 9
ILIM VIN BOOST HDRV SW BP10 LDRV PGND
(3) For more information on the PWP package, refer to TI Technical Brief, Literature No. SLMA002. (4) PowerPADt heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins.
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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
ELECTRICAL CHARACTERISTICS
TJ = -40C to 85C, VIN = 24 Vdc, RT = 90.9 k, IKFF = 150 A, fSW = 500 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN INPUT SUPPLY VIN Input voltage range, VIN OPERATING CURRENT IDD BP5 Quiescent current Output drivers not switching 4.7 RT = 90.9 k VPEAK-VVAL 480 2 5 50 2.38 VFB = 0 V, fSW 500 kHz VFB = 0 V, 500 kHz fSW 1 MHz VFB 0.75 V 85% 80% 0% 3.35 20 1.75 CSS = 220 pF CSS = 220 pF, 1.6 0 V VSS 1.6 V 115 9.0 TA = 25C 0C TA 85C -40C TA 85C GBW AVOL IOH IOL VOH VOL IBIAS (1) (2) (3) Gain bandwidth Open loop gain High-level output source current Low-level output sink current High-level output voltage Low-level output voltage Input bias current ISOURCE = 500 A ISINK = 500 A VFB = 0.7 V 0.698 0.690 0.690 3.0 60 2.0 2.5 3.2 2.35 3.7 2.2 155 9.6 0.700 0.700 0.700 5.0 80 4.0 4.0 3.5 0.20 100 0.35 200 V nA mA 2.8 205 10.3 0.704 0.707 0.715 MHz dB V 3.48 3.65 1100 2.85 V A A V s s 2.50 2.58 94% 8 1.5 5.0 500 2.0 5 0.8 10 V V A ns V 40 3.0 5.2 550 V mA V kHz TYP MAX UNIT
VBP5 Input voltage OSCILLATOR/RAMP GENERATOR(3) fOSC Accuracy VRAMP PWM ramp voltage(1) VIH VIL ISYNC VRT High-level input voltage, SYNC Low-level input voltage, SYNC Input current, SYNC Pulse width, SYNC RT voltage Maximum duty cycle Minumum duty cycle VKFF IKFF ISS VSS tDSCH tSS BP10 VBP10 Input voltage ERROR AMPLIFIER Feed-forward voltage Feed-forward current operating range(1) Soft-start source current Soft-start clamp voltage Discharge time Soft-start time
SOFT START
V
VFB
Feedback in ut voltage input
Ensured by design. Not production tested. All parameters measured at zero power dissipation. IKFF increases with SYNC frequency, IKFF decreases with maximum duty cycle
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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
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ELECTRICAL CHARACTERISTICS
TJ = -40C to 85C, VIN = 24 Vdc, RT = 90.9 k, IKFF = 150 A, fSW = 500 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN CURRENT LIMIT ISINK Current limit sink current Propagation delay to output tON tOFF VOS Switch leading-edge blanking pulse time(1) Off time during a fault TA = 25C VILIM = 23.6 V, VILIM = 23.6 V, OUTPUT DRIVER tLRISE tLFALL tHRISE tHFALL VOH VOL VOH VOL Low-side driver rise time Low-side driver fall time High-side driver rise time High-side driver fall time High-level ouput voltage, HDRV Low-level ouput voltage, HDRV High-level ouput voltage, LDRV Low-level ouput voltage, LDRV Minimum controllable pulse width SS/SD SHUTDOWN VSD VEN Shutdown threshold voltage Device active threshold voltage Outputs off 90 190 31.5 -5.5 125 210 32.5 -0.5 150 245 33.5 4.5 25 165 20 RKFF = 39.2 k 8.19 9.00 9.58 mV CLOAD = 2200 pF (HDRV - SW) pF, IHDRV = -0.1 A (HDRV - SW) IHDRV = 0.1 A (HDRV - SW) ILDRV = -0.1 A ILDRV = 0.1 A 100 BP10 -1.4 V BP10 - 1.0 V 0.5 150 ns BOOST -1.5 V CLOAD = 2200 pF 48 24 48 36 BOOST -1.0 V 0.75 V 96 48 96 72 ns -125 0C TA 85C -40C TA 85C -140 -140 -75 VILIM = 23.7 V, VSW = (VILIM - 0.5 V) VILIM = 23.7 V, VSW = (VILIM - 2 V) 100 7 -30 -15 10 mV cycles 8.6 10.0 300 200 ns 11.5 A TYP MAX UNIT
Offset voltage SW vs. ILIM
BOOST REGULATOR VBOOST Output voltage VIN = 24.0 V RECTIFIER ZERO CURRENT COMPARATOR (TPS40050/TPS40053 SS ONLY) VSW Switch voltage SW NODE ILEAK Leakage current(1) THERMAL SHUTDOWN TSD UVLO VUVLO (1) (2) (3) KFF programmable threshold voltage V Shutdown temperature(1) Hysteresis(1) LDRV output OFF V mV A
C
Ensured by design. Not production tested. All parameters measured at zero power dissipation. IKFF increases with SYNC frequency, IKFF decreases with maximum duty cycle
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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
TERMINAL FUNCTIONS
TERMINAL NAME BOOST BP5 BP10 COMP HDRV ILIM KFF LDRV PGND RT SGND NO. 14 3 11 8 13 16 1 10 9 2 5 I/O O O O O O I I O - I - DESCRIPTION Gate drive voltage for the high side N-channel MOSFET. The BOOST voltage is 9 V greater than the input voltage. A 0.1-F ceramic capacitor should be connected from this pin to the SW pin. 5-V reference. This pin should be bypassed to ground with a 0.1-F ceramic capacitor. This pin is not for external use. 10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1-F ceramic capacitor. This pin is not for external use. Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the VFB pin to compensate the overall loop. The comp pin is internally clamped above the peak of the ramp to improve large signal transient response. Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW (MOSFET off). Current limit pin, used to set the overcurrent threshold. An internal current sink from this pin to ground sets a voltage drop across an external resistor connected from this pin to VCC. The voltage on this pin is compared to the voltage drop (VIN -SW) across the high side MOSFET during conduction. A resistor is connected from this pin to VIN to program the amount of voltage feed-forward. The current fed into this pin is internally divided and used to control the slope of the PWM ramp. Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground (MOSFET off). Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of the lower MOSFET(s). A resistor is connected from this pin to ground to set the internal oscillator and switching frequency. Signal ground reference for the device. Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The capacitor is charged with an internal current source of 2.3 A. The resulting voltage ramp on the SS pin is used as a second non-inverting input to the error amplifier. Output voltage regulation is controlled by the SS voltage ramp until the voltage on the SS pin reaches the internal reference voltage of 0.7 V. Pulling this pin low disables the controller. This pin is connected to the switched node of the converter and used for overcurrent sensing. The TPS40050 and TPS40053 versions use this pin for zero current sensing as well. Syncronization input for the device. This pin can be used to synchronize the oscillator to an external master frequency. Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference voltage, 0.7 V. Supply voltage for the device.
SS/SD
6
I
SW SYNC VFB VIN
12 4 7 15
I I I I
5
TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
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SIMPLIFIED BLOCK DIAGRAM
ILIM 16 10V Regulator VIN 15 CLK RT 2 CLK Oscillator - + 1V5REF 7 SYNC 4 Ramp Generator 7 CLK 07VREF 7 1V5REF 7 Reference Voltages 3V5REF 7 BP5 7 7 CL 3-bit up/down Fault Counter 7 7 n-channel Driver 13 HDRV 14 BOOST Restart Fault BP5 3 BP5 7 7 Fault 7 07VREF VFB 7 Soft Start SS/SD 6 + 0V7REF tstart Restart 7 COMP 8 Zero Current Detector (TPS40050 Only) 5 SGND 7 07VREF 7 CLK 7 SW S Q 9 RQ PGND + + 7 CL RQ n-channel Driver 10 LDRV S Q 12 SW 7 BP10
UDG-02128
BP10
11
BP10
KFF 1
6
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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
APPLICATION INFORMATION
SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)
The TPS4005x has independent clock oscillator and ramp generator circuits. The clock oscillator serves as the master clock to the ramp generator circuit. The switching frequency, fSW in kHz, of the clock oscillator is set by a single resistor (RT) to ground. The clock frequency is related to RT, in k by equation (1) and the relationship is charted in Figure 2. RT + 1 17.82 10 *6 * 23 kW (1)
f SW
PROGRAMMING THE RAMP GENERATOR CIRCUIT
The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations since the PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 1).
VIN
SW VPEAK COMP RAMP tON1 T1 t d + ON T tON2 T2 d1 > d2
UDG-02131
COMP VVALLEY
Figure 1. Voltage Feed-Forward Effect on PWM Duty Cycle
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APPLICATION INFORMATION
The PWM ramp must be faster than the master clock frequency or the PWM is prevented from starting. The PWM ramp time is programmed via a single resistor (RKFF) pulled up to VIN. RKFF is related to RT, and the minimum input voltage, VIN(min) through the following: R KFF + VIN (min) * 3.5 where: 58.14 RT ) 1340 W (2)
D VIN(min) is the ensured minimum start-up voltage. The actual start-up voltage is nominally about 10% lower
at 25C.
D RT is the timing resistance in k
The curve showing the RKFF required for a given switching frequency, fSW, is shown in Figure 3.
600
SWITCHING FREQUENCY vs TIMING RESISTANCE
FEED-FORWARD IMPEDANCE vs SWITCHING FREQUENCY
700 RKFF - Feed-Forward Impedance - k 600
500 RT - Timing Resistance - k
500
400
400 300
VIN = 9 V
300
VIN = 15 V 200
200
VIN = 25 V
100
100 0 100
0 0 200 400 600 800 1000 fSW - Switching Frequency - kHz
200
300 400
500
600
700
800
900 1000
fSW - Switching Frequency - kHz
Figure 2
Figure 3
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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
APPLICATION INFORMATION
UVLO OPERATION
The TPS4005x uses variable (user programmable) UVLO protection. The UVLO circuit holds the soft-start low until the input voltage has exceeded the user programmable undervoltage threshold. The TPS4005x uses the feed-forward pin, KFF, as a user programmable low-line UVLO detection. This variable low-line UVLO threshold compares the PWM ramp duration to the oscillator clock period. An undervoltage condition existis if the TPS4005x receives a clock pulse before the ramp has reached 90% of its full amplitude. The ramp duration is a function of the ramp slope, which is directly related to the current into the KFF pin. The KFF current is a function of the input voltage and the resistance from KFF to the input voltage. The KFF resistor can be referenced to the oscillator frequency as descibed in equation (3): R KFF + VIN (min) * 3.5 where:. 58.14 RT ) 1340 W (3)
D VIN is the desired start-up (UVLO) input voltage
The variable UVLO function uses a three-bit full adder to prevent spurious shut-downs or turn-ons due to spikes or fast line transients. When the adder reaches a total of seven counts in which the ramp duration is shorter than the clock cycle a powergood signal is asserted and a soft-start initiated, and the upper and lower MOSFETS are turned off. Once the soft-start is initiated, the UVLO cicruit must see a total count of seven cycles in which the ramp duration is longer than the clock cycle before an undervoltage condition is declared. (See Figure 4).
UVLO Threshold VIN
Clock PWM RAMP
1234567 PowerGood
12
1234567
UDG-02132
Figure 4. Undervoltage Lockout Operation Some applications may require an additional circuit to prevent false restarts at the UVLO voltage level. This applies to applications which have high impedance on the input voltage line or which have excessive ringing on the VIN line. The input voltage impedance can cause the input voltage to sag enough at start-up to cause a UVLO shutdown and subsequent restart. Excessive ringing can also affect the voltage seen by the device and cause a UVLO shutdown and restart. A simple external circuit provides a selectable amount of hysteresis to prevent the nuisance UVLO shutdown.
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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
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APPLICATION INFORMATION
Assuming a hysteresis current of 10% IKFF, and the peak detector charges to 8 V and VIN(min) = 18 V, the value of RA is calculated by: RA + RKFF 0.1 (8 * 3.5) V IN(min) * 3.5 + 565 kW ^ 562 kW (4)
CA is chosen to maintain the peak voltage between switching cycles. To keep the capacitor charge from drooping 0.1-V, or from 8 V to 7.9 V. CA + (8 * 3.5) RA 7.9 f SW (5)
The value of CA imay calculate to less than 10 pF, but some standard value up to 470 pF works adequately. The diode can be a small signal switching diode or Schottky rated for more then 20 V. Figure 5 illustrates a typical implementation using a small switching diode.
+ VIN - RA 562 k RKFF 182 k TPS40050PWP TPS40051PWP 1 KFF CA 470 pF 2 RT 3 BP5 4 SYNC 5 SGND 6 SS 7 VFB 8 COMP ILIM 16 VIN 15 BOOST 14 HDRV 13 SW 12 BP10 11 LDRV 10 PGND 9 DA 1N914, 1N4150 Type Signal Diode
UDG-03034
PWP
Figure 5. Hysteresis for Programmable UVLO
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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
APPLICATION INFORMATION
SELECTING THE INDUCTOR VALUE
The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but is physically larger for the same load current. Too small an inductance results in larger ripple currents and a greater number of (or more expensive output capacitors for) the same output ripple voltage requirement. A good compromise is to select the inductance value such that the converter doesn't enter discontinuous mode until the load approximated somewhere between 10% and 30% of the rated output. The inductance value is described in equation (6). L+ where:. V IN * V O VIN DI VO f SW (Henries) (6)
D VO is the output voltage D I is the peak-to-peak inductor current
CALCULATING THE OUTPUT CAPACITANCE
The output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any output voltage deviation requirement during a load transient. The output ripple voltage is a function of both the output capacitance and capacitor ESR. The worst case output ripple is described in equation (7). DV + DI ESR ) 1 CO VP*P (7)
8
f SW
The output ripple voltage is typically between 90% and 95% due to the ESR component. The output capacitance requirement typically increases in the presence of a load transient requirement. During a step load, the output capacitance must provide energy to the load (light to heavy load step) or absorb excess inductor energy (heavy to light load step) while maintaining the output voltage within acceptable limits. The amount of capacitance depends on the magnitude of the load step, the speed of the loop and the size of the inductor. Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in equation (8). EL + 1 2 where: I2 + where: I OH
2
L
I 2 (Joules)
(8)
* I OL
2
(Amperes)
2
(9)
D IOH is the output current under heavy load conditions D IOL is the output current under light load conditions
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TPS40050 TPS40051 TPS40053
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APPLICATION INFORMATION
Energy in the capacitor is described in equation (10). EC + 1 2 where: V2 + where: Vf
2
C
V2 (Joules)
(10)
* Vi
2
Volts2 (11)
D Vf is the final peak capacitor voltage D Vi is the initial capacitor voltage
Substituting equation (9) into equation (8), then substituting equation (11) into equation (10), then setting equation (11) equal to equation (10), and then solving for CO yields the capacitance described in equation (12). L CO + Vf I OH
2 2
* I OL
2
2
(Farads) * Vi (12)
PROGRAMMING SOFT START
TPS4005x uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start is programmed by charging an external capacitor (CSS) via an internally generated current source. The voltage on CSS is fed into a separate non-inverting input to the error amplifier (in addition to FB and 0.7-V VREF). The loop is closed on the lower of the CSS voltage or the internal reference voltage ( 0.7-V VREF). Once the CSS voltage rises above the internal reference voltage, regulation is based on the internal reference. To ensure a controlled ramp-up of the output voltage the soft-start time should be greater than the L-CO time constant as described in equation (13). t START w 2p L CO (seconds) (13)
There is a direct correlation between tSTART and the input current required during start-up. The faster tSTART, the higher the input current required during start-up. This relationship is describe in more detail in the section titled, Programming the Current Limit which follows. The soft-start capacitance, CSS, is described in equation (14). For applications in which the VIN supply ramps up slowly, (typically between 50 ms and 100 ms) it may be necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance UVLO tripping. The soft-start time should be longer than the time that the VIN supply transitions between 6 V and 7 V. C SS + 2.3 mA 0.7 V t START (Farads) (14)
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APPLICATION INFORMATION PROGRAMMING CURRENT LIMIT
The TPS4005x uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the MOSFET when the gate is driven high. The MOSFET voltage is compared to the voltage dropped across a resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated. The MOSFET remains off until the next switching cycle is initiated. The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a restart is issued and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the PWM is re-enabled. If the fault has been removed the output starts up normally. If the output is still present the counter counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 6 for typical overcurrent protection waveforms. The minimum current limit setpoint (ILIM) depends on tSTART, CO, VO, and the load current at turn-on (IL). I LIM + CO V O t START ) I L (Amperes) (15)
The current limit programming resistor (RILIM) is calculated using equation (16). R ILIM + where: I OC RDS(on)[max] I SINK 1.12 ) V OS I SINK (W) (16)
D ISINK is the current into the ILIM pin and is nominally 10 A, D IOC is the overcurrent setpoint which is the DC output current plus one-half of the peak inductor current D VOS is the overcurrent comparator offset and is nominally -48 mV
HDRV
CLOCK tBLANKING VIN-SW SS
7 CURRENT LIMIT TRIPS (HDRV CYCLE TERMINATED BY CURRENT LIMIT TRIP) 7 SOFT-START CYCLES
UDG-02133
Figure 6. Typical Current Limit Protection Waveforms
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APPLICATION INFORMATION
SYNCHRONIZING TO AN EXTERNAL SUPPLY
The TPS4005x can be synchronized to an external clock through the SYNC pin. The TPS4005x must be synchronized at a frequency 20% higher than its programmed free-run frequency. The clock frequency at the SYNC pin replaces the master clock generated by the oscillator circuit. Pulling the SYNC pin low programs the TPS4005x to freely run at the frequency programmed by RT. The higher synchronization must be factored in when programming the PWM ramp generator circuit. If the PWM ramp is interrupted by the SYNC pulse, a UVLO condition is declared and the PWM becomes disabled. Typically this is of concern under low-line conditions only. In any case, RKFF needs to be adjusted for the higher switching frequency.
LOOP COMPENSATION
Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS4005x uses voltage feedforward control, the gain of the PWM modulator with voltage feedforward circuit must be included. The modulator gain is described in Figure 7, with VIN being the minimum input voltage required to cause the ramp excursion to cover the entire switching period. A MOD + VIN VS or A MOD(dB) + 20 log V IN VS
(17)
Duty dycle, D, varies from 0 to 1 as the control voltage, VC, varies from the minimum ramp voltage to the maximum ramp voltage, VS. Also, for a synchronous buck converter, D = VO / VIN. To get the control voltage to output voltage modulator gain in terms of the input voltage and ramp voltage, D+ VO V +C V IN VS or VO V + IN VC VS
Calculate the Poles and Zeros For a buck converter using voltage mode control there is a double pole due to the output L-CO. The double pole is located at the frequency calculated in equation (18). f LC + 2p 1 L (Hertz) CO (18)
There is also a zero created by the output capacitance, CO, and its associated ESR. The ESR zero is located at the frequency calculated in equation (19). fZ + 2p 1 ESR CO (Hertz) (19)
The Bode plot for the open-loop control voltage to output voltage gain, VC to VO, for a buck converter with voltage feed-forward control operating in continuous mode is shown in Figure 8. The maximum crossover frequency (0 dB loop gain) is calculated in equation (20). fC + f SW 4 (Hertz)
(20)
Typically, fC is selected to be close to the midpoint between the L-CO double pole and the ESR zero. At this frequency, the control to output gain has a -2 slope (-40 dB/decade), while the Type III topology has a +1 slope (20 dB/decade), resulting in an overall closed loop -1 slope (-20 dB/decade).
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APPLICATION INFORMATION
Figure 8 shows the modulator gain, L-C filter, output capacitor ESR zero, and the resulting response to be compensated. A Type III topology, shown in Figure 9, has two zero-pole pairs in addition to a pole at the origin. The gain and phase boost of a Type III topology is shown in Figure 9. The two zeros are used to compensate the L-CO double pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide controlled gain roll-off. In many cases the second pole can be eliminated and the amplifier's gain roll-off used to roll-off the overall gain at higher frequencies.
PWM MODULATOR RELATIONSHIPS MODULATOR GAIN vs SWITCHING FREQUENCY
ESR Zero, + 1
AMOD = VIN / VS Modulator Gain - dB
VS VC
Resultant, - 1
D = VC / VS
LC Filter, - 2
100
1k
10 k
100 k
fSW - Switching Frequency - Hz
Figure 7
C2 (optional) -1 R3 C1 R2 0 dB C3 R1 VFB 7 8 VOUT RBIAS + -270 VREF
UDG-02189
Figure 8
+1 -1
-90 COMP 180
GAIN
PHASE
Figure 9. Type III Compensation Configuration
Figure 10. Type III Compensation Gain and Phase
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APPLICATION INFORMATION
The poles and zeros for a type III network are described in equations (21). f Z1 + f P1 + 2p 2p 1 R2 1 R2 C1 C2 (Hertz) (Hertz) f Z2 + f P2 + 2p 2p 1 R1 1 R3 C3 C3 (Hertz) (Hertz) (21)
The unity gain frequency is described in equation (22) fC + 2p 1 R1 C2 (Hertz) (22)
The double zeros, fZ1 and fZ2 and the double poles, fP1 and fP2 are chosen from Venable's The K Factor[1], which states: f Z1 + f Z2 + fC K and f P1 + f P2 + f C K (23)
To determine the factor K, the phase boost must be calculated knowing the desired phase margin, M, and the modulator phase shift, P, at the unity gain frequency, fC. In addition, Boost = M-P-90. It is best to measure P, but typical values range from -140 to -170. Then the value of K is calculated from:
2
K + Tan Boost ) 45o 4 Calculate the value of RBIAS to set the output voltage, VOUT. R BIAS + 0.7 R1 VOUT * 0.7 Minimum Load Resistance
(24)
(25)
Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too small. The error amplifier has a finite output source and sink current which must be considered when sizing R2. Too small a value does not allow the output to swing over its full range. R2 (MIN) + VC (max) I SOURCE (min) + 3.45 V + 1725 W 2 mA
(26)
CALCULATING THE BOOST AN BP10 BYPASS CAPACITOR
The BOOST capacitance provides a local, low impedance source for the high-side driver. The BOOST capacitor should be a good quality, high-frequency capacitor. The size of the bypass capacitor depends on the total gate charge of the MOSFET and the amount of droop allowed on the bypass capacitor. The BOOST capacitance is described in equation (27). C BOOST + Qg DV (Farads) (27)
The 10-V reference pin, BP10V needs to provide energy for both the synchronous MOSFET and the high-side MOSFET via the BOOST capacitor. Neglecting any efficiency penalty, the BP10V capacitance is described in equation (28). C BP10 +
16
Q gHS ) Q gSR DV
(Farads)
(28)
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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
APPLICATION INFORMATION
dv/dt INDUCED TURN-ON
MOSFETs are susceptible to dv/dt turn-on particularly in high-voltage (VDS) applications. The turn-on is caused by the capacitor divider that is formed by CGD and CGS. High dv/dt conditions and drain-to-source voltage, on the MOSFET causes current flow through CGD and causes the gate-to-source voltage to rise. If the gate-to-source voltage rises above the MOSFET threshold voltage, the MOSFET turns on, resulting in large shoot-through currents. Therefore, the SR MOSFET should be chosen so that the CGD capacitance is smaller than the CGS capacitance. A resistor with a value between 2 and 5 in the upper MOSFET gate return lead shapes the turn-on and dv/dt of the SW node and helps reduce the induced turn-on.
HIGH SIDE MOSFET POWER DISSIPATION
The power dissipated in the external high-side MOSFET is comprised of conduction and switching losses. The conduction losses are a function of the IRMS current through the MOSFET and the RDS(on) of the MOSFET. The high-side MOSFET conduction losses are defined by equation (29). P COND + I RMS where:
2
R DS(on)
1 ) TC R
T J * 25
(Watts)
(29)
D TCR is the temperature coefficient of the MOSFET RDS(on)
The TCR varies depending on MOSFET technology and manufacturer but is typically ranges between .0035 ppm/_C and .010 ppm/_C. The IRMS current for the high side MOSFET is described in equation (30). I RMS + I O d AmperesRMS (30)
For the high-side MOSFET the switching losses are descibed in equation (31). P SW(fsw) + VIN where: I D1 6 ts1 ) I D2 2 ts2 f SW
(31)
D ID1 and ID2 are the current magnitudes at the instance of MOSFET switching (See Figure 11)
ID1 and ID2 are a function of the inductor value and load current. The inductance value is usually selected so that the converter remains in continuous mode of operation until approximately 10% to 30% of the typical load is acheived. The change in inductor current is described in equation (32). DI + 2 where: I O (dis) (32)
D IO (dis) is the load current when the converter enters discontinuous mode of operation.
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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
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APPLICATION INFORMATION
ID2 IO ID1 d BODY DIODE CONDUCTION 1-d BODY DIODE CONDUCTION I
SW
0 ANTI-CROSS CONDUCTION
SYNCHRONOUS RECTIFIER ON
HIGH SIDE ON
UDG-02139
Figure 11. Inductor Current and SW Node Waveforms ID1 and ID2 can be calculated from equations (33). I D1 + I O * DI 2 where: and I D2 + I O ) DI 2 (Amperes) (33)
D I is the inductor ripple current. (see Figure 11)
The converter enters discontinuous mode when IO = I / 2. Refer to Selecting the Inductor Value section, equation (6), for more information. The transition times, ts1 and ts2, are a function of the external MOSFETS selected. Refer to the design example for calculating ts1 and ts2. The maximum allowable power dissipation in the MOSFET is determined by equation (34). PT + where: P T + PCOND ) PSW(fsw) (Watts) and JA is the package thermal impedance. (35) TJ * TA q JA (Watts) (34)
18
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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
APPLICATION INFORMATION
SYNCHRONOUS RECTIFIER MOSFET POWER DISSIPATION
The power dissipated in the synchronous rectifier MOSFET is comprised of three components: RDS(on) conduction losses, body diode conduction losses, and reverse recovery losses. RDS(on) conduction losses can be found using equation (29) and the RMS current through the synchronous rectifier MOSFET is described in equation (36). I RMS + I O 1*d Amperes RMS (36)
The body-diode conduction losses are due to forward conduction of the body diode during the anti-cross conduction delay time. The body diode conduction losses are described by equation (37). P DC + I O VF t DELAY f SW (Watts) (37)
where: D VF is the body diode forward voltage D tDELAY is the total delay time per switching period The reverse recovery losses are due to the time it takes for the body diode to recovery from a forward bias to a reverse blocking state. The reverse recovery losses are described in equation (38). P RR + 0.5 where: Q RR V IN f SW (Watts) (38)
D QRR is the reverse recovery charge of the body diode
The total synchronous rectifier MOSFET power dissipation is described in equation (39). P SR + PDC ) PRR ) PCOND (Watts) (39)
TPS4005X POWER DISSIPATION
The power dissipation in the TPS4005x is largely dependent on the MOSFET driver currents and the input voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power (neglecting external gate resistance, refer to [2] can be calculated from equation (40). P D + Qg VDR f SW (Watts) (40)
And the total power dissipation in the TPS40050, assuming the same MOSFET is selected for both the high-side and synchronous rectifier is described in equation (41). PT + or PT + 2 where: Qg f SW ) I Q V IN (Watts) (42) 2 PD ) IQ V DR V IN (Watts)
(41)
D IQ is the quiescent operating current (neglecting drivers)
19
TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
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APPLICATION INFORMATION
The maximum power capability of the device's PowerPad package is dependent on the layout as well as air flow. The thermal impedance from junction to air, assuming 2 oz. copper trace and thermal pad with solder and no air flow. JA = 36.51C/W The maximum allowable package power dissipation is related to ambient temperature by equation (34). Substituting equation (34) into equation (42) and solving for fSW yields the maximum operating frequency for the TPS4005x. The result is described in equation (43). T J*T A q JA f SW + 2 V DD Qg * IQ (Hz) (43)
20
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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
LAYOUT CONSIDERATIONS THE POWERPADt PACKAGE
The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD derives its name and low thermal impedance from the large bonding pad on the bottom of the device. For maximum thermal performance, the circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depends on the size of the PowerPAD package. For a 16-pin TSSOP (PWP) package the area is 5 mm x 3.4 mm [3]. Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD Thermally Enhanced Package[3] and the mechanical illustration at the end of this document for more information on the PowerPAD package.
X: Minimum PowerPAD = 1.8 mm Y: Minimum PowerPAD = 1.4 mm Thermal Pad
X
4,50 mm 6,60 mm 4,30 mm 6,20 mm
1
Y
10
Figure 12. PowerPAD Dimensions
MOSFET PACKAGING
MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions. In general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance (JA) and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends on proper layout and thermal management. The JA specified in the MOSFET data sheet refers to a given copper area and thickness. In most cases, a lowest thermal impedance of 40C/W requires one square inch of 2-ounce copper on a G-10/FR-4 board. Lower thermal impedances can be achieved at the expense of board area. Please refer to the selected MOSFET's data sheet for more information regarding proper mounting.
GROUNDING AND CIRCUIT LAYOUT CONSIDERATIONS
The TPS4005x provides separate signal ground (SGND) and power ground (PGND) pins. It is important that circuit grounds are properly separated. Each ground should consist of a plane to minimize its impedance if possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor (BP10), and the input capacitor should be connected to PGND plane at the input capacitor. Sensitive nodes such as the FB resistor divider, RT, and ILIM should be connected to the SGND plane. The SGND plane should only make a single point connection to the PGND plane. Component placement should ensure that bypass capacitors (BP10 and BP5) are located as close as possible to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW).
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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
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DESIGN EXAMPLE
D Input Voltage: 10 Vdc to 24 Vdc D Output voltage: 3.3 V 2% D Output current: 8 A (maximum, steady state), 10 A (surge, 10ms duration, 10% duty cycle maximum) D Output ripple: 33 mVP-P at 8 A D Output load response: 0.3 V => 10% to 90% step load change D Operating temperature: -40C to 85C D fSW=300 kHz
1. Calculate maximum and minimum duty cycles d MIN + 2. Select I In this case I is chosen so that the converter enters discontinuous mode at 20% of nominal load. DI + I O 2 0.2 + 3.2 A (45) V O(min) VIN(max) + 0.135 d MAX + V O(max) V IN(min) + 0.337 (44)
3. Calculate the power losses in the high-side MOSFET (Si7860DY) from (30) I RMS + I O d+8 0.337 + 4.64 A (46)
substituting (30) into (29) yields P COND + I RMS + 4.642 from (33) I D1 + I O * DI + 8 * 1.6 + 6.4 A 2 I D2 + I O ) DI + 8 ) 1.6 + 9.6 A 2 (48)
2
R DS(on)
1 ) T CR
T J * 25 C
O
(47)
0.008
(1 ) 0.007
(150 * 25)) + 0.323 W
tS1 (rise time) and tS2 (fall time) is approximated from the Gate Charge characteristics graph on the MOSFET data sheet. Let Q2-Q1 equal the charge required to increase the gate voltage to its plateau voltage (VPLT). The equivalent input capacitance during this period is: C IN + dQ + 4 nC + 1143 pF dV 3.5 V (49)
The time required to charge the equivalent capacitance is: 3.5 + 10 * (10 * 2) e
*t RC
; t1 + * R X C IN ln 6.5 + 10 8
1143 pF
ln 6.5 + 2.4 ns 8
(50)
where R is the effective gate drive resistance of 10 . The time it takes the drain-to-source voltage VDS to fall can be found from Gate Charge graph on the data sheet. During this time in the plateau region the change in charge is: DQ + Q3 * Q2 + 9.5 * 5 + 4.5 nC
22
(51)
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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
DESIGN EXAMPLE
During this period of time VGS is held constant. Therefore the MOSFET gate drive looks like a constant current source with a current of: I DRV + VDRV * VGS + 10 * 3.5 + 650 mA 10 RDRV
(52)
The time it takes for VDS to fall can now be calculated: t2 + DQ + 4.5 nC + 6.9 ns I DRV 0.65 A (53)
The total rise time is : t S1 + t r + t l ) t 2 + 2.4 n ) 6.9 n + 9.3 ns The similarly the fall time can be found from: t 3 + (Q3 * Q2) t 4 + * R DRV RDRV + 4.5 nC VPLT C IN 7.5 W + 9.6 ns 3.5 V (54)
(55) (56)
ln 3.5 + 12 ns 10
The total fall time is: t S2 + t f + t 3 ) t 4 + 9.6 ns ) 12 ns + 21.6 ns Substituting tS1, tS2, ID1, and ID2 into (31) yields: P SW f SW + 24 9.3 ns 6 6.4 ) 21.6 ns 2 9.6 300 kHz + 818 mW (58) (57)
The MOSFET junction temperature can be found by rearranging equation (34) and substituting equation (35) T J + PCOND ) PSW q JA ) T A
4. Calculate synchronous rectifier losses The synchronous rectifier MOSFET has two (2) loss components, conduction, and diode reverse recovery losses. The conduction losses are due to IRMS losses as well as body diode conduction losses during the dead time associated with the anti-cross conduction delay. The IRMS current through the synchronous rectifier from (36) I RMS + I O 1*d +8 1 * 0.135 + 7.44 A RMS (59)
The synchronous MOSFET conduction loss from (29) is: P COND + I RMS
2
R DS(on) + 7.44 2
0.008
(1 ) 0.007(150 * 25)) + 0.83 W
(60)
The body diode conduction loss from (37) is: P DC + I O P RR + 0.5 VFD t dead f SW + 8.0 A f SW + 0.5 0.8 V 100 ns 300 kHz + 0.192 W (61)
The body diode reverse recovery loss from (38) is: Q RR V IN 40 nC 24 V 300 kHz + 0.144 W (62)
The total power dissipated in the synchronous rectifier MOSFET from (39) is: P SR + PRR ) PCOND ) PDC + 0.144 ) 0.83 ) 0.192 + 1.17 W (63)
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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
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DESIGN EXAMPLE
The junction temperature of the synchronous rectifier at 85C is: T J + PSR q JA ) T A + (1.17) 40 ) 85 + 132 oC (64)
In typical applications, paralleling the synchronous rectifier MOSFET with a Schottky rectifier increases the overall converter efficiency by approximately 2% due to the lower power dissipation during the body diode conduction and reverse recovery periods. 5. Calculate the inductor value The inductor value is calculated from (6) using (45). L+ (24 * 3.3) 3.3 + 2.96 mH 24 3.2 300 kHz (65)
A 2.9-H Panasonic ETQP6F2R9LFA or COEV DXM1306-2R9-T is chosen. 6. Setting the switching frequency The clock frequency is set with a resistor (RT) from the RT pin to ground. The value of RT can be found from equation (1), with fSW in kHz. RT + 1 17.82 10 *6 * 23 kW + 164 kW N use 165 kW (66)
f SW
7. Programming the ramp generator circuit The PWM ramp is programmed through a resistor (RKFF) from the KFF pin to VIN. The ramp generator also controls the input UVLO voltage. For an undervoltage level of 10 V, RKFF can be calculated from (2) R KFF + VIN(min) * 3.5 58.14 R T ) 1340 W + 71 kW N use 71.5 kW (67)
8. Calculating the output capacitance (CO) In this example the output capacitance is determined by the load response requirement of V = 0.3 V for a 1 A to 8 A step load. CO can be calculated using (12) CO + 2.9 m 82 * 12 3.3 2 * 3.0 2 + 97 mF (68)
Using (7) we can calculate the ESR required to meet the output ripple requirements. 33 mV + 3.2 ESR ) 8 97 mF 1 300 kHz (69) (70)
ESR + 10.3 * 3.33 + 6.97 mW For this design example two (2) Panasonic SP EEFUEOJ1B1R capacitors, 180 F, 12 m were used. 9. Calculate the soft-start capacitor (CSS) This design, requires a soft-start time (tSTART) of 1 ms. CSS can be calculated on (14) C SS + 2.3 mA 0.7 V 1 ms + 3.29 nF + 3300 pF
(71)
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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
DESIGN EXAMPLE
10. Calculate the current limit resistor (RILIM) The current limit set point depends on, tSTART, VO,CO and ILOAD at start-up as shown in (15). For this design, I LIM u 360 mF 3.3 ) 8.0 + 9.2 A 1 ms (72)
For this design, set ILIM for 11.0 A minimum. From equation (16), R ILIM + 11 1.12 0.008 ) (* 0.048) + 7.86 kW * 4.8 kW + 3.06 kW ^ 3.09 kW 10 mA 10 mA (73)
11. Calculate loop compensation values Calculate the voltage feed forward constant (AMOD) from (17) A MOD + 10 + 5.0 2 A MOD(dB) + 20 log (5) + 14 dB (74) (75)
Calculate the output poles and zeros from (18) and (19) f LC + and fZ + 2p 1 0.012 180 mF + 73.7 kHz (77) 1 2p 2.9 mH 360 mF + 4.93 kHz (76)
Select the close-loop 0 dB crossover frequency, fC. For this example fC = 20 kHz. Select the double zero location for the Type III compensation network. The location for the pole-zero placement according to [1] is determined by the phase boost required at crossover. For this example a 60_ phase margin is desired. The required phase boost for this example is: Boost + M * P * 90 o + 60o * (* 145 o) * 90 o + 115o where (78)
D M is the desired phase margin D P is the modulator phase shift (-145 for this example)
2
o K + Tan 115 ) 45 o 4
[ 11.77 and K + 3.43
(79)
so, f P1 + f P2 + K 20 kHz + 69 kHz and f Z1 + f Z2 + 1 K 20 kHz + 5.8 kHz
Following the K-Factor calculations described in reference [1], the double zero is placed at 5.8 kHz, and the double pole is placed at 69 kHz. Equations (21) and (22) can be solved for the component values in Figure 9. Select R1 = 100 k.
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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
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DESIGN EXAMPLE
From equation (21): C3 + R3 + C2 + R2 + C1 + 2p 2p 2p 2p 2p 1 100 kW 1 270 pF 1 100 kW 1 82 pF 1 28 kW 5.8 kHz 69 kHz 20 kHz 69 kHz + 274 pF [ 270 pF, from f Z2 (80) (81) (82) (83) (84) (85)
+ 8.54 kW [ 8.45 kW, from f P2 + 79.6 pF ^ 82 pF, from f C
+ 28.1 kW ^ 28 kW, from f P1 + 980 pF [ 1000 pF, from f Z1
5.8 kHz
R BIAS + 0.7 100kW + 26.9 kW [ 26.7 kW 3.3 * 0.7
GATE DRIVE CONFIGURATION
Due to the possibility of dv/dt induced turn-on from the fast MOSFET switching times, high VDS voltage and low gate threshold voltage of the Si7860, the design includes a 3.3- resistor in the gate return of the upper MOSFET. This resistor can be used to shape the low-to-high transition of the switch mode and reduce the tendancy of dv/dt-induced turn on.
CALCULATING THE BOOST AND BP10V BYPASS CAPACITANCE
The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount of droop allowed on the bypass cap. The BOOST capacitance, allowing for a 0.5 voltage droop on the BOOST pin from (27) is C BOOST + Qg + 13 nC + 26 nF DV 0.5 V Q gHS ) Q gSR DV
(86)
and the BP10V capacitance from (28) is C BP(10 V) + + 2 Qg + 26 nC + 52 nF DV 0.5 V
(87)
For this application, a 0.1-F capacitor is used for the BOOST bypass capacitor and a 1.0-F capacitor is used for the BP10V. Figure 13 shows component selection for the 24-V to 3.3-V at 8 A dc-to-dc converter specified in the design example.
26
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Figure 13. 24-V to 3.3-V at 8-A DC-to-DC Converter Design Example
27
+ VIN - 330 F 330 F 71.5 k 1 2 165 k 0.1 F 3300 pF 6 7 1000 pF 28 k 8 82 pF COMP PWP PGND 9 SS VFB BP10 11 3 4 5 TPS40050PWP TPS40051PWP KFF RT BP5 SYNC SGND ILIM 16 VIN 15 BOOST 14 HDRV 13
3.09 k
100 pF
0.1 F
1.0 F 50 V Si7860 2.9 H
22 F 50 V
22 F 50 V
3.3 SW 12 8.45 k Si7860 LDRV 10 1.0 F 270 pF 100 k 180 F D1 30BQ060
+
VOUT 180 F
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
- 26.7 k
TPS40050 TPS40051 TPS40053
UDG-02190
TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
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REFERENCES
1. Venable, H. Dean, The K Factor: A New Mathematical Tool for Stability Analysis and Synthesis Proceedings of Powercon 10, pp A5-1 through A5-12 2. Balogh, Laszlo, Design and Application Guide for High Speed MOSFET Gate Drive Circuits, Texas Instruments/Unitrode Corporation, Power Supply Design Seminar, SEM-1400 Topic 2. 3. PowerPAD Thermally Enhanced Package Texas Instruments, Semiconductor Group, Technical Brief: TI Literature No. SLMA002
28
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TPS40050 TPS40051 TPS40053
SLUS540B - DECEMBER 2002 - REVISED MARCH 2003
PWP (R-PDSO-G**)
20 PINS SHOWN
PowerPAD PLASTIC SMALL-OUTLINE
0,65 20
0,30 0,19 11
0,10 M
Thermal Pad (See Note D) 4,50 4,30 6,60 6,20 0,15 NOM
Gage Plane 1 A 10 0-8 0,25 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 PINS ** DIM A MAX A MIN 0,10
14 5,10 4,90
16 5,10 4,90
20 6,60 6,40
24 7,90 7,70
28 9,80 9,60 4073225/F 10/98
NOTES:A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusions. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments Incorporated. 29
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
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