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| Features * * * * * * * * * * * * * * * * * * * * 8-bit Resolution ADC Gain Adjust 1.8 GHz Full Power Input Bandwidth (-3 dB) 1 GSPS (min) Sampling Rate SFDR = 58 dBc, SINAD = 44.3 dB (7.2 Effective Bits), at FS = 1 GSPS, FIN = 20 MHz SFDR = 52 dBc, SINAD = 42.9 dB (7.0 Effective Bits), at FS = 1 GSPS, FIN = 500 MHz SFDR = 50 dBc, SINAD = 40.3 dB (6.8 Effective Bits), at FS = 1 GSPS, FIN = 1000 MHz (-3 dB FS) 2-tone IMD: -52 dBc (489 MHz, 490 MHz) at 1 GSPS DNL = 0.4 lsb, INL = 0.7 lsb Low Bit Error Rate (10-13) at 1 GSPS Very Low Input Capacitance: 3 pF 500 mVpp Differential or Single-ended Analog Inputs Differential or Single-ended 50 ECL Compatible Clock Inputs ECL or LVDS/HSTL Output Compatibility Data Ready Output with Asynchronous Reset Gray or Binary Selectable Output Data; NRZ Output Mode Power Consumption: 3.9W at Tj = 70C Typical Dual Power Supply: 5V Evaluation board: TSEV8388BGL Detailed Specification on Request Demultiplexer: TS81102G0: Companion Device Available ADC 8-bit 1 GSPS TS8388BGL Applications * * * * Digital Sampling Oscilloscopes Satellite Receiver Electronic Countermeasures/Electronic Warfare Direct RF Down-conversion Screening * * Atmel Standard Screening Level Temperature Range: - - C: 0C < Tc; Tj < +90C V: -40C < Tc; Tj < +110C Description The TS8388BGL is a monolithic 8-bit analog-to-digital converter, designed for digitizing wide bandwidth analog signals at very high sampling rates of up to 1 GSPS. The TS8388BGL uses an innovative architecture, including an on-chip Sample and Hold (S/H), and is fabricated with an advanced high-speed bipolar process. The on-chip S/H has a 1.8 GHz full power input bandwidth, providing excellent dynamic performance in undersampling applications (High IF digitizing). Rev. 2145A-BDC-03/02 1 Functional Description Block Diagram The following figure shows the simplified block diagram. Figure 1. Simplified Block Diagram GAIN MASTER/SLAVE TRACK & HOLD AMPLIFIER VIN, VINB G=2 T/H G=1 T/H G=1 RESISTOR CHAIN ANALOG ENCODING BLOCK 4 INTERPOLATION STAGES 4 5 REGENERATION LATCHES 4 5 ERROR CORRECTION & DECODE LOGIC CLOCK BUFFER 8 OUTPUT LATCHES & BUFFERS 8 DRRB DR, DRB GORB DATA, DATAB OR, ORB CLK, CLKB Functional Description The TS8388BGL is an 8-bit 1 GSPS ADC based on an advanced high-speed bipolar technology featuring a cutoff frequency of 25 GHz. The TS8388BGL includes a front-end master/slave Track and Hold stage (S/H), followed by an analog encoding stage and interpolation circuitry. Successive banks of latches regenerate the analog residues into logical data before entering an error correction circuitry and a resynchronization stage followed by 75 differential output buffers. The TS8388BGL works in fully differential mode from analog inputs up to digital outputs. The TS8388BGL features a full-power input bandwidth of 1.8 GHz (-3 dB). A control pin GORB is provided to select either Gray or Binary data output format. A gain control pin is provided in order to adjust the ADC gain. A Data Ready output asynchronous reset (DRRB) is available on TS8388BGL. The TS8388BGL uses only vertical isolated NPN transistors together with oxide isolated polysilicon resistors, which allow enhanced radiation tolerance (no performance drift measured at 150 kRad total dose). 2 TS8388BGL 2145A-BDC-03/02 TS8388BGL Specifications Absolute Maximum Ratings Table 1. Absolute Maximum Ratings Parameter Positive supply voltage Digital negative supply voltage Digital positive supply voltage Negative supply voltage Maximum difference between negative supply voltages Analog input voltages Maximum difference between VIN and VINB Digital input voltage Digital input voltage Digital output voltage Clock input voltage Maximum difference between VCLK and VCLKB Maximum junction temperature Storage temperature Lead temperature (soldering 10s) Note: Symbol VCC DVEE VPLUSD VEE DVEE to VEE VIN or VINB VIN - VINB VD VD VO VCLK or VCLKB VCLK - VCLKB Tj Tstg Tleads GORB DRRB Comments Value GND to 6 GND to -5.7 GND -0.3 to 2.8 GND to -6 0.3 -1 to +1 -2 to +2 -0.3 to VCC +0.3 VEE -0.3 to +0.9 VPLUSD -3 to VPLUSD -0.5 -3 to +1.5 -2 to +2 +135 -65 to +150 +300 Unit V V V V V V V V V V V V C C C Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum rating may affect device reliability. The use of a thermal heat sink is mandatory. See "Typical Characterization Results" on page 14. Recommended Operating Conditions Table 2. Recommended Operating Conditions Recommended Value Parameter Positive supply voltage Positive digital supply voltage Positive digital supply voltage Negative supply voltages Symbol VCC VPLUSD VPLUSD VEE, DVEE ECL output compatibility LVDS output compatibility Comments Min 4.75 - +1.4 -5.25 Typ +5 GND +2.4 -5 Max 5.25 - +2.6 -4.75 Unit V V V V 3 2145A-BDC-03/02 Table 2. Recommended Operating Conditions (Continued) Recommended Value Parameter Differential analog input voltage (Full Scale) Clock input power level Operating temperature range Symbol VIN, VINB VIN - VINB PCLK, PCLKB TJ Comments 50 differential or single-ended 50 single-ended clock input Commercial grade: "C" Industrial grade: "V" Min 113 450 3 Typ 125 500 4 0 < Tc; Tj < 90 -40 < Tc; Tj < 110 Max 137 550 10 Unit mV mVpp dBm C Electrical Operating Characteristics VEE = DVEE = -5V; VCC = +5V; VIN -VINB = 500 mVpp Full Scale differential input; Digital outputs 75 or 50 differentially terminated; Tj (typical) = 70C. Table 3. Electrical Specifications Test Level Value Min Typ Max Unit Note Parameter Power Requirements Positive supply voltage Analog Digital (ECL) Digital (LVDS) Positive supply current Analog Digital Negative supply voltage Negative supply current Analog Digital Nominal power dissipation Power supply rejection ratio Resolution Analog Inputs Full Scale Input Voltage range (differential mode) (0V common mode voltage) Full Scale Input Voltage range (single-ended input option) (See Application Notes) Analog input capacitance Input bias current Input Resistance Symbol VCC VPLUSD VPLUSD ICC IPLUSD VEE AIEE DIEE PD PSRR - 1 4 4 1 1 1 1 1 1 4 - 4.5 - 1.4 - - -5.5 - - - - - 5 0 2.4 420 130 -5 185 160 3.9 0.5 - 5.5 - 2.6 445 145 -4.5 200 180 4.1 2 8 V V V mA mA V mA mA W mW bits (2) VIN VINB VIN VINB CIN IIN RIN 4 - 4 - 4 4 4 -125 -125 -250 - - - 0.5 - - - 0 3 10 1 125 125 250 - 3.5 20 - mV mV mV mV pF A M 4 TS8388BGL 2145A-BDC-03/02 TS8388BGL Table 3. Electrical Specifications (Continued) Test Level 4 4 Value Min - - Typ 1.8 1.7 Max - - Unit GHz GHz Note Parameter Full Power input Bandwidth (-3 dB) Small signal input Bandwidth (10% full scale) Clock Inputs Logic compatibility for clock inputs (See Application Notes) ECL Clock inputs voltages (VCLK or VCLKB): Logic "0" voltage Logic "1" voltage Logic "0" current Logic "1" current Clock input power level into 50 termination Clock input power level Clock input capacitance Symbol FPBW SSBW - - VIL VIH IIL IIH - - CCLK - 4 - - - - - 4 4 ECL or specified clock input power level in dBm - - -1.1 - - - - - 5 5 dBm into 50 -2 - 4 3 10 3.5 - -1.5 - 50 50 - - V V A A - dBm pF (10) Digital Outputs Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format, Tj (typical) = 70C. Full temperature range: 0C < Tc; Tj < +90C. Logic compatibility for digital outputs (Depending on the value of VPLUSD) (See Application Notes) Differential output voltage swings (assuming VPLUSD = 0V): 75 open transmission lines (ECL levels) 75 differentially terminated 50 differentially terminated Output levels (assuming VPLUSD = 0V) 75 open transmission lines: Logic "0" voltage Logic "1" voltage Output levels (assuming VPLUSD = 0V) 75 differentially terminated: Logic "0" voltage Logic "1" voltage Output levels (assuming VPLUSD = 0V) 50 differentially terminated: Logic "0" voltage Logic "1" voltage - - ECL or LVDS - (1)(6) - - - - - VOL VOH - VOL VOH - VOL VOH 4 - - - 4 - - 4 - - - 1, 2 1, 2 - 1.5 0.70 0.54 - - -0.88 - - -1.07 - - -1.16 - 1.620 0.825 0.660 - -1.62 -0.8 - -1.41 -1 - -1.40 -1.10 - - - - - -1.54 - - -1.34 - - -1.32 - - V V V - V V - V V - V V (6) (6) (6) 5 2145A-BDC-03/02 Table 3. Electrical Specifications (Continued) Test Level 4 4 Value Min 270 - Typ 300 - Max - 1.6 Unit mV mV/C Note Parameter Differential Output Swing Output level drift with temperature Symbol DOS - DC Accuracy Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format Tj (typical) = 70C. Differential non linearity Differential non linearity Integral non linearity Integral non linearity No missing codes Gain Input offset voltage Gain error drift Offset error drift Transient Performance Bit Error Rate FS = 1 GSPS, FIN = 62.5 MHz ADC settling time VIN -VINB = 400 mVpp Overvoltage recovery time BER TS TOR 4 4 4 - - - - 0.5 0.5 1E-12 1 1 Error/ sample ns ns (2)(4) DNLDNL+ INLINL+ - - - - - 1 1 1 1 -0.6 - -1.2 - -0.4 0.4 -0.7 0.7 - 0.6 - 1.2 lsb lsb lsb lsb (2)(3) (2)(3) Guaranteed over specified temperature range 1, 2 1, 2 4 4 90 -26 100 40 98 -5 125 50 110 26 150 60 % mV ppm/C ppm/C (3) (2) (2) AC Performance Single-ended or differential input and clock mode, 50% clock duty cycle (CLK, CLKB), Binary output data format, Tj = 70C, unless otherwise specified. Signal to Noise and Distortion ratio FS = 1 GSPS, FIN = 20 MHz FS = 1 GSPS, FIN = 500 MHz FS = 1 GSPS, FIN = 1000 MHz (-1 dBFS) FS = 50 MSPS, FIN = 25 MHz Effective Number Of Bits FS = 1 GSPS, FIN = 20 MHz FS = 1 GSPS, FIN = 500 MHz FS = 1 GSPS, FIN = 1000 MHz (-1 dBFS) FS = 50 MSPS, FIN = 25 MHz SINAD - - - - ENOB - - - - - 4 4 4 1 - 4 4 4 1 - 42 41 38 40 - 7.0 6.6 6.2 7.0 - 44 43 40 44 - 7.2 6.8 6.4 7.2 - - - - - - - - - - - dB dB dB dB - Bits Bits Bits Bits (2) 6 TS8388BGL 2145A-BDC-03/02 TS8388BGL Table 3. Electrical Specifications (Continued) Test Level - 4 4 4 1 - 4 4 4 1 - 4 4 4 4 1 4 - Value Min - 42 41 41 44 - 50 46 42 44 - 52 47 42 45 40 - -47 Typ - 45 44 44 45 - 54 50 46 45 - 57 52 47 50 54 - -52 Max - - - - - - - - - - - - - - - - - - Unit - dB dB dB dB - dB dB dB dB - dBc dBc dBc dBc dBc - dBc (2) (2) (2) Parameter Signal to Noise Ratio FS = 1 GSPS, FIN = 20 MHz FS = 1 GSPS, FIN = 500 MHz FS = 1 GSPS, FIN = 1000 MHz (-1 dBFS) FS = 50 MSPS, FIN = 25 MHz Total Harmonic Distortion FS = 1 GSPS, FIN = 20 MHz FS = 1 GSPS, FIN = 500 MHz FS = 1 GSPS, FIN = 1000 MHz (-1 dBFS) FS = 50 MSPS, FIN = 25 MHz Spurious Free Dynamic Range FS = 1 GSPS, FIN = 20 MHz FS = 1 GSPS, FIN = 500 MHz FS = 1 GSPS, FIN = 1000 MHz (-1 dBFS) FS = 1 GSPS, FIN = 1000 MHz (-3 dBFS) FS = 50 MSPS, FIN = 25 MHz Two-tone Inter-modulation Distortion FIN1 = 489 MHz at FS = 1 GSPS, FIN2 = 490 MHz at FS = 1 GSPS Symbol SNR - - - - THD - - - - SFDR - - - - - IMD - Note (2) Switching Performance and Characteristics - See Figure 2 and Figure 3 on page 9 Maximum clock frequency Minimum clock frequency Minimum Clock pulse width (high) Minimum Clock pulse width (low) Aperture delay Aperture uncertainty Data output delay Output rise/fall time for DATA (20% - 80%) Output rise/fall time for DATA READY (20% - 80%) Data ready output delay Data ready reset delay FS FS TC1 TC2 Ta Jitter TDO TR/TF TR/TF TDR TRDR - 4 4 4 4 4 4 4 4 4 4 1 10 0.280 0.350 100 - 1150 250 250 1110 - - - 0.500 0.500 +250 0.4 1360 350 350 1320 720 1.4 50 50 50 400 0.6 1660 550 550 1620 1000 GSPS MSPS ns ns ps ps (rms) ps ps ps ps ps (2) (2)(5) (2)(10) (11)(12) (11) (14) (15) (11) (2)(10) (11)(12) 7 2145A-BDC-03/02 Table 3. Electrical Specifications (Continued) Test Level 4 4 4 Value Min 0 420 Typ 40 460 4 Max 80 500 Unit ps ps clock cycles Note (9)(13) (14) Parameter Data to data ready - Clock low pulse width (See "Timing Diagrams" on page 9.) Data to data ready output delay (50% duty cycle) at 1 GSPS (See "Timing Diagrams" on page 9.) Data pipeline delay Notes: 1. 2. 3. 4. 5. Symbol TOD-TDR TD1 TPD (2)(15) Differential output buffers are internally loaded by 75 resistors. Buffer bias current = 11 mA. See "Definition of Terms" on page 40. Histogram testing based on sampling of a 10 MHz sinewave at 50 MSPS. Output error amplitude < 4 lsb around worst code. Maximum jitter value obtained for single-ended clock input on the JTS8388B die (chip on board): 200 fs. (500 fs expected on TS8388BGL) 6. Digital output back termination options depicted in Application Notes. 7. With a typical value of TD = 465 ps, at 1 GSPS, the timing safety margin for the data storing using the ECLinPS 10E452 output registers from Motorola(R) is of 315 ps, equally shared before and after the rising edge of the Data Ready signals (DR, DRB). 8. The clock inputs may be indifferently entered in differential or single-ended, using ECL levels or 4 dBm typical power level into the 50 termination resistor of the inphase clock input. (4 dBm into 50 clock input correspond to 10 dBm power level for the clock generator.) 9. At 1 GSPS, 50/50 clock duty cycle, TC2 = 500 ps (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate. 10. Specifiedloadingconditionsfordigitaloutputs: -50 or 75 controlled impedance traces properly 50/75 terminated, or unterminated 75 controlled impedance traces. - Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola. (i.e.: 10E452) (Typical input parasitic capacitance of 1.5 pF including package and ESD protections.) 11. Terminationloadparasiticcapacitancederatingvalues: -50 or 75 controlled impedance traces properly 50/75 terminated: 60 ps/pF or 75 ps per additionnal ECLinPS load. - Unterminated (source terminated) 75 controlled impedance lines: 100 ps/pF or 150 ps per additionnal ECLinPS termination load. 12. Apply proper 50/75 impedance traces propagation time derating values: 6 ps/mm (155 ps/inch) for TSEV8388BGL Evaluation Board. 13. Values for TOD and TDR track each other over temperature, (1% variation for TOD-TDR per 100C temperature variation). Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between each Data TODs and TDR effect can be considered as negligible. Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes about "TOD-TDR Variation Over Temperature" on page 23). 14. Min value guarantees performance. Max value guarantees functionality. 15. Min value guarantees functionality. Max value guarantees performance. 8 TS8388BGL 2145A-BDC-03/02 TS8388BGL Timing Diagrams Figure 2. TS8388BGL Timing Diagram (1 GSPS Clock Rate), Data Ready Reset, Clock Held at LOW Level TA = 250 ps X (VIN, VINB) X N-1 N X N+1 TC = 1000 ps TC1 TC2 X N+2 X N+3 X N+4 X N+5 (CLK, CLKB) 1360 ps TPD: 4.0 Clock periods TOD = 1360 ps DIGITAL OUTPUTS 1000 ps DATA N-5 DATA N-4 TDR = 1320 ps DATA N-3 DATA N-2 DATA N-1 DATA N DATA N+1 TDR = 1320 ps TD1 = TC1+TDR-TOD = TC1-40 ps = 460 ps Data Ready (DR, DRB) TD2 = TC2+TOD-TDR = TC2+40 ps = 540 ps TRDR = 720 ps DRRB 1 ns (min) Figure 3. TS8388BGL Timing Diagram (1 GSPS Clock Rate), Data Ready Reset, Clock Held at HIGH Level TA = 250 ps X (VIN, VINB) X X N+2 X N+3 N+4 X X N+5 XN-1 N N+1 TC = 1000 ps TC1 TC2 (CLK, CLKB) 1360 ps TPD: 4.0 Clock periods TOD = 1360 ps DIGITAL OUTPUTS 1000 ps DATA N-5 DATA N-4 TDR = 1320 ps DATA N-3 DATA N-2 DATA N-1 DATA N DATA N+1 TDR = 1320 ps TD1 = TC1+TDR-TOD = TC1-40 ps = 460 ps Data Ready (DR, DRB) TD2 = TC2+TOD-TDR = TC2+40 ps = 540 ps TRDR = 720 ps DRRB 1 ns (min) 9 2145A-BDC-03/02 Explanation of Test Levels Table 4. Explanation of Test Levels Num 1 2 3 4 5 6 Notes: Characteristics 100% production tested at +25C(1) (for "C" Temperature range(2)). 100% production tested at +25C(1), and sample tested at specified temperatures (for "V" Temperature range(2)). Sample tested only at specified temperatures. Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified temperature). Parameter is a typical value only. 100% production tested over specified temperature range (for "B/Q" Temperature range(2)). 1. Unless otherwise specified, all tests are pulsed tests: therefore Tc = Ta, where Tc and Ta are case and ambient temperature. 2. Refer to "Ordering Information" on page 42. 3. Only MIN and MAX values are guaranteed (typical values are issuing from characterization results). Functions Description Table 5. Functions Description Name VCC VEE VPLUSD GND VIN, VINB CLK, CLKB CLK VIN VINB OR ORB VCC = +5V VPLUSD = +0V (ECL) VPLUSD = +2.4V (LVDS) Differential output data port Differential data ready outputs Out of range outputs ADC gain adjust Gray or Binary digital output select Die junction temperature measurement/ asynchronous data ready reset CLKB GAIN GORG DIOD/ DRRB TS8388BGL D0 16 D0B DR DRB D7 D7B DVEE = -5V VEE = -5V GND 10 TS8388BGL 2145A-BDC-03/02 TS8388BGL Digital Output Coding NRZ (Non Return to Zero) mode, ideal coding: does not include gain, offset, and linearity voltage errors. Table 6. Digital Output Coding Digital Output Differential Analog Input > +251 mV +251 mV +249 mV +126 mV +124 mV +1 mV -1 mV -124 mV -126 mV -249 mV -251 mV < -251 mV Voltage Level > Positive full scale + 1/2 lsb Positive full scale + 1/2 lsb Positive full scale - 1/2 lsb Positive 1/2 scale + 1/2 lsb Positive 1/2 scale - 1/2 lsb Bipolar zero + 1/2 lsb Bipolar zero - 1/2 lsb Negative 1/2 scale + 1/2 lsb Negative 1/2 scale - 1/2 lsb Negative full scale + 1/2 lsb Negative full scale - 1/2 lsb < Negative full scale - 1/2 lsb Binary GORB = VCC or Floating 11111111 11111111 11111110 11000000 10111111 10000000 01111111 01000000 00111111 00000001 00000000 00000000 Gray GORB = GND 10000000 10000000 10000001 10100000 11100000 11000000 01000000 01100000 00100000 00000001 00000000 00000000 Out of Range 1 0 0 0 0 0 0 0 0 0 0 1 11 2145A-BDC-03/02 Package Description Pin Description Table 7. TS8388BGL Pin Description Symbol GND VCC VEE DVEE VIN VINB CLK CLKB B0, B1, B2, B3, B4, B5, B6, B7 B0B, B1B, B2B, B3B, B4B, B5B, B6B, B7B OR ORB DR DRB GORB Pin number A2, A5, B1, B5, B10, C2, D2, E1, E2, E11, F1, F2, G11, K2, K3, K4, K5, K10, L2, L5 A4, A6, B2, B4, B6, H1, H2, L6, L7 A3, B3, G1, G2, J1, J2 F10, F11 L3 L4 C1 D1 A8, A9, A10, D10, H11, J11, K9, K8 B7, B8, B9, C11, G10, H10, L10, L9 K7 L8 E10 D11 A7 Function Ground pins. To be connected to external ground plane. +5V positive supply. 5V analog negative supply. -5V digital negative supply. In phase (+) analog input signal of the Sample and Hold differential preamplifier. Inverted phase (-) of ECL clock input signal (CLK). In phase (+) ECL clock input signal. The analog input is sampled and held on the rising edge of the CLK signal. Inverted phase (-) of ECL clock input signal (CLK). In phase (+) digital outputs. B0 is the LSB. B7 is the MSB. Inverted phase (-) digital outputs. B0B is the inverted LSB. B7B is the inverted MSB. In phase (+) Out of Range Bit. Out of Range is high on the leading edge of code 0 and code 256. Inverted phase (+) Out of Range Bit (OR). In phase (+) output of Data Ready Signal. Inverted phase (-) output of Data Ready Signal (DR). Gray or Binary select output format control pin. - Binary output format if GORB is floating or VCC. - Gray output format if GORB is connected at ground (0V). ADC gain adjust pin. The gain pin is by default grounded, the ADC gain transfer fuction is nominally close to one. Die function temperature measurement pin and asynchronous data ready reset active low, single-ended ECL input. +2.4V for LVDS output levels otherwise to GND(1). Not connected. GAIN DIOD/DRRB K6 K1 VPLUSD NC Note: B11, C10, J10, K11 A1, A11, L1, L11 1. The common mode level of the output buffers is 1.2V below the positive digital supply. For ECL compatibility the positive digital supply must be set at 0V (ground). For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V. If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive digital supply level in the same proportion in order to spare power dissipation. 12 TS8388BGL 2145A-BDC-03/02 TS8388BGL TS8388BGL Pinout Figure 4. TS8388BGL Pinout of CBGA 72 Package 11 NC VPLUSD B3b DRb GND DVEE GND B4 B5 VPLUSD NC 10 B2 GND VPLUSD B3 DR DVEE B4b B5b VPLUSD GND B6b 9 B1 B2b B6 B7b 8 B0 B1b B7 ORb 7 Gorb B0b OR VCC 6 VCC VCC GAIN VCC 5 GND GND GND GND 4 VCC VCC GND VINB 3 VEE VEE GND VIN 2 GND VCC GND GND GND GND VEE VCC VEE GND GND 1 Ball A1 Index other side NC GND CLK CLKB GND GND VEE VCC VEE Diode NC A B C D E F G H J K L BOTTOM VIEW 13 2145A-BDC-03/02 Typical Characterization Results Static Linearity FS = 50 MSPS/FIN = 10 MHz Figure 5. Integral Non Linearity Note: Clock Frequency = 50 MSPS; Signal Frequency = 10 MHz; Positive peak: 0.78 lsb; Negative peak: -0.73 lsb Figure 6. Differential Non Linearity Note: Clock Frequency = 50 MSPS; Signal Frequency = 10 MHz; Positive peak: 0.3 lsb; Negative peak: -0.39 lsb 14 TS8388BGL 2145A-BDC-03/02 TS8388BGL Effective Number of Bits Versus Power Supplies Variation Figure 7. Effective Number of Bits = f (VEEA); FS = 500 MSPS; FIN = 100 MHz 8 7 6 ENOB (bits) 5 4 3 2 1 0 -7 -6.5 -6 -5.5 VEEA (V) -5 -4.5 -4 Figure 8. Effective Number of Bits = f (VCC); FS = 500 MSPS; FIN = 100 MHz 8 7 6 ENOB (bits) 5 4 3 2 1 0 3 3.5 4 4.5 5 VCC (V) 5.5 6 6.5 7 Figure 9. Effective Number of Bits = f (VEED); FS = 500 MSPS; FIN = 100 MHz 8 7 6 ENOB (bits) 5 4 3 2 1 0 -6 -5.5 -5 -4.5 VEED (V) -4 -3.5 -3 15 2145A-BDC-03/02 Typical FFT Results Figure 10. FS = 1 GSPS; FIN = 20 MHz Figure 11. FS = 1 GSPS; FIN = 495 MHz Figure 12. FS = 1 GSPS; FIN = 995 MHz (-3 dB Full Scale Input) 16 TS8388BGL 2145A-BDC-03/02 TS8388BGL Spurious Free Dynamic Range Versus Input Amplitude Figure 13. Sampling Frequency: FS = 1 GSPS; Input Frequency FIN = 995 MHz; Full Scale; ENOB = 6.4; SINAD = 40 dB; SNR = 44 dB; THD = -46 dBc; SFDR = -47 dBc; Gray or Binary Output Coding Figure 14. Sampling Frequency: FS = 1 GSPS; Input Frequency FIN = 995 MHz; -3 dB Full Scale; ENOB = 6.6; SINAD = 40.8 dB; SNR = 44 dB; THD = -48 dBc; SFDR = -50 dBc; Gray or Binary Output Coding 17 2145A-BDC-03/02 Dynamic Performance Versus Analog Input Frequency Figure 15. ENOB (dB) 8 FS = 1 GSPS, FIN = 0 up to 1600 MHz, Full Scale input (FS), FS -3 dB Clock duty cycle 50/50, Binary/Gray output coding, fully differential or single-ended analog and clock inputs. 7 ENOB (dB) -3 dB FS 6 5 FS 4 3 0 200 400 600 800 1000 1200 1400 1600 1800 Input frequency (MHz) Figure 16. SNR (dB) 50 48 46 44 SNR (dB) 42 40 38 36 34 32 30 0 200 400 600 800 1000 1200 1400 1600 1800 Input frequency (MHz) FS -3 dB FS Figure 17. SFDR (dBc) -20 -25 -30 SFDR (dBc) -35 -40 -45 -50 -55 -60 0 200 400 600 800 1000 1200 1400 1600 1800 Input frequency (MHz) -3 dB FS FS 18 TS8388BGL 2145A-BDC-03/02 TS8388BGL Effective Number of Bits (ENOB) Versus Sampling Frequency Figure 18. ENOB (dB) 8 FIN = FS/2 7 FIN = 500 MHz 6 ENOB (dB) Analog Input Frequency: FIN = 495 MHz and Nyquist conditions (FIN = FS/2) Clock duty cycle 50/50, Binary output coding 5 4 3 2 0 200 400 600 800 1000 1200 1400 1600 Sampling frequency (MSPS) SFDR Versus Sampling Frequency Figure 19. SFDR (dBc) -20 -25 -30 -35 SFDR (dBc) -40 -45 Analog Input Frequency: FIN = 495 MHz and Nyquist conditions (FIN = FS/2) Clock duty cycle 50/50, Binary output coding FIN = FS/2 -50 FIN = 500 MHz -55 -60 0 200 400 600 800 1000 1200 1400 1600 Sampling frequency (MSPS) 19 2145A-BDC-03/02 TS8388BGL ADC Performances Versus Junction Temperature Figure 20. Effective Number of Bits Versus Junction Temperature FS = 1 GSPS; FIN = 500 MHz; Duty Cycle = 50% 8 7 ENOB (bits) 6 5 4 3 -40 -20 0 20 40 60 80 Temperature (C) 100 120 140 160 Figure 21. Signal to Noise Ratio Versus Junction Temperature FS = 1 GSPS; FIN = 507 MHz; Differential Clock; Single-ended Analog Input (VIN = -1 dBFs) 46 45 SNR (dB) 44 43 42 -60 -40 -20 0 20 40 Temperature (C) 60 80 100 120 Figure 22. Total Harmonic Distorsion Versus Junction Temperature FS = 1 GSPS; FIN = 507 MHz; Differential Clock; Single-ended Analog Input (VIN = -1 dBFs) 53 51 THD (dB) 49 47 45 43 -60 -40 -20 0 20 40 Temperature (C) 60 80 100 120 20 TS8388BGL 2145A-BDC-03/02 TS8388BGL Figure 23. Power Consumption Versus Junction Temperature FS = 1 GSPS; FIN = 500 MHz; Duty Cycle = 50% 5 Power consumption (W) 4 3 2 1 0 -40 -20 0 20 40 60 80 100 120 140 160 Temperature (C) Typical Full Power Input Bandwidth Figure 24. 1.8 GHz at -3 dB (-2 dBm Full Power Input) Frequency (MHz) 400 0 600 800 1000 1200 1400 1600 1800 2000 -1 Magnitude (dB) -2 -3 -4 -5 -6 21 2145A-BDC-03/02 ADC Step Response Test pulse input characteristics: 20% to 80% input full scale and rise time ~ 200 ps. Note: This step response was obtained with the TSEV8388B chip on-board (device in die form). Figure 25. Test Pulse Digitized with 20 GHz DSO Vpp ~ 260 mV Tr ~ 240 ps 50 mV/div 500 ps/div 0 0.5 1.0 1.5 2.0 2.5 Time (ns) 3.0 3.5 4.0 4.5 5.0 Figure 26. Same Test Pulse Digitized with TS8388BGL ADC 200 150 ADC code Tr ~ 280 ps 100 50 codes/div (Vpp ~ 260 mV) 500 ps/div ADC calculated rise time: between 150 and 200 ps 50 0 0 0.5 1.0 1.5 2.0 2.5 Time (ns) 3.0 3.5 4.0 4.5 5.0 Note: Ripples are due to the test setup (they are present on both measurements). 22 TS8388BGL 2145A-BDC-03/02 TS8388BGL TS8388BGL Main Features Timing Information Timing Value for TS8388BGL Timing values as defined in Table 3 on page 4 are advanced data, issued from electric simulations and first characterizations results fitted with measurements. Timing values are given at CBGA72 package inputs/outputs, taking into account package internal controlled impedance traces propagation delays, and specified termination loads. Propagation delays in 50/75 impedance traces are NOT taken into account for TOD and TDR. Apply proper derating values corresponding to termination topology. The min/max timing values are valid over the full temperature range in the following conditions: * Specified Termination Load (Differential output Data and Data Ready): 50 resistor in parallel with 1 standard ECLinPS register from Motorola (i.e.: 10E452) Typical ECLinPS inputs shows a typical input capacitance of 1.5 pF (including package and ESD protections). If addressing an output Dmux, take care if some Digital outputs do not have the same termination load and apply corresponding derating value given below. Output Termination Load derating values for TOD and TDR: ~ 35 ps/pF or 50 ps per additional ECLinPS load. Propagation time delay derating values have also to be applied for TOD and TDR: ~ 6 ps/mm (155 ps/inch) for TSEV8388B Evaluation Board. Apply proper time delay derating value if a different dielectric layer is used. * * Propagation Time Considerations TOD and TDR Timing values are given from pin to pin and DO NOT include the additional propagation times between device pins and input/output termination loads. For the TSEV8388B Evaluation Board, the propagation time delay is 6 ps/mm (155 ps/inch) corresponding to 3.4 (at 10 GHz) dielectric constant of the RO4003 used for the Board. If a different dielectric layer is used (for instance Teflon), please use appropriate propagation time values. TD does NOT depend on propagation times because it is a differential data (TD is the time difference between Data Ready output delay and digital Data output delay). TD is also the most straightforward data to measure, again because it is differential: TD can be measured directly onto termination loads, with matched Oscilloscopes probes. TOD-TDR Variation Over Temperature Values for TOD and TDR track each other over temperature (1% variation for TOD-TDR per 100C temperature variation). Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between each Data TODs and TDR effect can be considered as negligible. Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values. 23 2145A-BDC-03/02 In other terms: - - If TOD is at 1150 ps, TDR will not be at 1620 ps (maximum time delay for TDR). If TOD is at 1660 ps, TDR will not be at 1110 ps (minimum time delay for TDR). However, external TOD-TDR values may be dictated by total digital datas skews between every TODs (each digital data) and TDR: MCM Board, bonding wires and output lines lengths differences, and output termination impedance mismatches. The external (on board) skew effect has NOT been taken into account for the specification of the minimum and maximum values for TOD-TDR. Principle of Operation The Analog input is sampled on the rising edge of external clock input (CLK, CLKB) after TA (aperture delay) of typically 250 ps. The digitized data is available after 4 clock periods latency (pipeline delay (TPD)), on clock rising edge, after 1360 ps typical propagation delay TOD. The Data Ready differential output signal frequency (DR, DRB) is half the external clock frequency, that is it switches at the same rate as the digital outputs. The Data Ready output signal (DR, DRB) switches on external clock falling edge after a propagation delay TDR of typically 1320 ps. A Master Asynchronous Reset input command DRRB (ECL compatible single-ended input) is available for initializing the differential Data Ready output signal (DR, DRB). This feature is mandatory in certain applications using interleaved ADCs or using a single ADC with demultiplexed outputs. Actually, without Data Ready signal initialization, it is impossible to store the output digital datas in a defined order. Principle of Data Ready Signal Control by DRRB Input Command Data Ready Output Signal Reset The Data Ready signal is reset on falling edge of DRRB input command, on ECL logical low level (-1.8V). DRRB may also be tied to VEE = -5V for Data Ready output signal Master Reset. So long DRRB remains at logical low level, (or tied to VEE = -5V), the Data Ready output remains at logical zero and is independant of the external free running encoding clock. The Data Ready output signal (DR, DRB) is reset to logical zero after TRDR = 920 ps typical. TRDR is measured between the -1.3V point of the falling edge of DRRB input command and the zero crossing point of the differential Data Ready output signal (DR, DRB). The Data Ready Reset command may be a pulse of 1 ns minimum time width. 24 TS8388BGL 2145A-BDC-03/02 TS8388BGL Data Ready Output Signal Restart The Data Ready output signal restarts on DRRB command rising edge, ECL logical high levels (-0.8V). DRRB may also be Grounded, or is allowed to float, for normal free running Data Ready output signal. The Data Ready signal restart sequence depends on the logical level of the external encoding clock, at DRRB rising edge instant: * The DRRB rising edge occurs when external encoding clock input (CLK, CLKB) is LOW: The Data Ready output first rising edge occurs after half a clock period on the clock falling edge, after a delay time TDR = 1320 ps already defined hereabove. The DRRB rising edge occurs when external encoding clock input (CLK, CLKB) is HIGH: The Data Ready output first rising edge occurs after one clock period on the clock falling edge, and a delay TDR = 1320 ps. * Consequently, as the analog input is sampled on clock rising edge, the first digitized data corresponding to the first acquisition (N) after Data Ready signal restart (rising edge) is always strobed by the third rising edge of the data ready signal. The time delay (TD1) is specified between the last point of a change in the differential output data (zero crossing point) to the rising or falling edge of the differential Data Ready signal (DR, DRB) (zero crossing point). For normal initialization of Data Ready output signal, the external encoding clock signal frequency and level must be controlled. It is reminded that the minimum encoding clock sampling rate for the ADC is 10 MSPS and consequently the clock cannot be stopped. One single pin is used for both DRRB input command and die junction temperature monitoring. Pin denomination will be DRRB/DIOD. On the former version denomination was DIOD. Temperature monitoring and Data Ready control by DRRB is not possible simultaneously. Analog Inputs (VIN) (VINB) The analog input Full Scale range is 0.5V peak to peak (Vpp), or -2 dBm into the 50 termination resistor. In differential mode input configuration, that means 0.25V on each input, or 125 mV around 0V. The input common mode is GROUND. The typical input capacitance is 3 pF for TS8388BGL in CQFP package. The input capacitance is mainly due to the package. The ESD protections are not connected (but present) on the inputs. Differential Inputs Voltage Span Figure 27. Differential Inputs Voltage Span [mV] 125 500 mV Full Scale analog input 250 mV VIN VINB -250 mV 0V -125 (VIN, VINB) = 250 mV = 500 mV diff t 25 2145A-BDC-03/02 Differential Versus Single-ended Analog Input Operation The TS8388BGL can operate at full speed in either differential or single-ended configuration. This is explained by the fact the ADC uses a high input impedance differential preamplifier stage, (preceeding the Sample and hold stage), which has been designed in order to be entered either in differential mode or single-ended mode. This is true so long as the out-of-phase analog input pin VINB is 50 terminated very closely to one of the neighboring shield ground pins (52, 53, 58, 59) which constitute the local ground reference for the inphase analog input pin (VIN). Thus the differential analog input preamplifier will fully reject the local ground noise (and any capacitively and inductively coupled noise) as common mode effects. In typical single-ended configuration, enter on the (VIN) input pin, with the inverted phase input pin (VINB) grounded through the 50 termination resistor. In single-ended input configuration, the in-phase input amplitude is 0.5V peak to peak, centered on 0V (or -2 dBm into 50). The inverted phase input is at ground potential through the 50 termination resistor. However, dynamic performances can be somewhat improved by entering either analog or clock inputs in differential mode. Typical Single-ended Analog Input Configuration Figure 28. Typical Single-ended Analog Input Configuration [mV] 250 500 mV Full Scale analog input 500 mV VINB t VIN = 250 mV = 500 mV diff 50 reverse termination VIN VIN or VINB double pad (pins 54, 55 or 56, 57) VIN or VINB VINB = 0V 50 (on package) 1 M 3 pF -250 Clock Inputs (CLK) (CLKB) The TS8388BGL can be clocked at full speed without noticeable performance degradation in either differential or single-ended configuration. This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer, which has been designed in order to be entered either in differential or single-ended mode. Recommended sinewave generator characteristics are typically -120 dBc/Hz phase noise floor spectral density, at 1 kHz from carrier, assuming a single tone 4 dBm input for the clock signal. Single-ended Clock Input (Ground Common Mode) Although the clock inputs were intended to be driven differentially with nominal -0.8V/-1.8V ECL levels, the TS8388BGL clock buffer can manage a single-ended sinewave clock signal centered around 0V. This is the most convenient clock input configuration as it does not require the use of a power splitter. No performance degradation (i.e.: due to timing jitter) is observed in this particular singleended configuration up to 1.2 GSPS Nyquist conditions (FIN = 600 MHz). 26 TS8388BGL 2145A-BDC-03/02 TS8388BGL This is true so long as the inverted phase clock input pin is 50 terminated very closely to one of the neighboring shield ground pins, which constitutes the local Ground reference for the inphase clock input. Thus the TS8388BGL differential clock input buffer will fully reject the local ground noise (and any capacitively and inductively coupled noise) as common mode effects. Moreover, a very low phase noise sinewave generator must be used for enhanced jitter performance. The typical inphase clock input amplitude is 1V peak to peak, centered on 0V (ground) common mode. This corresponds to a typical clock input power level of 4 dBm into the 50 termination resistor. Do not exceed 10 dBm to avoid saturation of the preamplifier input transistors. The inverted phase clock input is grounded through the 50 termination resistor. Figure 29. Single-ended Clock Input (Ground Common Mode): VCLK common mode = 0V; VCLKB = 0V; 4 dBm typical clock input power level (into 50 termination resistor) [V] +0.5V VCLK CLK or CLKB double pad (pins 37, 38 or 39, 40) CLK or CLKB 1 M VCLK = 0V VCLK -0.5V t 50 (on package) 0.4 pF 50 reverse termination Note: Do not exceed 10 dBm into the 50 termination resistor for single clock input power level. Differential ECL Clock Input The clock inputs can be driven differentially with nominal -0.8V/-1.8V ECL levels. In this mode, a low phase noise sinewave generator can be used to drive the clock inputs, followed by a power splitter (hybrid junction) in order to obtain 180 degrees out of phase sinewave signals. Biasing tees can be used for offseting the common mode voltage to ECL levels. Note: As the biasing tees propagation times are not matching, a tunable delay line is required in order to ensure the signals to be 180 degrees out of phase especially at fast clock rates in the GSPS range. Figure 30. Differential Clock Inputs (ECL Levels) [mV] -0.8V VCLK VCLKB CLK or CLKB double pad (pins 37, 38 or 39, 40) CLK or CLKB 1 M Common mode = -1.3V 50 (on package) -2V 0.4 pF -1.8V t 50 reverse termination 27 2145A-BDC-03/02 Single-ended ECL Clock Input In single-ended configuration enter on CLK (resp. CLKB) pin, with the inverted phase Clock input pin CLKB (respectively CLK) connected to -1.3V through the 50 termination resistor. The inphase input amplitude is 1V peak to peak, centered on -1.3V common mode. Figure 31. Single-ended Clock Input (ECL): VCLK common mode = -1.3V; VCLKB = -1.3V [V] -0.8V VCLK VCLKB = -1.3V -1.8V t Noise Immunity Information Circuit noise immunity performance begins at design level. Efforts have been made on the design in order to make the device as insensitive as possible to chip environment perturbations resulting from the circuit itself or induced by external circuitry (Cascode stages isolation, internal damping resistors, clamps, internal (on-chip) decoupling capacitors). Furthermore, the fully differential operation from analog input up to the digital outputs provides enhanced noise immunity by common mode noise rejection. Common mode noise voltage induced on the differential analog and clock inputs will be canceled out by these balanced differential amplifiers. Moreover, proper active signals shielding has been provided on the chip to reduce the amount of coupled noise on the active inputs. The analog inputs and clock inputs of the TS8388BGL device have been surrounded by ground pins, which must be directly connected to the external ground plane. Digital Outputs The TS8388BGL differential output buffers are internally 75 loaded. The 75 resistors are connected to the digital ground pins through a -0.8V level shift diode (see Figure 32, Figure 33, Figure 34 on page 30). The TS8388BGL output buffers are designed for driving 75 (default) or 50 properly terminated impedance lines or coaxial cables. An 11 mA bias current flowing alternately into one of the 75 resistors when switching ensures a 0.825V voltage drop across the resistor (unterminated outputs). The VPLUSD positive supply voltage allows the adjustment of the output common mode level from -1.2V (VPLUSD = 0V for ECL output compatibility) to +1.2V (VPLUSD = 2.4V for LVDS output compatibility). Therefore, the single-ended output voltages vary approximately between -0.8V and -1.625V, (outputs unterminated), around -1.2V common mode voltage. 28 TS8388BGL 2145A-BDC-03/02 TS8388BGL Three possible line driving and back-termination scenarios are proposed (assuming VPLUSD = 0V): 1. 75 impedance transmission lines, 75 differentially terminated (Figure 32): Each output voltage varies between -1V and -1.42V (respectively +1.4V and +1V), leading to 0.41V = 0.825V in differential, around -1.21V (respectively +1.21V) common mode for VPLUSD = 0V (respectively 2.4V). 2. 50 impedance transmission lines, 50 differentially termination (Figure 33): Each output voltage varies between -1.02V and -1.35V (respectively +1.38V and +1.05V), leading to 0.33V = 660 mV in differential, around -1.18V (respectively +1.21V) common mode for VPLUSD = 0V (respectively 2.4V). 3. 75 impedance open transmission lines (Figure 34): Each output voltage varies between -1.6V and -0.8V (respectively +0.8V and +1.6V), which are true ECL levels, leading to 0.8V = 1.6V in differential, around -1.2V (respectively +1.2V) common mode for VPLUSD = 0V (respectively 2.4V). Therefore, it is possible to drive directly high input impedance storing registers, without terminating the 75 transmission lines. In time domain, that means that the incident wave will reflect at the 75 transmission line output and travel back to the generator (i.e.: the 75 data output buffer). As the buffer output impedance is 75, no back reflection will occur. Note: This is no longer true if a 50 transmission line is used, as the latter is not matching the buffer 75 output impedance. Each differential output termination length must be kept identical. It is recommended to decouple the midpoint of the differential termination with a 10 nF capacitor to avoid common mode perturbation in case of slight mismatch in the differential output line lengths. Too large mismatches (keep < a few mm) in the differential line lengths will lead to switching currents flowing into the decoupling capacitor leading to switching ground noise. The differential output voltage levels (75 or 50 termination) are not ECL standard voltage levels, however it is possible to drive standard logic ECL circuitry like the ECLinPS logic line from Motorola(R). At sampling rates exceeding 1 GSPS, it may be difficult to trigger the HP16500 or any other Acquisition System with digital outputs. It becomes necessary to regenerate digital data and Data Ready by means of external amplifiers, in order to be able to test the TS8388BGL at its optimum performance conditions. 29 2145A-BDC-03/02 Differential Output Loading Configurations (Levels for ECL Compatibility) Figure 32. Differential Output: 75 Terminated VPLUSD = 0V -0.8V Out 75 75 75 75 -1V/-1.41V Differential output: +0.41V = 0.825V Common mode level: -1.2V (-1.2V below VPLUSD level) - + 75 impedance 10 nF 75 OutB 11 mA DVEE -1.41V/-1V Figure 33. Differential Output: 50 Terminated VPLUSD = 0V -0.8V Out 75 75 50 50 -1.02V/-1.35V Differential output: +0.33V = 0.660V Common mode level: -1.2V (-1.2V below VPLUSD level) - + 50 impedance 10 nF 50 OutB 11 mA DVEE -1.35V/-1.02V Figure 34. Differential Output: Open Loaded VPLUSD = 0V -0.8V Out 75 75 75 -0.8V/-1.6V Differential output: +0.8V = 1.6V Common mode level: -1.2V (-1.2V below VPLUSD level) - + 75 impedance OutB 11 mA DVEE -1.6V/-0.8V 30 TS8388BGL 2145A-BDC-03/02 TS8388BGL Differential Output Loading Configurations (Levels for LVDS Compatibility) Figure 35. Differential Output: 75 Terminated VPLUSD = 2.4V 1.6V Out 75 75 75 75 1.4V/0.99V Differential output: +0.41V = 0.825V Common mode level: -1.2V (-1.2V below VPLUSD level) - + 75 impedance 10 nF 75 OutB 11 mA DVEE 0.99V/1.4V Figure 36. Differential Output: 50 Terminated VPLUSD = 2.4V 1.6V Out 75 75 50 50 1.38V/1.05V Differential output: +0.33V = 0.660V Common mode level: -1.2V (-1.2V below VPLUSD level) - + 50 impedance 10 nF 50 OutB 11 mA DVEE 1.05V/1.38V Figure 37. Differential Output: Open Loaded VPLUSD = 2.4V 1.6V Out 75 75 75 1.6V/0.8V Differential output: +0.8V = 1.6V Common mode level: -1.2V (-1.2V below VPLUSD level) - + 75 impedance OutB 11 mA DVEE 0.8V/1.6V 31 2145A-BDC-03/02 Out of Range Bit An Out of Range (OR, ORB) bit is provided that goes to logical high state when the input exceeds the positive full scale or falls below the negative full scale. When the analog input exceeds the positive full scale, the digital output datas remain at high logical state, with (OR, ORB) at logical one. When the analog input falls below the negative full scale, the digital outputs remain at logical low state, with (OR, ORB) at logical one again. Gray or Binary Output Data Format Select The TS8388BGL internal regeneration latches indecision (for inputs very close to latches threshold) may produce errors in the logic encoding circuitry and leading to large amplitude output errors. This is due to the fact that the latches are regenerating the internal analog residues into logical states with a finite voltage gain value (Av) within a given positive amount of time (t): Av = exp((t)/), with the positive feedback regeneration time constant. The TS8388BGL has been designed for reducing the probability of occurrence of such errors to approximately 10-13 (targeted for the TS8388BGL at 1 GSPS). A standard technique for reducing the amplitude of such errors down to 1 lsb consists of outputting the digital datas in Gray code format. Though the TS8388BGL has been designed for featuring a Bit Error Rate of 10-13 with a binary output format, it is possible for the user to select between the Binary or Gray output data format, in order to reduce the amplitude of such errors when occurring, by storing Gray output codes. Digital Datas format selection: * * BINARY output format if GORB is floating or VCC. GRAY output format if GORB is connected to ground (0V). Diode Pin K1 One single pin is used for both DRRB input command and die junction monitoring. The pin denomination is DRRB/DIOD. Temperature monitoring and Data Ready control by DRRB is not possible simultaneously. (See "Principle of Data Ready Signal Control by DRRB Input Command" on page 24 for Data Ready Reset input command). The operating die junction temperature must be kept below 145C, therefore an adequate cooling system has to be set up. The diode mounted transistor measured Vbe value versus junction temperature is given below. Figure 38. Diode Pin K1 1000 960 920 880 VBE (mV) 840 800 760 720 680 640 600 -55 -35 -15 5 25 45 65 Junction temperature (C) 85 105 125 32 TS8388BGL 2145A-BDC-03/02 TS8388BGL ADC Gain Control Pin K6 The ADC gain is adjustable by the means of the pin K6 (input impedance is 1 M in parallel with 2 pF). The gain adjust transfer function is given below. Figure 39. ADC Gain Control Pin K6 1.20 1.15 1.10 ADC Gain 1.05 1.00 0.95 0.90 0.85 0.80 -500 -400 -300 -200 -100 0 100 200 300 400 500 Vgain (command voltage) (mV) Note: For more information, please refer to the document "DEMUX and ADCs Application Notes". 33 2145A-BDC-03/02 Equivalent Input/Output Schematics Figure 40. Equivalent Analog Input Circuit and ESD Protections VCC = +5V VCLAMP = +2.4V -0.8V -0.8V VCC GND -5.8V -5.8V GND = 0V +1.65V 50 E21V E21V 50 VEE 200 200 VEE VINB Pad capacitance 340 fF 5.8V VIN Pad capacitance 340 fF -1.55V 5.8V 0.8V 0.8V E21G VEE = -5V E21G Note: The ESD protection equivalent capacitance is 150 fF. Figure 41. Equivalent Analog Clock Input Circuit and ESD Protections VCC = +5V +0.8V -5.8V -0.8V VCC -5.8V -5.8V GND = 0V -5.8V -5.8V E31V 150 150 VEE CLK Pad capacitance 340 fF E31V VEE CLKB Pad capacitance 340 fF 5.8V 5.8V 380 A 0.8V 0.8V E21G VEE = -5V E21G Note: The ESD protection equivalent capacitance is 150 fF. 34 TS8388BGL 2145A-BDC-03/02 TS8388BGL Figure 42. Equivalent Data Output Buffer Circuit and ESD Protections VPLUSD = 0V to 2.4V -5.8V -5.8V VEE OUT E01V E01V VEE OUTB 5.8V Pad capacitance 180 fF 0.8V 5.8V Pad capacitance 180 fF 0.8V 0.8V 0.8V VEE = -5V E21GA DVEE = -5V VEE = -5V Note: The ESD protection equivalent capacitance is 150 fF. Figure 43. ADC Gain Adjust Equivalent Analog Input Circuit and ESD Protections VCC = +5V -0.8V GND +0.8V NP1032C2 -5.8V E22V GA Pad capacitance 180 fF 1 k 0.8V 2 pF 0.8V GND 5.8V 500 A 500 A VEE E22GA VEE = -5V Note: The ESD protection equivalent capacitance is 150 fF. 35 2145A-BDC-03/02 Figure 44. GORB Equivalent Input Schematic and ESD Protections GORB: gray or binary select input; floating or tied to VCC -> binary VCC = +5V -0.8V 1 k -0.8V 1 k -5.8V 1 k VEE E21VA 5 k GORB Pad capacitance 180 fF 5.8V 5.8V 250 A 5.8V 250 A VEE = -5V E31G GND = 0V Note: The ESD protection equivalent capacitance is 150 fF. Figure 45. DRRB Equivalent Input Schematic and ESD Protections Actual protection range: 6.6V above VEE, in fact stress above GND are clipped by the CB diode used for Tj monitoring VCC = +5V GND = 0V NP1032C2 10 k 200 DRRB -1.3V Pad capacitance 180 fF -2.6V 5.8V 0.8V VEE E21G VEE = -5V Note: The ESD protection equivalent capacitance is 150 fF. 36 TS8388BGL 2145A-BDC-03/02 TS8388BGL TSEV8388BF: Device Evaluation Board For complete specification, see separate TSEV8388BGL document. General Description The TSEV8388BGL Evaluation Board (EB) is a board which has been designed in order to facilitate the evaluation and the characterization of the TS8388BGL device up to its 1.8 GHz full power bandwidth at up to 1 GSPS in the military temperature range. The high speed of the TS8388BGL requires careful attention to circuit design and layout to achieve optimal performance. This four metal layer board with internal ground plane has the adequate functions in order to allow a quick and simple evaluation of the TS8388BGL ADC performances over the temperature range. The TSEV8388BGL Evaluation Board is very straightforward as it only implements the TS8388BGL ADC, SMA connectors for input/output accesses and a 2.54 mm pitch connector compatible with HP16500C high frequency probes. The board also implements a de-embedding fixture in order to facilitate the evaluation of the high frequency insertion loss of the input microstrip lines, and a die junction temperature measurement setting. The board is constituted by a sandwich of two dielectric layers, featuring low insertion loss and enhanced thermal characteristics for operation in the high frequency domain and extended temperature range. The board dimensions are 130 mm x 130 mm. The board set comes fully assembled and tested, with the TS8388BGL and its heatsink installed. 37 2145A-BDC-03/02 Thermal and Moisture Characteristics Thermal Resistance from Junction to Ambient: RTHJA The following table lists the converter thermal performance parameters of the device itself, with no external heatsink added. Table 8. Thermal Resitance Air flow (m/s) 0 0.5 1 1.5 2 2.5 3 4 5 Estimated JA thermal resistance (C/W) 45 35.8 30.8 27.4 24.9 23 21.5 19.3 17.7 Figure 46. Thermal Resistance from Junction to Ambient: RTHJA 50 RTHJA (C/W) 40 30 20 10 0 0 1 2 3 4 5 Air flow (m/s) Thermal Resistance from Junction to Case: RTHJC Typical value for Rthjc is given to 6.7C/W (8C/W max). This value does not include thermal contact resistance between package and external component (heatsink or PCBoard). As an example, 2.0C/W can be taken for 50 m of thermal grease. 38 TS8388BGL 2145A-BDC-03/02 TS8388BGL CBGA68 Board Assembly with External Heasink It is recommended to use an external heatsink or PCBoard special design. Cooling system efficiency can be monitored using the Temperature Sensing Diode, integrated in the device. Figure 47. CBGA68 Board Assembly 50.5 24.2 20.2 32.5 31 Board Moisture Characteristics This device is sensitive to the moisture (MSL3 according to JEDEC standard): Shelf life in sealed bag: 12 months at <40C and <90% relative humidity (RH). After this bag is opened, devices that will be subjected to infrared reflow, vapor-phase reflow, or equivalent processing (peak package body temperature 220C) must be: * * mounted within 198 hours at factory conditions of 30C/60% RH, or stored at 20% RH. Devices require baking, before mounting, if Humidity Indicator Card is >20% when read at 23C 5C. If baking is required, devices may be baked for: * * 192 hours at 40C +5C/-0C and <5% RH for low-temperature device containers, or 24 hours at 125C 5C for high temperature device containers. 39 2145A-BDC-03/02 Definitions Definition of Terms (BER) Bit Error Rate Probability to exceed a specified error threshold for a sample. An error code is a code that differs by more than 4 lsb from the correct code. Analog input frequency at which the fundamental component in the digitally reconstructed output has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for input at Full Scale. Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale, to the RMS sum of all other spectral components, including the harmonics except DC. Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale, to the RMS sum of all other spectral components excluding the five first harmonics. Ratio expressed in dBc of the RMS sum of the first five harmonic components, to the RMS value of the measured fundamental spectral component. Ratio expressed in dB of the RMS signal amplitude, set at 1 dB below Full Scale, to the RMS value of the next highest spectral component (peak spurious spectral component). SFDR is the key parameter for selecting a converter to be used in a frequency domain application (Radar systems, digital receiver, network analyzer, etc.). It may be reported in dBc (i.e.: degrades as signal levels is lowered), or in dBFS (i.e.: always related back to converter full scale). (FPBW) Full Power Input Bandwidth (SINAD) Signal to Noise and Distortion Ratio (SNR) Signal to Noise Ratio (THD) Total Harmonic Distorsion (SFDR) Spurious Free Dynamic Range (ENOB) Effective Number Of Bits ENOB = SINAD - 1.76 + 20 log (A/V/2) 6.02 Where A is the actual input amplitude and V is the full scale range of the ADC under test. (DNL) Differential Non Linearity The Differential Non Linearity for an output code i is the difference between the measured step size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum value of all DNL (i). DNL error specification of less than 1 lsb guarantees that there are no missing output codes and that the transfer function is monotonic. The Integral Non Linearity for an output code i is the difference between the measured input voltage at which the transition occurs and the ideal value of this transition. INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|. (DG) Differential Gain The peak gain variation (in percent) at five different DC levels for an AC signal of 20% Full Scale peak to peak amplitude. FIN = 5 MHz (TBC). Peak Phase variation (in degrees) at five different DC levels for an AC signal of 20% Full Scale peak to peak amplitude. FIN = 5 MHz (TBC). Delay between the rising edge of the differential clock inputs (CLK, CLKB) (zero crossing point), and the time at which (VIN, VINB) is sampled. (INL) Integral Non Linearity (DP) Differential Phase (TA) Aperture Delay 40 TS8388BGL 2145A-BDC-03/02 TS8388BGL (JITTER) Aperture Uncertainty (TS) Settling Time Sample to sample variation in aperture delay. The voltage error due to jitter depends on the slew rate of the signal at the sampling point. Time delay to achieve 0.2% accuracy at the converter output when a 80% Full Scale step function is applied to the differential analog input. Time to recover 0.2% accuracy at the output, after a 150% full scale step applied on the input is reduced to midscale. Delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing point) to the next point of change in the differential output data (zero crossing) with specified load. Time delay from Data transition to Data ready. (ORT) Overvoltage Recovery Time (TOD) Digital Data Output Delay (TD1) Time Delay from Data to Data Ready (TD2) Time Delay from Data Ready to Data (TC) Encoding Clock Period (TPD) Pipeline Delay General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock period. TC1 = Minimum clock pulse width (high) TC = TC1 + TC2 TC2 = Minimum clock pulse width (low) Number of clock cycles between the sampling edge of an input data and the associated output data being made available, (not taking in account the TOD). For the TS8388BF the TPD is 4 clock periods. Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB) and the reset to digital zero transition of the Data Ready output signal (DR). Time delay for the output DATA signals to rize from 20% to 80% of delta between low level and high level. Time delay for the output DATA signals to fall from 80% to 20% of delta between low level and high level. Ratio of input offset variation to a change in power supply voltage. (TRDR) Data Ready Reset Delay (TR) Rise Time (TF) Fall Time (PSRR) Power Supply Rejection Ratio (NRZ) Non Return to Zero When the input signal is larger than the upper bound of the ADC input range, the output code is identical to the maximum code and the Out of Range bit is set to logic one. When the input signal is smaller than the lower bound of the ADC input range, the output code is identical to the minimum code, and the Out of range bit is set to logic one. (It is assumed that the input signal amplitude remains within the absolute maximum ratings). The two tones intermodulation distortion (IMD) rejection is the ratio of either input tone to the worst third order intermodulation products. The input tones levels are at -7 dB Full Scale. The NPR is measured to characterize the ADC performance in response to broad bandwidth signals. When using a notch-filtered broadband white-noise generator as the input to the ADC under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample test. (IMD) InterModulation Distortion (NPR) Noise Power Ratio 41 2145A-BDC-03/02 Ordering Information Package Device TS 8388B C G L Manufacturer prefix L: ceramic lid Device or family Temperature Range: C: 0C < Tc; Tj < 90C V: 40C < Tc; Tj < 110C Package: G: CBGA72 with C and R Evaluation Board TS EV 8388B G L ZA2 ZA2: with MC100EL16 digital recivers __: No receiver Evaluation board prefix L: ceramic lid G: CBGA72 with C and R The evaluation board is delivered with an ADC and includes the heat sink. 42 TS8388BGL 2145A-BDC-03/02 TS8388BGL TS8388BGL Capacities and Resistances Implant Figure 48. TS8388BGL Capacities and Resistances Implant GND 0.9 mm 100 pF 7.0 mm DVEE 0.9 mm GND VCC 100 pF GAIN GND 100 pF VINB GND 50 GND VIN 50 0.9 mm VEE VCC VEE CLKB CLK 100 pF 100 pF 100 pF 50 50 GND GND GND GND GND 0.9 mm Only on-package marking Electrically isolated Note: R and C are discrete components of 0603 size (1.6 x 0.8 mm). GND VCC 100 pF GND VEE 100 pF GND VCC 100 pF GND VCC 100 pF GORB GND 100 pF 43 2145A-BDC-03/02 Outline Descriptions Figure 49. Package Dimension - 72 Pins CBGA CBGA 68 package. AL203 substrate. Package design. Corner balls (x4) are not connected (mechanical ball). Balls : 1.27 mm pitch on 11x11 grid. View balls side Top side with soldered R, C devices 0.95 max (using solder Sn/Pb 63/37) 0.20 T -T- 1.27 11 10 9 8 7 6 5 4 3 1 Ball A1 Index other side Balls side Balls Sn/Pb 63/37 AI203 substrate AI203 Ceramic Cap. Glued on substrate 0.15 7.84 7.84 15.00 0.15 mm 0.15 ref 0.30 max ABCDEFGHI 15.00 0.15 mm 72x D = 0.80 0.10 mm J K -B- 1.25 0.12 D 1.27 ref Detail of ball x2 0.63 0.10 All units in mm -A- 0.40 T A B (Positon of array of balls / edges A and B) 0.15 T (Positon of balls within array) 44 TS8388BGL 2145A-BDC-03/02 50 2 100 pF TS8388BGL Figure 50. Cross Section T 0.20 -TTop side with soldered R, C devices (using solder Sn/Pb 63/37) 0.95 max Balls side 100 pF Balls Sn/Pb 63/37 AI203 substrate AI203 Ceramic Cap. Glued on substrate 50 (0.200) (0.200) (0.250) (0.200) 1.25 0.12 All units in mm 0.15 (0.400) 45 2145A-BDC-03/02 Datasheet Status Description Table 9. Datasheet Status Datasheet Status Objective specification This datasheet contains target and goal specifications for discussion with customer and application validation. This datasheet contains target or goal specifications for product development. This datasheet contains preliminary data. Additional data may be published later; could include simulation results. This datasheet contains also characterization results. This datasheet contains final product specification. Validity Before design phase Target specification Valid during the design phase Preliminary specification -site Valid before characterization phase Preliminary specification -site Product specification Limiting Values Valid before the industrialization phase Valid for production purposes Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application Information Where application information is given, it is advisory and does not form part of the specification. Life Support Applications These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. 46 TS8388BGL 2145A-BDC-03/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. Motorola (R) is the registered trademark of Motorola Company. Other terms and product names may be the trademarks of others. Printed on recycled paper. 2145A-BDC-03/02 |
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