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| U2733B-C Fractional-N Frequency Synthesizer for DAB Tuner Description The U2733B-C is a monolithic integrated fractional-N frequency synthesizer circuit fabricated in TEMIC's advanced UHF5S technology. Designed for applications in DAB receivers, it controls a VCO to synthesize frequencies in the range of 70 MHz to 500 MHz in a 16 kHz raster; four different reference divide factors can be selected. The lock status of the phase detector is indicated at a special output pin, six switching outputs can be addressed. An internal frequency doubler provides an output signal having twice the frequency of the reference oscillator. All functions of this IC are controlled by I2C bus. Electrostatic sensitive device. Observe precautions for handling. Features D Microprocessor-controlled via an I2C bus D Four addresses selectable D Four reference divide factors selectable: 1024, 1120, 1152, 1536 effectively D Tristate phase detector with programmable charge pump D Programmable 15-bit counter 1:2048 to 1:32767 effectively D D D D D Superior phase-noise performance De-activation of tuning output programmable Six switching outputs (open collector) Reference frequency doubler (open collector output) Lock-status indication (open collector) Block Diagram FDO NFDO 10 Frequency doubler x2 9 Lock detector 3 1 REF NREF 4 5 Reference counter Tristate phase detector PLCK PD Programmable charge pump 2 VD Fractional-N control 18 17 RF NRF Programmable 13-bit counter N/N+1 5-bit latch 6-bit latch 2-bit latch 15-bit latch MUX MUX I2C bus-interface/control 19 GND 20 VS 6 ADR 7 SCL 8 SDA 11 12 Switches 13 14 15 16 12476 SWC SWD SWE SWF SWG SWH Figure 1. Block diagram Rev. A1, 23-Jun-99 1 (12) Preliminary Information U2733B-C Ordering Information Extended Type Number U2733B-CFS Package SSO20 Remarks Pin Description PD 1 VD 2 PLCK 3 REF NREF ADR SCL SDA 4 5 6 7 8 20 VS 19 GND 18 RF 17 NRF 16 SWH 15 SWG 14 SWF 13 SWE 12 SWD 11 SWC 12484 NFDO 9 FDO 10 Figure 2. Pinning Functional Description The U2733B-C is a low-power fractional-N frequency synthesizer designed for applications in DAB receivers. Its RF operation range reaches from 70 MHz to 500 MHz. The device includes input buffers for reference and RF dividers, a reference divider, a programmable RF divider using fractional-N technique, a tristate phase detector, a programmable charge pump, six switching outputs, a frequency doubler for the reference input signal and a control unit. The control unit has to be accessed by a microcontroller via an I2C bus. The programming information is stored in a set of internal registers. 2 (12) Preliminary Information AAAAAAAAAAA A A AAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAA A A AAAAAAAAAAAAAAAA AA AAAAAAAAAAA A AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAA AA AAAAAAAAAAA A AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AAAAAA A 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 The basic difference to the U2753B-C is the use of a special phase-noise shaping technique based on the fractional-N principle which concentrates the phase detector's phase-noise contribution to the spectrum of the controlled VCO at frequency positions where it does not damage the quality of the received DAB signal. In critical locations of the VCO's frequency spectrum, the phase detector's phase-noise contribution is reduced by roughly 12 dB. A special property of the transmission technique used in DAB is that the phase-noise weighting function (which measures the influence of the LO's phase noise on the phase information of the coded signal in a DAB receiver) has zeros, i.e., if phase noise is concentrated in the position of such zeros as discrete lines, the DAB signal is not disturbed as long as these lines do not exceed a certain limit. Rev. A1, 23-Jun-99 Pin 1 2 3 Symbol Function PD Tristate charge pump output VD Active filter output PLCK Lock-indicating output (open collector) REF Reference input NREF Reference input (inverted) ADR Address selection SCL Clock (I2C) SDA Data (I2C) NFDO Frequency-doubler output (inverted, open collector) FDO Frequency-doubler output (open collector) SWC Switching output (open collector) SWD Switching output (open collector) SWE Switching output (open collector) SWF Switching output (open collector) SWG Switching output (open collector) SWH Switching output (open collector) NRF RF input (inverted) RF RF input GND Ground VS Supply voltage U2733B-C For DAB mode I this phase noise weighting function is shown in the following figure: 1.80 1.60 1.40 1.20 PNWF 1.00 0.80 0.60 0.40 0.20 0.00 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 df / Hz 12477 Main Divider The main divider consists of a fully programmable 13-bit divider which defines a division ratio N. The applied division ratio is either N or N+1 according to the control of a special control unit. On average, the scaling factors SF = N+k/ 4 can be selected where k = 0, 1, 2, 3. In this way, the VCO frequencies fVCO = 4 (N+k/4) fref/(4 SFref) can be synthesized starting from a reference frequency, fref.. If we define SFeff = 4 N+k and SFref, eff = 4 SFref we end up with fVCO = SFeff fref/SFref,eff, Figure 3. PNWF vs. df/Hz It is important to realize that this function shows zeros in all distances from the center line which are multiples of the carrier spacing. The technique of concentrating the phase noise in the positions of such zeros is protected by a patent. In this circuit, the phase detector is operated at a frequency which is four times the desired frequency raster spacing (e.g., 16 kHz in case of DAB) and the well known fractional-N technique is used to synthesize the raster. As a result of this technique, spurious in the VCO's frequency spectrum occur not only in multiples of the phase detector's input comparison frequency (64 kHz) but also in multiples of the raster frequency (16 kHz). As described above for all DAB modes, these spurious are placed in spectral positions where the phase-noise weighting function is zero. Therefore, no measures are necessary to suppress these lines. where SFeff is defined by 15 bits. In the following, this circuit is described in terms of SFeff and SFref,eff. SFeff has to be programmed via the I2C-bus interface. An effective scaling factor from 2048 to 32767 can be selected. By setting the I2C-bus bit T, a test signal representing the divided input signal can be monitored at the switching output SWF. When the supply voltage is switched on, both the reference divider and the programmable divider are kept in RESET state till a complete scaling factor is written onto the chip. Changes in the setting of the programmable divider become active when the corresponding I2C-bus transmission is completed. By an internal synchronization procedure is ensured that such changes do not become active while the charge pump is sourcing or sinking current at its output pin. This behavior enables a smooth tuning of the output frequency without disturbing the controlled VCO's frequency spectrum. Phase Comparator and Charge Pump The tristate phase detector causes the charge pump to source or to sink current at the output Pin PD depending on the phase relation of its input signals which are provided by the reference and the main divider respectively. Four different values of this current can be selected by means of the I2C-bus bits I50 and I100. By using this option, for example, changes of the loop characteristics due to the variation of the VCO gain as a function of the tuning voltage can be reduced. The charge-pump current can be switched off using the I2Cbus bit TRI. A change in the setting of the charge-pump current becomes active when the corresponding I2C-bus transmission is completed. As described for the setting of the scaling factor of the programmable divider an internal synchronization procedure ensures that such changes do not become active while the charge pump is sourcing or sinking current at its output pin. This behavior enables a change in the charge-pump current without disturbing the controlled VCO's frequency spectrum. 3 (12) Reference Divider Four different scaling factors, SFref, of the reference divider can be selected by means of the bits RD1 and RD2 in the I2C-bus instruction code: 256, 280, 288, and 384. Starting from a reference oscillator frequency of 16.384 MHz/ 17.92 MHz/ 18.432 MHz/ 24.576 MHz, these scaling factors provide a frequency raster of 64 kHz. By changing the division ratio of the main divider from N to N+1 in an appropriate way (fractional-N technique), this frequency raster is interpolated to deliver a frequency spacing of 16 kHz according to the DAB specification. Thus, the reference divide factors 1024, 1120, 1152 and 1536 can be selected effectively. By setting of the I2C-bus bit T, a test signal representing the divided input signal can be monitored at the switching output SWC. Rev. A1, 23-Jun-99 Preliminary Information U2733B-C A high-gain amplifier (output Pin: VD), which is implemented in order to construct a loop filter as shown in the application circuit, can be switched off by means of the I2C-bus bit OS. An internal lock detector checks if the phase difference of the input signals of the phase detector is smaller than approximately 250 ns in seven subsequent comparisons. If phase lock is detected, the open-collector output Pin PLCK is set HIGH (logical value!). It should be noted that the output current of this pin must be limited by external circuit as it is not limited internally. If the I2C-bus bit TRI is set HIGH the lock detector function is de-activated and the logical value of the PLCK output is undefined. Frequency Doubler An internal frequency doubler provides a signal at twice the frequency of the reference signal appearing at the input Pins REF and NREF. If the I2C-bus bit OFD = HIGH, the current of its open-collector outputs FDO and NFDO is doubled. By means of the I2C-bus bit OFD, the frequency-doubler function can be switched off. As shown in figure 9, the output signal of the frequency doubler can be used in order to construct the LO signal of the IF circuit (U2759B). I2C-Bus Interface Via its I2C-bus interface, various functions can be controlled by a microprocessor. These functions are overviewed in the following sections `I2C bus instruction codes' and `I2C bus functions'. By means of thePin ADR, four different I2C-bus addresses can be selected as described in the section `Electrical characteristics'. Switching Outputs Six switching outputs controlled by the bits SWC, SWD, SWE, SWF, SWG, SWH can be used for any switching task on the front end board. The currents of these outputs are not limited internally. They have to be limited by external circuit. I2C-bus I2C-Bus Instruction Codes AAAAAAAAAAA A A A AAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAA A A AA AAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAAA A AA AAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA 1 RD1 X X 1 2IFD 0 0 RD2 n11 n5 0 SWC 0 0 X n10 n4 OS SWD 0 0 X n9 n3 T SWE 0 AS1 n14 n8 n2 TRI SWF 0 AS2 n13 n7 n1 I100 SWG 0 Description Address byte Divider byte 1 Divider byte 2 Divider byte 3 Control byte 1 Control byte 2 Control byte 3 MSB 1 0 X X 1 OFD X LSB 0 n12 n6 n0 I50 SWH 0 I2C-Bus Functions AS1, AS2 RD1, RD2 RD1 0 1 0 1 define the I2C-bus address TRI TRI = HIGH switches off the charge pump define the charge-pump current: I100 Charge-Pump Current (nominal)/mA 50 102 151 203 define the effective scaling factor of the reference divider RD2 0 0 1 1 Effective Scaling Factor 1120 1152 1024 1536 I50, I100 I50 ni effective scaling factor (SFeff) of the main divider SFeff = SUM(ni 2i) OS = HIGH switches off the tuning output LOW HIGH LOW HIGH LOW LOW HIGH HIGH OS T OFD OFD = HIGH switches off the frequency doubler 2IFD 2IFD = HIGH doubles the frequency-doubler output current SWa SWa = HIGH switches on output current for T = HIGH reference signals describing the output frequencies of reference divider and programmable divider are monitored at SWF (programable divider) and SWC (reference divider) 4 (12) Rev. A1, 23-Jun-99 Preliminary Information U2733B-C I2C Bus Data Transfer Format START - ADR - ACK - Stop Start Description START STOP ACK ADR DBi CBi start condition stop condition acknowledge address byte divider byte i (i = 1, 2, 3) control byte i (i = 1, 2, 3) I2C Bus Timing The values of the periods shown are specified in the section `Electrical Characteristics'. More detailed information can be taken from `Application Note 1.0 (I2C -Bus Description)'. Please note: due to the I2C-bus specification, the MSB of a byte is transmitted first, the LSB last. Start Stop SDA tbuf tr tf thdstat SCL thdstat tlow thddat thigh tsudat tsudat tsustp 12478 Figure 4. I2C-bus timing diagram Typical Pulse Diagram START SDA SCL ADDRESS BYTE ACK DIVIDER BYTE 1 ACK DIVIDER BYTE 2 ACK DIVIDER BYTE 3 SDA SCL ACK CONTROL BYTE 1 ACK CONTROL BYTE 2 ACK STOP 12479 Figure 5. Typical pulse diagram Rev. A1, 23-Jun-99 5 (12) Preliminary Information AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A A A A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA Absolute Maximum Ratings Thermal Resistance Operating Range U2733B-C 6 (12) Junction ambient Supply voltage Ambient temperature range I2C-bus input / output voltage Pins 7 and 8 SDA output current Pin 8 Address select voltage Pin 6 Switch output voltage open collector Switch output current open collector PLCK output voltage open collector Pin 3 PLCK output current open collector Pin 3 Frequency doubler output open collector Pins 9 and 10 Parameters Supply voltage Junction temperature Storage temperature RF input voltage (AC) Pins 18 and 17 Reference input voltage (AC) Pins 4 and 5 Parameters Parameters SSO20 Symbol VS Tj Tstg RF, NRF REF, NREF SCL, SDA SDA ADR SWa SWa PLCK PLCK FDO, NFDO Symbol RthJA Symbol VS Tamb VS - 1 Min. -0.3 -0.3 -0.3 4 -0.3 -0.3 -40 Value 4.5 to 5.5 -30 to +85 Value 140 Typ. Preliminary Information Max. +5.5 125 +125 1 1 Rev. A1, 23-Jun-99 5.5 0.5 5.5 VS 5 VS 5.5 Unit K/W Unit V C Unit V C C Vpp Vpp V mA V V mA V mA V AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAA A A A A AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A AAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A A A A AAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA *) Test conditions: VS = 5 V, Tamb = 25C, unless otherwise specified Rev. A1, 23-Jun-99 Electrical Characteristics Saturation voltage Lock indication, PLCK Leakage current Effective phase noise Input sensitivity Maximum input signal Input impedance Phase detector, PD Charge pump current RF input, RF, NRF Input frequency range Input sensitivity Maximum input signal Input impedance VSWR REF input, REF, NREF Input frequency range Tuning step Effective scaling factor of programmable divider Effective scaling factor of reference divider Parameters Supply current The phase detector's phase-noise contribution to the VCO's frequency spectrum is referred to the operating frequency of the phase detector divided by 4, according to the fractional-N technique (regularly: 16 kHz). *) Test Conditions / Pins SWa = LOW, TRI = LOW, PLCK = LOW, OS = LOW, I50 = HIGH, I100 = HIGH OFD = LOW, 2IFD = LOW SWa = LOW, TRI = LOW, PLCK = LOW, OS = LOW, I50 = HIGH, I100 = HIGH, OFD = HIGH, 2IFD = LOW IPLCK = 0.5 mA VPLCK = 5.5 V IPD = 203 TRI = HIGH I100 = LOW, I50 = LOW I100 = LOW, I50 = HIGH I100 = HIGH, I50 = LOW Single ended Pin 1 I100 = HIGH, I50 = HIGH Pins 4 and 5 VS = 4.5 V, Tamb = 20C Differential RD1 = LOW, RD2 = LOW RD1 = HIGH,RD2 = LOW RD1 = LOW, RD2 = HIGH RD1 = HIGH, RD2 = HIGH 17.920 MHz/ 18.432 MHz/ 16.384 MHz/ 24.576 MHz reference frequency Pins 17 and 18 VS = 4.5 V, Tamb = 20C Preliminary Information mA VPLCK,sat frf Vrfs Vrfmax Zrf VSWRrf IPD4 IPD3 IPD2 IPD1 IPD,tri Symbol Is SFref,eff IPLCK,L Vrefs Vrefmax Zref SFeff LPD frast fref Iso 120 160 2048 Min. 13.2 40 80 70 5 2.7 o 2.5 17.92 18.432 10 102 151 203 -163 1120 1152 1024 1536 16 50 Typ. 16.5 14.6 200 2 10 U2733B-C 32767 100 120 180 240 Max. 19.8 60 300 500 20 300 0.5 10 30 mVrms mVrms kW o pF dBc/Hz MHz mVrms mVrms MHz Unit mA kHz mA mA mA mA mA mA 7 (12) nA W V AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A AAAAA AAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAAAA AAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A AAAA A A A A A AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAAAA AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Test conditions: VS = 5 V, Tamb = 25C, unless otherwise specified Electrical Characteristics (continued) U2733B-C 8 (12) Output voltage SDA (open collector) SCL clock frequency Rise time (SCL, SDA) Fall time (SCL; SDA) Time before new transmission can start SCL HIGH period SCL LOW period Hold time START Setup time START Setup time STOP Hold time DATA Setup time DATA Switches, SWa Leakage current Saturation voltage Address selection, ADR AS1 = 0, AS2 = 0 AS1 = 0, AS2 = 1 AS1 = 1, AS2 = 0 AS1 = 1, AS2 = 1 I2C bus, SCL, SDA Input voltage SCL/SDA p g Parameters Test Conditions / Pins Frequency doubler, FDO, NFDO Pins 9 and 10 Output current VFDO = VS, VNFDO = VS, 2IFD = LOW VFDO = VS, VNFDO = VS, 2IFD = HIGH Minimum output voltage VS = 5 V Pins 7 and 8 HIGH LOW ISDA = 2 mA, SDA = LOW VSWa = 5.5 V ISWa = 4 mA Pin 6 Symbol IFDOL, INFDOL IFDOH, INFDOH VFDO, VNFDO ISW,L VSW,sat thigh tlow thdsta tsusta tsustp thddat tsudat fSCL tr tf tbuf VH VL 0.4 VS 0.9 VS Min. 4 4.7 4 4.7 4.7 0 250 4.7 0.1 0.8 0.4 3 0 4 open Typ. 1.0 0.5 Preliminary Information Rev. A1, 23-Jun-99 0.6 VS VS 0.1 VS Max. 100 1 300 5.5 1.5 0.4 10 0.5 1.2 0.6 mApp mApp Unit kHz mA ms ms ms ms ms ms ms ms ns V V V V V V V V ns U2733B-C Application Circuit +8.5V Alternative load circuit VS U2750B Band switches L1, L2: LL1608-F47NJ (TOKO) VS 20 19 18 17 16 15 14 13 12 11 L1 47nH (5%) L2 47nH (5%) 600ENS- 9272Y (TOKO) VCO signal Tuning voltage VS 1n 1n 15p (5%) +17V for f res= 36MHz U2733B-C 1 4.7n 2 3 4 1n 5 6 1n 7 8 9 10 180p (1%) 27p (1%) (18p) 22k 1k 10n 1k 10n 470p SDA SCL 47k 1n U2759B 1n C BC846B Ref. oscillator Address select voltage 22k +5V 12480 Figure 6. Application circuit Phase Noise Performance 10.00 dB/DIV (Example: SFeff = 16899, SFref,eff = 1120, fref = 17.92 MHz, IPD = 200 mA, reference oscillator: MARCONI INSTRUMENTS signal generator 2042, spectrum analysis: HP70000, above shown application circuit, band A oscillator of U2309B) 10.00 dB/DIV -70.5 dBc/Hz CENTER 270.384 MHz RB 100 Hz VB 100 Hz SPAN 10.00 kHz ST 3.050 sec 12481 CENTER 270.384 MHz RB 1.00 kHz VB 1.00 kHz SPAN 200.0 kHz ST 600.0 msec 12482 Figure 7. Figure 8. Rev. A1, 23-Jun-99 9 (12) Preliminary Information U2733B-C Integration in TEMIC DAB Receiver Concept 10 (12) U2750B 1452 ... 1492 MHz 79 ... 240 MHz AGC U2759B AGC IF2 (IF3) SAW 38.912 MHz VCO 3.072 MHz PIN ~ 190 ... 230 MHz Channel decoder FSYNC- generation Figure 9. DAB Receiver Frontend 35.84 MHz U2733B (U2734B) Preliminary Information PLL 17.92 MHz DCXO Reference System controller AFC L-band down-converter 12483 Rev. A1, 23-Jun-99 U2733B-C Package Dimensions Package SSO20 Dimensions in mm 6.75 6.50 5.7 5.3 4.5 4.3 1.30 0.25 0.65 5.85 20 11 0.15 0.05 0.15 6.6 6.3 technical drawings according to DIN specifications 13007 1 10 Rev. A1, 23-Jun-99 11 (12) Preliminary Information U2733B-C Ozone Depleting Substances Policy Statement It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2594, Fax number: 49 ( 0 ) 7131 67 2423 12 (12) Rev. A1, 23-Jun-99 Preliminary Information |
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