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U2758M-B
DAB Channel Decoder
Description
The channel decoder chip set for the DAB receiver consists of 4 ICs (U2758B-B, U2757M-B, a dynamic RAM 256 x 4 bit and a digital signal processor, e.g., MT DSP56166). The U2758M-B performs the program selection, de-interleaving and Viterbi decoding. Electrostatic sensitive device. Observe precautions for handling.
Features
D U2758M-B supports all 4 transmission modes of D D D
EUREKA 147 DAB preliminary system definition and ETSI DAB standard (ETS 300 401) Processing of FIC and up to 6 application channels Parallel use of up to 8 U2758M with separate application selection possible Functions: - Program selection - Frequency, time and block de-interleaving - Depuncturing with Equal Error Protection (EEP) and Unequal Error Protection (UEP) profiles
- Soft decision 384 kbit/s Viterbi decoder - PRBS descrambler - Reliability information calculation - CRC checksum comparison
D Interfaces:
- Metric interface: U2757M-B interface - DRAM interface: 256 x 4-bit dynamic RAM - DAB3 interface: source decoder interface - L3-bus interface: microcontroller (MC) interface
Block Diagram
ADR DATA OE CAS RAS WRITE TMODE TIN TMUX TOUT
9
4
3
21
3
16 MRC_MODE MRC_TOGGLE DAB3_WFORMAT
DATA_MET 4 DATA_CLO FRAME_SOUT SOS_OUT
DAB3_DATA
De-interleaving
De- puncturing
Viterbi decoder algorithm
DAB3_FLAG
DAB3 Interface
DAB3_CLK 7 DAB3_W
MCDATA
Control
MC Interface
MCMODE MCCLK
3
14687
CLK24576
RESET
VDD
VSS
IC_SEL
Figure 1. Block diagram
Ordering Information
Extended Type Number U2758M-BFT Package TQFP100 Remarks
Rev. A1, 07-May-98
1 (28)
Preliminary Information
U2758M-B
Table of Contents
1 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Overview of Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 De-interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Depuncturing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Viterbi Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 DAB3 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 MC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Metric Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 DRAM Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 MC Bus Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1 L3 Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2 U2758M-B Operation in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.3 Application Channel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UEP Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEP Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.4 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.5 Carrier Shift Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.6 Microcontroller Memory (MCM) Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Information Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Flag Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.7 DAB3 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation in Parallel Mode (MRC_MODE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplex Reconfiguration Mode (MRC_MODE = 1) . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 6 6 6 6 6 6 7 7 7 7 8 9 9 9 9 10 14 14 18 18 19 20 22 22 22 23 24 25 26 26 27
3
4
5
2 (28)
Rev. A1, 07-May-98
Preliminary Information
U2758M-B
1 Pin Description
96 DATA_3 95 DATA_2 94 DATA_1 93 DATA_0 98 TIN_18 100 TIN_20 97 TIN_17 99 TIN_19 91 WRITE 81 ADR5 80 ADR6 77 TMUX_2 ADR4
79 ADR7
86 ADR1
84 ADR3
83 VSS
92 VSS
78 ADR8
85 ADR2
89 CAS
90 RAS
87 VDD
88 OE
82
76
T_MODE_0 T_MODE_1 T_MODE_2 VDD FRAME_SOUT SOS_OUT DATA_MET_0 DATA_MET_1 DATA_MET_2 DATA_MET_3 DATA_CLO VSS TIN_0 TIN_1 TIN_2 TIN_3 VDD TOUT_0 TOUT_1 TOUT_2 TOUT_3 TOUT_4 TOUT_5 TOUT_6 TOUT_7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 36 37 38 40 42 43 39 41 44 27 28 29 30 31 32 33 34 45 26 35 46 47 48 49 50
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
TMUX_1 TMUX_0 VDD MRC_MODE MCR_TOGGLE DAB3_CLK DAB_DATA VSS DAB3_W1 DAB3_W2 DAB3_W3 DAB3_W4 DAB3_W5 DAB3_W6 DAB3_W7 DAB3_FLAG DAB3_WFORMAT VDD TIN_16 TIN_15 TIN_14 TIN_13 TIN_12 TIN_11 TIN_10
TIN_7
TOUT_12
CLK24576
MCMODE
TOUT_10
TOUT_11
TIN_5
TIN_6
TIN_8
IC_SEL_1
IC_SEL_2
TOUT_13
VSS
RESET
MCCLK
TOUT_8
MCDATA
TOUT_9
TIN_4
IC_SEL_0
TOUT_14
TOUT_15
TIN_9
VSS
VDD
14813
Figure 2. Pinning
Rev. A1, 07-May-98
3 (28)
Preliminary Information
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Pinning (Plastic TQFP100 Thin Quad-Flat Package)
U2758M-B
4 (28)
Pin Signal Left Side 1 T_MODE_0 2 T_MODE_1 3 T_MODE_2 4 VDD 5 FRAME_SOUT 6 SOS_OUT 7 DATA_MET_0 8 DATA_MET_1 9 DATA_MET_2 10 DATA_MET_3 11 DATA_CLO 12 VSS 13 TIN_0 14 TIN_1 15 TIN_2 16 TIN_3 17 VDD 18 TOUT_0 19 TOUT_1 20 TOUT_2 21 TOUT_3 22 TOUT_4 23 TOUT_5 24 TOUT_6 25 TOUT_7 Bottom Side 26 TIN_4 27 CLK24576 28 VSS 29 RESET 30 MCCLK 31 TIN_5 32 TIN_6 33 TIN_7 34 TIN_8 35 MCDATA 36 MCMODE 37 VDD 38 TOUT_8 39 TOUT_9 40 TOUT_10 41 TOUT_11 42 TOUT_12 43 TOUT_13 44 TOUT_14 45 TOUT_15 46 IC_SEL_0 47 IC_SEL_1 48 IC_SEL_2 49 VSS 50 TIN_9
Preliminary Information
Test input bit 4 System clock 24.576 MHz Ground Reset signal (active high) MC bus clock signal Test input bit 5 Test input bit 6 Test input bit 7 Test input bit 8 MC bus data signal MC bus mode signal Power supply Test output bit 8 Test output bit 9 Test output bit 10 Test output bit 11 Test output bit 12 Test output bit 13 Test output bit14 Test output bit15 IC selection Pin 0 (LSB) IC selection Pin 1 IC selection Pin 2 Ground Test input bit 9 Test mode selection bit 0 (LSB) Test mode selection bit 1 Test mode selection bit 2 (MSB) Power supply Frame synchronization signal input Symbol synchronization signal input 4-bit metric input (LSB) 4-bit metric input 4-bit metric input 4-bit metric input (MSB) Metric data clock 12.288 MHz Ground Test input bit 0 Test input bit 1 Test input bit 2 Test input bit 3 Power supply Test output bit 0 Test output bit 1 Test output bit 2 Test output bit 3 Test output bit 4 Test output bit 5 Test output bit 6 Test output bit 7 Description
Rev. A1, 07-May-98
BINCDN BTGCMOS BOUT6 BOUT6 BOUT6 BOUT6 BOUT6 BOUT6 BOUT6 BOUT6 BINCMOS BINCMOS BINCMOS BINCMOS BINCMOS BINCDN BINCDN BINCDN BINCDN BIOC6 BINCMOS BINCMOS BINCMOS BINCMOS BINCMOS BINCMOS BINCMOS BINCMOS PAD Type BINCDN BINCDN BINCDN BINCDN BINCDN BINCDN BINCDN BOUT6 BOUT6 BOUT6 BOUT6 BOUT6 BOUT6 BOUT6 BOUT6 BINCDN
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Pin Right Side 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Top Side 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 TMUX_2 ADR8 ADR7 ADR6 ADR5 ADR4 VSS ADR3 ADR2 ADR1 ADR0 VDD OE CAS RAS WRITE VSS DATA_0 DATA_1 DATA_2 DATA_3 TIN_17 TIN_18 TIN_19 TIN_20 TIN_10 TIN_11 TIN_12 TIN_13 TIN_14 TIN_15 TIN_16 VDD DAB3_WFORMAT DAB3_FLAG DAB3_W7 DAB3_W6 DAB3_W5 DAB3_W4 DAB3_W3 DAB3_W2 DAB3_W1 VSS DAB3_DATA DAB3_CLK MRC_TOGGLE MRC_MODE VDD TMUX_0 TMUX_1 Signal Test output multiplexer bit 2 (MSB) External DRAM address bit 8 (MSB) External DRAM address bit 7 External DRAM address bit 6 External DRAM address bit 5 External DRAM address bit 4 Ground External DRAM address bit 3 External DRAM address bit 2 External DRAM address bit 1 External DRAM address bit 0 (LSB) Power Output enable signal for external DRAM Column address strobe for external DRAM Row address strobe for external DRAM Read/write for external DRAM Ground Data signal bit 0 of external DRAM (LSB) Data signal bit 1 of external DRAM Data signal bit 2 of external DRAM Data signal bit 3 of external DRAM (MSB) Test input bit 17 Test input bit 18 Test input bit 19 Test input bit 20 Test input bit 10 Test input bit 11 Test input bit 12 Test input bit 13 Test input bit 14 Test input bit 15 Test input bit 16 Power supply DAB3 window format selection DAB3 error flag DAB3 window signal 7 DAB3 window signal 6 DAB3 window signal 5 DAB3 window signal 4 DAB3 window signal 3 DAB3 window signal 2 DAB3 window signal 1 Ground DAB3 data output DAB3 clock output 384 kHz Multiplex reconfiguration toggle signal Multiplex reconfiguration mode signal Power supply Test output multiplexer bit 0 (LSB) Test output multiplexer bit 1 Description
Rev. A1, 07-May-98
Preliminary Information
U2758M-B
PAD Type
BIOT6 BIOT6 BIOT6 BIOT6 BINCDN BINCDN BINCDN BINCDN
BINCDN BOUT6 BOUT6 BOUT6 BOUT6 BOUT6
BINCDN BINCDN
B3STA6 B3STA6 BINCDN BINCDN
BINCDN B3STA6 B3STA6 B3STA6 B3STA6 B3STA6 B3STA6 B3STA6 B3STA6
BINCDN BINCDN BINCDN BINCDN BINCDN BINCDN BINCDN
BOUT6 BOUT6 BOUT12 BOUT6
BOUT6 BOUT6 BOUT6 BOUT6
5 (28)
U2758M-B
1.1
Left Bottom Right Top
Overview of Pins
VSS VDD 1 2 2 1 1 2 2 1 6 6 IN 14 13 12 5 44 OUT 8 8 10 13 39 IN/OUT 0 1 0 4 5 25 25 25 25 100
2.3
D D D D D
Viterbi Decoder
4-bit soft decision Viterbi decoder Constraint length 7
Generator polynomials 133, 171, 145, 133 in octal form
AAA A A A AA A AAAAAAAAAAAAAAAA A A A A AA AAA A A A AA A AAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A A A AA A A A AA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A AA
2
D D D D D
Output data clock is 384 kHz Reliability-information calculation using re-encoding and comparison error flag count EFC (sum of error flags per application is stored in the MC memory) (see chapters `DAB3 Interface Description' and `MC Bus Interface Description')
Functional Description
De-interleaving
D Bit error flag (DAB3 interface, DAB3_FLAG) and
2.1
Specification: ETSI DAB standard (ETS 300401) Input is metric result of the U2757M-B Bit reversal on transmission symbol level Frequency de-interleaving Time de-interleaving The time de-interleaved data are stored in an external 1-Mbit DRAM. If the multiplex configuration is changed, the output of the U2758M-B is invalid for 16 CIFs after the reprogramming of the U2758M-B. (see chapter `MC Bus Interface Description')
2.4
DAB3 Interface
D Energy dispersal (PRBS descrambling) for every
application, output is DAB3_DATA
D Program selection via L3 bus D DRAM interface processing including DRAM
refresh controller (see chapter `DRAM Interface Description') DRAM requirements: - 256 x 4 bit configuration - 110 ns cycle time - 60 ns access time - 8 ms or 1 ms refresh time
D Window signal selection D Binary- or decimal-coded window signals D Generation of 24 ms output frame and 384 kHz data
clock burst
D Multiplex reconfiguration mode processing
(see chapter `DAB3 Interface Description')
2.5
MC Bus Interface
D Programming of the U2758M-B:
- Application information - Mode information
2.2
Depuncturing
section 11.1.2, table 31:
D Specification: ETSI DAB standard (ETS 300401)
(see DAB standard puncturing vectors)
D U2758M-B device selection via the MC bus D MC memory delivers processing information
(see chapter `MC Bus Interface Description') - FIC with CRC checksum comparison in the last two bytes of every FIB - EFC per application - MC memory organisation - 5 ports with 32 bytes per port - 3 - 4 ports for FIC information (mode I, II:96 bytes, mode III: 128 bytes) - 1 port for EFC (sum of error flag bit) 2 bytes per application
D Error protection profiles are selected via the MC bus
(see chapter `MC Bus Interface Description')
D Unequal Error Protection (UEP) for audio services
(see DAB standard section 11.3.1, table 33: audio service component protection profile)
D Equal Error Protection (EEP) for data services D Bit rates in multiples of 8 kbit/s and 32 kbit/s
(see DAB standard section 11.3.2)
6 (28)
Rev. A1, 07-May-98
Preliminary Information
AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA
3.3
Supply voltage Input / output voltage Ambient temperature Power dissipation p Junction ambient
AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A
3.1
Rev. A1, 07-May-98
3.2
3
Supply voltage Input / output voltage Storage temperature
Electrical Characteristics
Thermal Resistance
Absolute Maximum Ratings
Operating Range
Parameters
Parameters
Parameters
Preliminary Information
Symbol VDD Vin/Vout Tamb Pstat Pdyn Symbol VDD Vin/Vout Tstg Symbol RthJA Min. 4.5 0 -40 Min. -0.5 -0.5 -65 Typ. Value t.b.d. t.b.d. t.b.d. Typ.
U2758M-B
Max. 7 VDD + 0.5 150
Max. 5.5 VDD +85
Unit K/W
Unit V V C mW mW
Unit V V C
7 (28)
AAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A AAAAAAAAAAA AAA A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAA A AAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A
The DRAM interface has TTL level, all other interfaces CMOS level
3.4
U2758M-B
8 (28) Tristate output p leakage current Output LOW voltage p g Output HIGH voltage p g Positive threshold Negative threshold Input leakage p g Input LOW voltage p g Parameter Input HIGH voltage p g
DC Characteristics
VIN = VDD or VSS VIN = VDD or VSS VIN = VDD IOH = +6 mA IOH = +12 mA IOH = +6 mA IOH = +6 mA IOH = +6 mA IOL = -6 mA IOL = -12 mA IOL = -6 mA IOL = -6 mA IOL = -6 mA VOUT = VDD or VSS VOUT = VDD or VSS VOUT = VDD or VSS
Conditions
Preliminary Information
PAD type BINCMOS BINCDN BIOC6 BIOT6 BINCMOS BINCDN BIOC6 BIOT6 BTGCMOS BTGCMOS BINCMOS BTGCMOS BINCDW BOUT6 BOUT12 BIOC6 BIOT6 B3STA6 BOUT6 BOUT12 BIOC6 BIOT6 B3STA6 BIOC6 BIOT6 B3STA6 Symbol Min. VIH 3.5 VIH 3.5 VIH 3.5 VIH 2.0 VIL VIL VIL VIL VT+ VT- 0.9 IL IL IL VOH 2.4 VOH 2.4 VOH 2.4 VOH 2.4 VOHAAAA 2.4 VOL VOL VOL VOL VOL IOZ IOZ IOZ Typ.
$1 $1 $1
3.1 1.3 1 1 40
Rev. A1, 07-May-98 Max.
$5 $5 $5
0.4 0.4 0.4 0.4 0.4 1.5 1.5 1.5 0.8 3.9
5 5 100
Unit V V V V V V V V V V A A A V V V V V V V V V V A A A
U2758M-B
4
4.1
Technical Description
General
Whenever a mode selection or an application channel selection command is invoked by the microcontroller, the DAB3 output interface of U2758M-B in invalid for 16 CIFs.
The channel decoder of the TEMIC DAB receiver is partioned into 4 ICs. These ICs are U2757M-B (FFT, differential demodulation and metric generation), U2758M-B (program selection, de-interleaving and Viterbi decoding), a DSP, for example MT DSP56166, and a dynamic RAM 256 x 4 bit.
The following functions are available in the U2758M-B:
4.2
Interface Description
The interface description is divided into four parts: metric interface description; DRAM interface description; MC bus interface description; and DAB3 interface description. All test input and output signals are implemented with a corresponding pull-up or pull down resistor, so all test pins can be unconnected for normal application.
As defined in the ETS 300401 document, the different services consist of service components which correspond to a sub channel in the Main Service Channel. Via the MC bus, up to 7 sub-channels, including FIC processing, can be selected. FIC processing is fixed on application channel 1. Thus a maximum 7 selected sub channels or application channels will be de-interleaved, depunctured and Viterbi decoded. Afterwards, the decoded bitstream, a corresponding window signal and a reliability information is available at the DAB3 interface. For the time de-interleaver, an external DRAM is necessary to store the interleaved data of the application channels.
4.3
Metric Interface Description
The 4-bit-wide metric input interface receives the metric from the U2757M-B. The data input clock is DATA_CLO and SOS_OUT is the window signal of the DATA_MET bus. FRAME_SOUT is the frame synchronization input, also delivered by the U2757M.
Table 1. Metric interface signal description
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DATA_CLO FRAME_SOUT SOS_OUT Rev. A1, 07-May-98 9 (28)
Signal Name DATA_MET[3:0]
Description Metric input data The metric DATA_MET[3:0] of U2758M-B correspond to the 4-bit output DATA_MET[5:2] of U2757M-B. U2757M-B output U2758M-B input U2757M-B/DATA_MET[5] U2758M-B/DATA_MET[3] MSB U2757M-B/DATA_MET[4] U2758M-B/DATA_MET[2] U2757M-B/DATA_MET[3] U2758M-B/DATA_MET[1] U2757M-B/DATA_MET[2] U2758M-B/DATA_MET[0] LSB These mode-dependent data arise in bit-reversed order at a data rate of DATA_CLO. For mode I 4096 values in bit reversed order are delivered by U2757M-B. For example, in mode I the first metric value belongs to the unused carrier 0, the second value to carrier 1024, the third value to carrier 512, and so on. Input clock for DAT_MET This clock is a windowed 12.288-MHz clock, depending on the validity of DATA_MET delivered by U2757M-B. Frame synchronization signal input, (active low signal) The signal defines the start of a transmission frame.The falling edge of FRAME_SOUT is used for the synchronization of the U2758M-B delivered by U2757M-B. Start of symbol window input signal of DATA_MET (active low signal). The signal defines the start of a symbol in a transmission frame and should be activated on the first input of each symbol. The falling edge of SOS_OUT is used for the synchronization of the U2758M-B and is delivered by U2757M-B.
Preliminary Information
U2758M-B
tclk tL tH
CLK24576 ts1 th1
FRAME_SOUT 2 x Ts ts2 th2
SOS_OUT ts3 DATA_MET [7:0 ] MET 0 ts4 MET 1 MET 2 MET N-3 MET N-2 th3 MET N-1 th4
DATA_CLO
14688
Figure 3. Metric input interface Table 2. Metric interface setup and hold times
10 (28)
Preliminary Information
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AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAA
ts2 th2 ts3 th3 ts4 th4 18.35 18.35 0 25 1600 0 25 -20 25 0 25 22.35 22.35 10 35 tguard* 10 35 -10 35 10 35 * see ETS 300401 standard
Parameters CLK24576 clock period CLK24576 clock HIGH CLK24576 clock LOW Set-up time *FRAME_SOUT Hold time *FRAME_SOUT Pulse width *FRAME_SOUT Set-up time *SOS_OUT Hold time *SOS_OUT Se-tup time DATA_MET Hold time DATA_MET Set-up time DATA_CLO Hold time DATA_CLO
Symbol tclk tH tL ts1 th1
Min.
Typ. 40.7
Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns
4.4
DRAM Interface Description
Table 3. DRAM interface signal description
For the time de-interleaving function an external DRAM of 1 Mbit is necessary. The U2758M-B includes a refresh controller. Therefore, the refresh period specification of the DRAM can be down to 1 ms. The DRAM has the following requirements: D 262144 (256 k) words by 4-bit organization D Min. access time 60 ns and min. cycle time 110 ns D Refresh period min. 1 ms D DRAM access modes: write cycle (early write), read cycle and RAS only refresh cycle
Signal Name DATA[0:3] I/O ADR[0:8] A RAS CAS
WRITE OE
Description Data input / output Address input Row address strobe, active LOW signal Column address strobe, active LOW signal Read / write input Output enable, active LOW signal
Rev. A1, 07-May-98
U2758M-B
tRC tRAS VIH RAS VIL tRCD tCRP VIH CAS VIL tASR VIH A0 - A8 VIL
Row address
tRP
tAR
tCSH tRSH tCAS tCRP
tRAH tRAL tASC tCAH
Column address
tRAD tRCS
tRCH tRRH tAA tROH tOEA
VIH WRITE VIL
OE
VIH VIL tRAC VOH tCAC tOEZ
Valid data out
tOFF
I/O 1 - I/O 4
open
VOL
Don't care
tCLZ
14689
Figure 4. Read cycle
Rev. A1, 07-May-98
11 (28)
Preliminary Information
U2758M-B
tRC tRAS VIH RAS VIL tRCD tCRP VIH CAS VIL tASR VIH A0 - A8 VIL
Row address
tRP
tAR
tCSH tRSH tCAS tCRP
tRAH tRAL tASC tCAH
Column address
tRAD tCWL tWCS tWCH tWP
VIH WRITE VIL
tWCR tRWL
OE
VIH VIL tDHR tDS VIH tDH
I/O 1 - I/O 4
Valid data in
open
14690
VIL
Don't care
Figure 5. Write cycle (early write) tRC tRAS VIH RAS VIL tCRP VIH CAS VIL tASR VIH A0 - A8 VIL
Row address Don't care
tRP
tCRP
tRAH
14691
Figure 6. RAS only refresh cycle
12 (28)
Rev. A1, 07-May-98
Preliminary Information
U2758M-B
Table 4. DRAM timing parameters
Parameter Random read or write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in low-Z Output buffer turn-off delay RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address hold time referred to RAS Column address to RAS lead time Read command set-up time Read command hold time Read command hold time referred to RAS Write command hold time Write command hold time referred to RAS Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Data hold time referred to RAS Write command set-up time RAS to CAS precharge time RAS hold time referred to OE OE access time Output buffer turn-off delay time from OE
Symbol tRC
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tRAC tCAC tAA tCLZ tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS tRPC tROH tOEA tOEZ 40 80 40 80 40 40 20 40 20 20 20 40 80 60 100 60 60 20 60 40 60 60 40 40 80 20 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Rev. A1, 07-May-98 13 (28)
DRAM Min. Max. 110 - - 60 - 20 - 30 0 - 0 20 40 - 60 10000 20 - 60 - 20 10000 20 40 15 30 5 - 0 - 10 - 0 - 15 - 50 - 30 - 0 - 0 - 0 - 15 - 50 - 15 - 20 - 20 - 0 - 15 - 50 - 0 - 0 - 10 - - 20 0 20
Min.
U2758M Typ. Max. 120
Unit
Preliminary Information
U2758M-B
4.5 MC Bus Interface Description
The MC bus selection is performed with the signal MCMODE during the RESET high active phase. If MCMODE is `1' during the RESET active high period, the MC interface is disabled. If MCMODE is `0' during the RESET active high period, the MC interface is configured as a L3 bus interface. After a reset, all internal parameter are set to their default values. This section describes the data transfer between a microcontroller and the U2758M-B. The MCMODE signal must be set low during the RESET active period to define the use of the L3 bus. Via the MC bus interface, the microcontroller has to select the application channel, which can be either an audio or a data sub channel. Also the DAB mode has to be chosen. The carrier shift function is not supported any longer. The MC bus interface includes a so-called MC memory which offers the possibility of accessing some processing information, like FIC (Fast Information Channel), EFC (Error Flag Count) and the result of the comparision of the transmitted CRC signature and the on-chip calculated CRC signature of the FIC. A set of MC commands invoke the processing which starts time aligned with the next frame synchronization input signal FRAME_SOUT including a set-up time of approximately 0.5 ms. The following signals are influenced by the MC bus interface:
Table 5. MC bus interface signal description
4.5.1
L3 Bus Description
The L3 bus interface is a 3-wire microcontroller interface with a higher rate than other common interfaces. It allows connection of a microcontroller to several slave devices. The signals L3MODE and L3CLK are driven by the microcontroller, L3DATA is bi-directional. The preliminary L3 interface description offers 4 different types of instructions to handle the data transfer between a master (microcontroller) and one or several slave devices:
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A A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAA
IC_SEL[0:2] IC selection input pins Define the number of the U2758M-B, binary coded IC_SEL[0] LSB, IC_SEL[2] MSB MC bus data line for L3 bus MCDATA MCMODE If MC_MODE = 1 during RESET active don't care If MC_MODE = 0 during RESET active L3 bus mode line MC bus clock line for L3 bus MCCLK Table 6. L3 interface signal definition
Signal Name
Description
D Write command (command instruction) D Read command (command instruction) D Write data (data instruction) D Read data (data instruction)
Table 7 describes the controlling process (mode selection and application channel selection) and the read-out process (FIC, EFC).
Signal Name L3MODE
Description Defines the operation mode LOW -> address mode HIGH -> data mode Is a gated bit clock for transfer synchronization Maximum clock 2 MHz Carries the transferred serial data LSB first, MSB last, Basic data transfer 8 bit byte
Microcontroller output
U2758M-B (slave device) input
L3CLK
output
input
L3DATA
output / input
input / output
14 (28)
Rev. A1, 07-May-98
Preliminary Information
U2758M-B
Table 7. L3 bus instructions AM: address mode; HM: halt mode; DM: data mode; ( ) optional / depends on function
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Table 8. Address-mode byte of command and data instruction
Controlling Device MCU -> U2758M-B Instruction Sequence Mode L3 Bus Programming AM Address byte Write command (HM) DM Data byte AM Address byte Write data (HM) DM Data byte 0 ... ... ... (HM) (DM) Data byte n
Read-Out Information U2758M-B -> MCU Instruction Sequence Mode L3 Bus Programming Read command AM Address byte (HM) DM Data byte Read data AM Address byte (HM) DM Data byte 0 HM DM Data byte 1 ... HM DM Data byte 31
Rev. A1, 07-May-98
Preliminary Information
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AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A
SADR1 SADR0 LSB SDEV2 MSB SDEV1 SDEV0 LSB DOM1 MSB A command instruction is always followed by a data instruction. Its purpose is to identify the desired slave device on the bus, to specify the type of instruction applied and to define the type of data which are accessed by the data instruction to follow. These data can be addressed by the selection of so-called ports. All these instructions consist of an address-mode byte and one or several data-mode bytes which are marked by the L3MODE signal. In the address-mode byte system address, system-device select bit and the instruction type are specified. The data-mode byte of a command instruction consists of a single byte which characterizes the selected device and the port where those data are or have to be located, which are processed in the data instruction to follow. The data-mode byte of a data instruction consists of a defined number of bytes which contain the data to be transferred. During adressing mode, a single byte is sent by the microcontroller. The structure of this byte is shown in table 8, the timing is given in figure 5. The system address bits (SADR) indicate the DAB system, the system-device selection bits (SDEV) define the U2758M-B component and the data operation-mode bits(DOM) describe the data transfer instruction. For DAB applications, the system address is defined as follows: System SADR2 SADR1 SADR0 address DAB 0 1 1 Comment
Table 9. System-address configuration
Bit 7 MSB SADR2 MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 LSB DOM0 LSB
Reserved for DAB In a DAB receiver, several system devices are accessed by a L3 bus interface.These devices can be distinguished by means of the SDEV0, SDEV, SDEV2 bits:
15 (28)
U2758M-B
Table 10.DAB system-device configuration
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Table 11.Data operation mode instructions
DAB System Device SDEV2 SDEV1 SDEV0 Comment 0 0 0 MPEG audio source decoder U2758M-B 0 0 1 De-interleaving, depuncturing and Viterbi decoding; This system-device address is a fixed hardware implementation. t.b.d. 0 1 0 DAB data decoder i.e. MT 56166 0 1 1 DSP, synchronization tbd. 1 0 0 tbd. tbd. 1 0 1 tbd. tbd. 1 1 0 tbd. tbd. 1 1 1 tbd.
DOM1 0 0 1 1
DOM0 0 1 0 1
Data Operation Mode Data transfer from MC to U2758M Data transfer from U2758M to MC Register(IC) selection for write data transfer Register(IC) selection for read data transfer
Instruction Write data Read data Write command Read command
Table 12.Data-mode byte in write- or read-command instruction Bit 7 MSB Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 LSB
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IC_SEL2 MSB IC_SEL1 IC_SEL0 LSB PORT4 MSB PORT3 PORT2 PORT1 PORT0 LSB
The bits DOM0, DOM1 in the address byte characterize the type of instruction according to table 11. As already mentioned, the data mode of a command instruction consists of a single byte. Its structure is shown in table 12. An IC connected to the L3 bus reacts on the command of the microcontroller if the IC select bits IC_SEL0, IC_SEL1 and IC_SEL2 with the signal levels applied to the corresponding IC select pins IC_SEL(0:2). The bits PORT0, PORT1, PORT2, PORT3, PORT4 are used to define the port of those data which are processed in the data
td1 L3MODE tcL L3CLK tcH
instruction to follow. Table 15 and 18 give an over-view of those ports which can be addressed by a write command or a read command, respectively. During data mode, the microcontroller sends or receives information to or from the U2758M-B. The L3MODE signal is high, the L3CLK signal consist of 8 pulses which indicate the 8 transferred bits. L3DATA carries the data (LSB first) and must be stable during the low phase of the L3CLK signal. To separate two transferred bytes, the interface protocol uses a so-called halt mode where the L3CLK remains high.
th2
L3DATA th1 tsu Figure 7. Timing address mode
14692
16 (28)
Rev. A1, 07-May-98
Preliminary Information
U2758M-B
td1 L3MODE tcL L3CLK tsu th1 L3DATA micro- controller to IC Figure 8. Timing data mode (slave receiver) tcH th1 th2
14693
td1 L3MODE tcL L3CLK L3DATA micro- controller to IC L3DATA IC to micro- controller tcH
th1
th2
td2 td3
th3
td5
14694
Figure 9. Timing data mode (slave transmitter)
tL L3MODE th2 L3CLK L3DATA IC to micro- controller Figure 10. Timing halt mode td1
14695
Rev. A1, 07-May-98
17 (28)
Preliminary Information
U2758M-B
Table 13.L3 bus interface delay, set-up and hold times
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AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAA
240 440 80 240
Parameters Delay time between L3MODE and L3CLK Hold time between L3MODE and L3CLK Low phase of L3CLK High phase of L3CLK Set-up time between L3CLK and L3DATA Hold time between L3CLK and L3DATA Delay time between L3MODE and L3DATA Delay time between L3MODE and valid L3DATA Hold time between L3CLK and L3DATA Delay time between L3MODE and L3DATA L3MODE LOW time
Symbol td1 th2 tcL tcH tsu th1 td2 td3 th3 td5 tL
Min.
w w w w w w w
Typ. 190 190 250 250 190 30 300 500 100 300 190
Max.
360 560 120 360
Unit ns ns ns ns ns ns ns ns ns ns ns
4.5.2
U2758M-B Operation in Parallel
4.5.3
Application Channel Selection
In one channel decoder system, up to 8 U2758M-B can be used in parallel. They can be separately addressed by means of the data mode of a command instruction as desribed in the section "L3 Bus Description". A typical IC selection configuration is shown in table 14.
The application channel is either a UEP or an EEP sub channel. Up to 7 application channels can be programmed in one U2758M-B with a maximum data rate below 384 kHz. The FIC processing is fixed programmed on application channel 1. Depending on the selected write port address, a defined number of bytes follows. The definition of the write port addresses including these numbers are shown in table 15. The 3 data bytes, which follow the address byte in a write data instruction, depend on the chosen application. IC_SEL0 0 1 0 1 0 1 0 1 Comment U2758M number 0 U2758M number 1 U2758M number 2 U2758M number 3 U2758M number 4 U2758M number 5 U2758M number 6 U2758M number 7
Table 14. IC selection configuration
IC Selection 0 (even) 1 (odd) 2 (even) 3 (odd) 4 (even) 5 (odd) 6 (even) 7 (odd)
IC_SEL2 0 0 0 0 1 1 1 1
IC_SEL1 0 0 1 1 0 0 1 1
Table 15. Write port selection configuration and following byte acount
Write Port Address Mode selection FIC (fixed) Application channel 2 Application channel 3 Application channel 4 Application channel 5 Application channel 6 Application channel 7
PORT4 0 0 0 0 0 0 0 0
PORT3 0 0 0 0 0 0 0 0
PORT2 0 0 0 0 1 1 1 1
PORT1 0 0 1 1 0 0 1 1
PORT0 0 1 0 1 0 1 0 1
Bytes 1 - 3 3 3 3 3 3
18 (28)
Rev. A1, 07-May-98
Preliminary Information
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MSB MSB MSB MSB MSB For UEP applications, the switch-on/off information, the first capacity unit C0...C9 and the corresponding unequal-error protection profile index A0...A6 must be programmed. Also the EEP or UEP selection UEP/EEP MSB L3 bus programming: C7 S2 1 on x x 0 0 0 UEP / EEP S1 IC_SEL 1 DAB 1 DAB A6 C6 A5 C5 S0 x x 1 1 data mode C4 C3 CU data mode A4 A3 UEP entry address data mode P4 P3 address mode 0 0 U2758M address mode 0 0 U2758M data mode x x must be announced as shown in table 16. For the U2758M-B the FIC is processed as application channel 1, so the application channel 1 can not be programmed by the MC. x x P2 write port A2 C2 x x 1 1 C9 MSB A1 C1 P1 0 1 0 write command write data C0 LSB C8 CU A0 P0 0 LSB LSB LSB LSB LSB LSB
Rev. A1, 07-May-98
UEP Application
Preliminary Information
U2758M-B
19 (28)
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MSB MSB MSB MSB MSB MSB L3 bus programming: For EEP applications, the switch-on/off information and the first capacity unit number are also transferred. Additionally, EEP option, code rate and the net bit rate must be programmed by the microcontroller.
EEP Application
U2758M-B
20 (28) R1 C7 S2 1 on 0 0 code rate S1 IC_SEL 1 A/D 1 DAB 1 DAB R0 C6 N5 C5 S0 x x 1 1 data mode C4 C3 CU data mode N4 N3 data mode P4 P3 address mode 0 0 U2758M address mode 0 0 U2758M data mode x x x x net bit rate P2 write port O option N2 C2 1 1 N1 C1 P1 0
Preliminary Information
C9 MSB 1 0 write command Rev. A1, 07-May-98 write data C0 LSB C8 CU N0 P0 0 LSB LSB LSB LSB LSB LSB
U2758M-B
Table 16. Application channel programming for UEP and EEP sub-channels
Signal Name on
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UEP / EEP C(9:0) A(6:0) O R(1:0) N(5:0) If O = 0 If O = 1 1-A 00 code rate 2/8 1-B 00 code rate 4/9 2-A 01 code rate 3/8 2-B 01 code rate 4/7 3-A 10 code rate 4/8 3-B 10 code rate 4/6 4-A 11 code rate 6/8 4-B 11 code rate 4/5 If O=0; EEP set A; Net bit rate in multiples of 8 kbit/s N = n-1 000000 n 8 kbit/s = 8 kbit/s 000001 n 8 kbit/s = 16 kbit/s ... Nmax (< (384 kbit/s -Data rateallAppl.Channel - DatarateFIC))/8 ) For mode III: 101001 42 8 kbit/s = 336 kbit/s For mode I, II and IV: 101010 43 8 kbit/s = 344 kbit/s If O=1; EEP set B; Net bit rate in multiples of 32 kbit/s N = n-1 000000 n 32 kbit/s = 32 kbit/s 000001 n 64 kbit/s = 64 kbit/s ... 001001 10 32 kbit/s = 320 kbit/s Example: The value N can be derived from the sub-channel size which is transmitted in the FIG 0/1 and Table 8 or 9 of DAB standard (ETS 300 401, Jan. 1997). Option 0 indicates multiples of 8 kbit/s. Protection level 3-A indicates code rate 1/2 (see table 8) SbChSize 48 CU correspond to 48 = 6 n (table 8) and therefore n = 48 / 6 = 8. Further N is defined by n -1 = 7. Data rate = n 8 kbit/s = 64 kbit/s Rev. A1, 07-May-98 21 (28)
Description 0 switch application channel off 1 switch application channel on 0 UEP application 1 EEP application First capacity unit number (Start Address, ETS 300 401, figure 13) UEP entry address corresponds to the Table switch A(6) and the Table index A(5:0) (ETS 300 401, table 7). EEP long form option 0 option 0 (protection level x-A) 1 option 1 (protection level x-B) Convolutional coding rate for data application
Preliminary Information
U2758M-B
4.5.4 Mode Selection
complete apllication-channel programming information is removed. So the mode selection can be used as an initialization procedure for the U2758M-B. The U2758M-B supports all 4 DAB modes. The mode must be set in advance to the application channel processing. If a new mode setting is programmmed, the L3 bus programming:
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A A AA A A AAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A A A A A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A
0 1 DAB 1 1 1 0 write command MSB S2 S1 IC_SEL S0 data mode 0 LSB 0 0 write port 0 0 MSB 0 1 DAB 1 address mode 0 0 U2758M data mode x x LSB 1 0 0 write data MSB LSB M1 M1 M0 M0 x x x x x x x x x x The mode bits (M1, M0) are defined as shown in the table below:
Table 17.Mode selection
MSB
address mode 0 0 U2758M
LSB
M1 (MSB) 0 0 1 1
M0 (LSB) 0 1 0 1
Mode Mode IV Mode I Mode II Mode III
4.5.5
Carrier Shift Programming
4.5.6
Due to the AFC function on U2757M-C, the carrier shift function is not supported any longer.
Microcontroller Memory (MCM) Access
During the processing of the selected application channels, some information is stored in the MC memory. A read block data transfer allows access to this memory. The MC memory has 5 ports with 32 bytes per port. A read block data transfer delivers a complete 32-byte block from the MC memory.
22 (28)
Rev. A1, 07-May-98
Preliminary Information
U2758M-B
Table 18.Read port selection configuration and following byte account
Read Port Address FIB port 1 FIB port 2 FIB port 3 FIB port 4 EFC
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AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A
AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA A A A A AA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A A AA
32 32 32 32 32
PORT4 P4 0 0 0 0 0
PORT3 P3 0 0 0 0 0
PORT2 P2 0 0 0 0 1
PORT1 P1 0 0 1 1 0
PORT0 P0 0 1 0 1 0
Bytes
Fast Information Channel
The size of the FIC depends on the mode and is at most 128 bytes, which correspond to 4 Fast Information Blocks (FIB). These FIBs can be read out after the corresponding DAB3 window signal, window number 1, is deactivated. Additionally, the last two bytes of every FIB in the MC memory, not at the serial DAB3 interface, are replaced by the comparison of the received CRC signature and the recalculated CRC signature inside the U2758M-B. For FIC verification, these last two bytes indicate a correct transmisson at an early stage. If these two bytes are all zero, the received FIC information is correct. L3 bus programming: MSB 0 1 DAB 1
The order of the FIB bytes corresponds to the serial DAB3_DATA output. For example, the DAB3_DATA index for mode I (3 FIBs = 3 x 32 byte = 96 x 8 bit = 768 bit) is from 0 (first output) up to 767 (last serial output bit). These data are stored in the MC memory as FIB1 (first 32 bytes) at port 1, FIB2 (second 32 bytes) at port 2 and FIB3 (third 32 bytes) at port 3. The byte 0 (0:7) of the port 1 (FIB1) corresponds to index 0 to 7, byte 1 to index 8 to 15 and so on.
address mode 0 0 1 U2758MAAAAA
LSB
1 0 read command
MSB
S2
S1 IC_SEL
S0
data mode P4 P3
LSB
P2 read port
P1
P0
MSB
0
1 DAB
1
address mode 0 0 U2758M
LSB
1
0
0
read data
MSB FIC index7
FIC
FIC
data mode FIC FIC byte 0 data mode FIC FIC byte 1
LSB
FIC
FIC
FIC index0
MSB FIC index15
SSS
LSB
FIC
FIC
FIC
FIC
FIC index8
MSB FIC
FIC
FIC
data mode FIC FIC byte 31
LSB FIC FIC FIC
32 bytes delivered by U2758M-B
Rev. A1, 07-May-98
23 (28)
Preliminary Information
U2758M-B
Error Flag Count
Furthermore, the MC memory includes the sum of error flags per application. This result is achieved by summing up the DAB3_ERRORFLAG bit over the application duration, which corresponds to the time duration of the DAB3_W signal. The error flag information is calculated through a re-encoding and comparing process. The read block transfer again delivers 32 bytes at the EFC port. From these 32 bytes, however, only 14 bytes contain real EFC information as shown in table 19. The EFC of one application channel is a 16-bit-wide sum which is valid for 24 ms after the falling edge of the corresponding DAB3 window signal. It can be used for a rough BER estimation.
Table 19. Port 4 configuration
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A AAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A
Not used Not used Least significant byte EFC FIC Most significant byte EFC FIC Most significant byte EFC application channel 5 Least significant byte EFC application channel 6 Most significant byte EFC application channel 6 Least significant byte EFC application channel 7 Most significant byte EFC application channel 7 Not used Least significant byte EFC application channel 2 Most significant byte EFC application channel 2 Least significant byte EFC application channel 3 Most significant byte EFC application channel 3 Least significant byte EFC application channel 4
Byte 0 1 2 3 4 5 6 7 8
Error Flag Count
Byte 9 10 11 12 13 14 15 16 - 31
Error Flag Count Most significant byte EFC application channel 4 Least significant byte EFC application channel 5
L3 bus programming: MSB 0
1 DAB
1
address mode 0 0 U2758M
LSB
1
1 0 read command
MSB
S2
S1 IC_SEL
S0
data mode P4 P3
LSB
P2 read port
P1
P0
MSB
0
1 DAB
1
address mode 0 0 U2758M
LSB
1
0
0
read data
MSB EFC MSB
SSS
EFC
EFC
data mode EFC EFC byte 0
LSB
EFC
EFC
EFC LSB
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A
EFC EFC EFC EFC EFC LSB 32 bytes delivered by U2758M-B 24 (28) Rev. A1, 07-May-98
MSB EFC MSB
data mode EFC EFC byte 31
LSB
Preliminary Information
U2758M-B
4.5.7 DAB3 Interface Description
flag DAB3_WFORMAT, the window signals are binary or decimal coded. Furthermore, a multiplex reconfiguration mode can be performed. The output frame length of the data burst is 24 ms for all 3 DAB modes. This section describes the data output interface between the U2758M-B and a source decoder to follow. It is a windowed 384-kHz interface with single data bit line and a single error flag line. For every selected application channel, a window signal is generated. Depending on the
Table 20. DAB3 interface signal description
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DAB3_CLK DAB3_WFORMAT DAB3_W[1:7] MRC_MODE MRC_TOGGLE Multiplex reconfiguration toggle signal, input MRC_MODE = 1; 0 U2758M-B even (IC_SEL[0] low) is active and U2758M-B odd (IC_SEL[0] high) is inactive with a tri-stated DAB3 interface. 1 U2758M-B odd (IC_SEL[0] high) is active and U2758M-B even (IC_SEL[0] low) is inactive with a tri-stated DAB3 interface. MRC_MODE = 0 Do not care Rev. A1, 07-May-98 25 (28)
Signal Name DAB3_DATA DAB3_FLAG
Description Serial output data carries the decoded data burst at 384 kHz. Error flag signal, output reliability information which corresponds to the serial data DAB3_DATA signal. A `0' indicates an error-free transmisson. Is a gated 384-kHz clock, output Defines the window (DAB3_W) format, input 0 decimal-coded window format DAB3_W[1:7] single window line for every application channel 1 binary-coded window format DAB3_W[1] LSB, DAB3_W[2] , DAB3_W[3] MSB binary-coded window signals for the application channels The active window signal defines the processed application channel, output DAB3_WFORMAT 0 1 (binary coded) DAB3_W[1] FIC bit 0 (LSB) DAB3_W[2] application channel 2 bit 1 DAB3_W[3] application channel 3 bit 2 (MSB) DAB3_W[4] application channel 4 0 DAB3_W[5] application channel 5 0 DAB3_W[6] application channel 6 0 DAB3_W[7] application channel 7 0 Multiplex reconfiguration mode, input 0 U2758M-B operation in parallel mode Up to 8 U2758M-B can be programmed separately with normal DAB3 output behavior. 1 multiplex reconfiguration mode With a pair of even and odd U2758M-B, a multiplex reconfiguration can be handled without mute state. DAB3 interface is tri-stated for the inactive U2758M-B. If a multiplex reconfiguration occurs, the signal MRC_TOGGLE exchanges the inactive and active U2758M.
Preliminary Information
U2758M-B
2T DAB3_WI
DAB3_DATA DAB3_ERROR- FLAG DAB3_CLK (384 kHz) Figure 11. Timing DAB3 interface 64T 32T T CLK24576 t_d3clk DAB3_CLK t_d3data DAB3_DATA DAB3_ERROR- FLAG t_d3win DAB3_W
14710
14709
t_d3clk
t_d3data
t_d3win
Figure 12. Detailed timing DAB3 interface Table 21. DAB3 interface hold times
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Operation in Parallel Mode (MRC_MODE = 0) Multiplex Reconfiguration Mode (MRC_MODE = 1)
The operation in parallel mode increases the maximum data rate of the channel decoder and can be used for a system with source decoder and data decoder. Every U2758M-B can be programmed freely and separately. The U2758M-B offers the possibility handling a multiplex reconfiguration under certain circumstances without audio data loss. The limitation results from the different behavior of increasing and decreasing data rate of a sub-channel. In this mode the complete DAB3 interface can be set active or tri-stated with the MRC_TOGGLE signal as described in table 20. 26 (28) Rev. A1, 07-May-98
Parameters Delay time of DAB3_CLK Delay time of DAB3_DATA and DAB3_ERRORFLAG Delay time of DAB3_W
Symbol t d3clk t d3data t d3win
Min. 5 5 5
Typ. 15 15 15
Max. 35 35 35
Unit ns ns ns
Preliminary Information
U2758M-B
5 Package Information
Package plastic TQFP 100
Dimensions in mm
16.20 15.80 14.10 13.90 100 76 75 1 0.5 0.75 0.45 0.15 0.05 1.6 1.4
16.20 15.80
14.10 13.90
25 51 26 50
0.22
technical drawings according to DIN specifications
0.17
13051
Rev. A1, 07-May-98
27 (28)
Preliminary Information
U2758M-B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax number: 49 ( 0 ) 7131 67 2423
28 (28)
Rev. A1, 07-May-98
Preliminary Information

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