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| RFG60P05E Data Sheet July 1999 File Number 2745.6 60A, 50V, 0.030 Ohm, ESD Rated, P-Channel Power MOSFET This is a P-Channel power MOSFET manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. It was designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. This type can be operated directly from integrated circuits. Formerly developmental type TA09835. Features * 60A, 50V * rDS(ON) = 0.030 * Temperature Compensating PSPICE(R) Model * 2kV ESD Rated * Peak Current vs Pulse Width Curve * UIS Rating Curve * 175oC Operating Temperature * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Ordering Information PART NUMBER RFG60P05E NOTE: PACKAGE TO-247 BRAND RFG60P05E Symbol D When ordering, use the entire part number. G S Packaging JEDEC STYLE TO-247 SOURCE DRAIN GATE DRAIN (BOTTOM SIDE METAL) 4-147 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE(R) is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 RFG60P05E Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFG60P05E -50 -50 20 60 Refer to Peak Current Curve 215 1.43 Refer to UIS Curve 2 -55 to 175 300 260 UNITS V V V A W W/oC W/oC kV oC oC oC Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate above 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Electrostatic Discharge Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD MIL-STD-883, Category B(2) Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) t(ON) td(ON) tr td(OFF) tF t(OFF) Qg(TOT) Qg(-10) Qg(TH) CISS COSS CRSS RJC RJA VGS = 0V to -20V VGS = 0V to -10V VGS = 0V to -2V VDD = -40V, ID = 60A, RL = 0.67 Ig(REF) = -4mA TEST CONDITIONS ID = 250A, VGS = 0V VGS = VDS, ID = 250A VDS = -50V, VGS = 0V VDS = 0.8 x Rated BVDSS, TC = 150oC VGS = 20V ID = 60A, VGS = -10V (Figure 9) VDD = -25V, ID = 30A, RL = 0.83, VGS = -10V, RGS = 2.5 (Figure 13) MIN -50 -2 TYP 20 60 65 20 7200 1700 325 MAX -4 -1 -25 100 0.030 125 125 450 225 15 0.70 30 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF oC/W oC/W Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient VDS = -25V, VGS = 0V, f = 1MHz (Figure 12) Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage (Note 2) Diode Reverse Recovery Time NOTE: 2. Pulse test: pulse width 300s maximum, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). SYMBOL VSD tRR TEST CONDITIONS ISD = -60A ISD = -60A, dISD/dt = 100A/s MIN TYP MAX -1.75 200 UNITS V ns 4-148 RFG60P05E Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 ID , DRAIN CURRENT (A) 0 25 50 75 100 125 150 175 0.8 0.6 0.4 0.2 0 Unless Otherwise Specified -70 -60 -50 -40 -30 -20 -10 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 ZJC , NORMALIZED TRANSIENT THERMAL IMPEDANCE 1 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 100 101 PDM FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE -500 TC = 25oC, TJ = MAX RATED -500 VGS = -10V -100 100ms IDM , PEAK CURRENT (A) ID , DRAIN CURRENT (A) TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT CAPABILITY AS FOLLOWS: 175 - T C I = I 25 --------------------- 150 1ms -10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) -1 -1 10ms 100ms DC VDSS MAX = -50V -100 -100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION -50 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 -10 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY 4-149 RFG60P05E Typical Performance Curves -200 IAS , AVALANCHE CURRENT (A) STARTING TJ = 25oC ID , DRAIN CURRENT (A) -100 -120 VGS = -10V -80 VGS = -6V -40 VGS = -4.5V VGS = -5V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC Unless Otherwise Specified (Continued) -160 VGS = -20V VGS = -8V VGS = -7V STARTING TJ = 150oC If R = 0 tAV = (L) (IAS) / (1.3RATED BVDSS - VDD) If R 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] -10 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms) 10 0 0 -2 -4 -6 -8 VDS , DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS IDS(ON) , DRAIN TO SOURCE CURRENT (A) -160 175oC 25oC -120 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VDD = -15V PULSE DURATIONM = 80s DUTY CYCLE = 0.5% MAX -55oC 2 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = -10V, ID = 60A 1.5 -80 1 -40 0.5 0 0 -2 -4 -6 -8 -10 0 -80 -40 0 40 80 120 160 200 VGS , GATE TO SOURCE VOLTAGE (V) TJ , JUNCTION TEMPERATURE (oC) FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 2 VGS = VDS, ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 2 ID = 250A THRESHOLD VOLTAGE NORMALIZED GATE 1.5 1.5 1 1 0.5 0.5 0 -80 -40 0 40 80 120 160 200 0 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 4-150 RFG60P05E Typical Performance Curves 8000 CISS C, CAPACITANCE (pF) 6000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGS COSS Unless Otherwise Specified (Continued) -50 -10 VDS , DRAIN TO SOURCE VOLTAGE (V) -37.5 VDD = BVDSS RL = 0.83 IG(REF) = 4mA VGS = -10V 0.75 BVDSS VDD = BVDSS -7.5 4000 -25 -5 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS 0 -2.5 2000 CRSS 0 -12.5 0.50 BVDSS 0.25 BVDSS 0 I G ( REF ) 20 -----------------------I G ( ACT ) t, TIME (s) I G ( REF ) 80 -----------------------I G ( ACT ) 0 -5 -10 -15 -20 -25 VDS , DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS RG 0 + VDD VDD 0V VGS DUT tP IAS 0.01 IAS tP BVDSS VDS FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS tON VDS RL 0 VGS td(ON) tr 10% tOFF td(OFF) tf 10% VDD VGS RGS + VDS VGS 0 90% 90% DUT 10% 50% PULSE WIDTH 90% 50% FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS 4-151 VGS , GATE TO SOURCE VOLTAGE (V) RFG60P05E Test Circuits and Waveforms VDS RL 0 VGS = -2V VGS (Continued) Qg(TH) VDS VDD + -VGS Qg(-10) VDD Qg(TOT) 0 IG(REF) VGS = -10V DUT Ig(REF) VGS = -20V FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS 4-152 RFG60P05E PSPICE Electrical Model .SUBCKT RFG60P05E 2 1 3; CA 12 8 1.01e-8 CB 15 14 1.05e-8 CIN 6 8 6.9e-9 DBODY 5 7 DBDMOD DBREAK 7 11 DBKMOD DPLCAP 10 6 DPLCAPMOD EBREAK 5 11 17 18 -76.35 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTO 20 6 8 18 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 7.9e-9 LSOURCE 3 7 4.18e-9 12 DPLCAP VTO + GATE 1 LGATE RGATE 9 EVTO 20 18 8 ESG 10 8 6 5 + RDRAIN EBREAK 16 MOS2 21 6 RIN CIN 8 S1A 13 8 S1B CA + 6 EGS -8 13 S2A 14 13 S2B CB + EDS 14 5 8 IT 15 17 MOS1 11 DBREAK RSOURCE 7 RBREAK LSOURCE 3 SOURCE 18 + 17 18 LDRAIN DRAIN 2 REV 9/20/94 - - - MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 12.83e-3 RGATE 9 20 1.5 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 3.25e-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 -0.83 + - DBODY RVTO 19 VBAT + - .MODEL DBDMOD D (IS = 1.24e-12 RS = 4.72e-3 TRS1 = 1.43e-3 TRS2 = -4.91e-7 CJO = 6.98e-9 TT = 1.5e-7) .MODEL DBKMOD D (RS = 1.11e-1 TRS1 = 1.34e-3 TRS2 = 4.46e-12) .MODEL DPLCAPMOD D (CJO = 15e-10 IS = 1e-30 N = 10) .MODEL MOSMOD PMOS (VTO = -3.71 KP = 31.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 9.42e-4 TC2 = 0) .MODEL RDSMOD RES (TC1 = 5.85e-3 TC2 = 7.69e-6) .MODEL RVTOMOD RES (TC1 = -3.39e-3 TC2 = 1.07e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 4.6 VOFF = 2.6) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.6 VOFF = 4.6) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.16 VOFF = -3.84) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.84 VOFF = 1.16) .ENDS For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 4-153 |
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