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CY7B9910 CY7B9920
Low Skew Clock Buffer
Features

All outputs skew <100 ps typical (250 max.) 15 to 80 MHz output operation Zero input to output delay 50% duty cycle outputs Outputs drive 50 terminated lines Low operating current 24-pin SOIC package Jitter:<200 ps peak to peak, <25 ps RMS
The completely integrated PLL enables "zero delay" capability. External divide capability, combined with the internal PLL, allows distribution of a low frequency clock that is multiplied by virtually any factor at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility.
Block Diagram Description
Phase Frequency Detector and Filter
The Phase Frequency Detector and Filter blocks accept inputs from the reference frequency (REF) input and the feedback (FB) input and generate correction information to control the frequency of the Voltage Controlled Oscillator (VCO). These blocks, along with the VCO, form a Phase Locked Loop (PLL) that tracks the incoming REF signal.
Functional Description
The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer low skew system clock distribution. These multiple output clock drivers optimize the timing of high performance computer systems. Each of the eight individual drivers can drive terminated transmission lines with impedances as low as 50. They deliver minimal and specified output skews and full swing logic levels (CY7B9910 TTL or CY7B9920 CMOS).
VCO
The VCO accepts analog control inputs from the PLL filter block and generates a frequency. The operational range of the VCO is determined by the FS control pin.
Logic Block Diagram
TEST FB REF FS PHASE FREQ DET VOLTAGE FILTER CONTROLLED OSCILLATOR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Cypress Semiconductor Corporation Document Number: 38-07135 Rev. *B
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised August 07, 2007
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CY7B9910 CY7B9920
Pin Configuration
SOIC Top View
REF VCCQ FS NC VCCQ VCCN Q0 Q1 GND Q2 Q3 VCCN
1 2 3 4 5 6 7 8 9 10 11 12 7B9910 7B9920 24 23 22 21 20 19 18 17 16 15 14 13
GND TEST NC GND VCCN Q7 Q6 GND Q5 Q4 VCCN FB
Pin Definitions
Signal Name REF FB FS[1,2,3] TEST Q[0..7] VCCN VCCQ GND IO I I I I O PWR PWR PWR Description Reference frequency input.This input supplies the frequency and timing against which all functional variations are measured. PLL feedback input (typically connected to one of the eight outputs). Three level frequency range select. Three level select. See TEST MODE. Clock outputs. Power supply for output drivers. Power supply for internal circuitry. Ground.
Test Mode
The TEST input is a three level input. In normal system operation, this pin is connected to ground, allowing the CY7B9910 and CY7B9920 to operate as described in Block Diagram Description. For testing purposes, any of the three level inputs can have a removable jumper to ground or be tied LOW through a 100W resistor. This enables an external tester to change the state of these pins. If the TEST input is forced to its MID or HIGH state, the device operates with its internal phase locked loop disconnected and input levels supplied to REF directly control all outputs. Relative output-to-output functions are the same as in normal mode.
Notes 1. For all three state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 2. The level to be set on FS is determined by the "normal" operating frequency (fNOM) of the VCO (see Logic Block Diagram). The frequency appearing at the REF and FB inputs are fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/X when the device is configured for a frequency multiplication by using external division in the feedback path of value X. 3. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC reached 4.3V.
Document Number: 38-07135 Rev. *B
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CY7B9910 CY7B9920
Maximum Ratings
Operating outside these boundaries may affect the performance and life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage to Ground Potential................-0.5V to +7.0V DC Input Voltage ............................................-0.5V to +7.0V Output Current into Outputs (LOW) ............................. 64 mA
Static Discharge Voltage............................................ >2001V (MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Document Number: 38-07135 Rev. *B
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CY7B9910 CY7B9920
Electrical Characteristics Over the Operating Range
CY7B9910 Parameter VOH VOL VIH VIL VIHH VIMM VILL IIH IIL IIHH IIMM IILL IOS ICCQ Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage (REF and FB inputs only) Input LOW Voltage (REF and FB inputs only) Three Level Input HIGH Voltage (Test, FS)[4] Three Level Input MID Voltage (Test, FS)[4] Three Level Input LOW Voltage (Test, FS)[4] Input HIGH Leakage Current (REF and FB inputs only) Input LOW Leakage Current (REF and FB inputs only) Input HIGH Current (Test, FS) Input MID Current (Test, FS) Input LOW Current (Test, FS) Output Short Circuit Current[5] Operating Current Used by Internal Circuitry Output Buffer Current per Output Pair[6] Power Dissipation per Output Pair[7] Min VCC Max Min VCC Max Min VCC Max VCC = Max, VIN = Max VCC = Max, VIN = 0.4V VIN = VCC VIN = VCC/2 VIN = GND VCC = Max, VOUT = GND (25C only) VCCN = VCCQ = Max All Input Selects Open VCCN = VCCQ = Max IOUT = 0 mA Input Selects Open, fMAX VCCN = VCCQ = Max IOUT = 0 mA Input Selects Open, fMAX Com'l Mil/Ind -50 -500 200 50 -200 -250 85 90 14 -50 Test Conditions VCC = Min, IOH = -16 mA VCC = Min, IOH =-40 mA VCC = Min, IOL = 46 mA VCC = Min, IOL = 46 mA 2.0 -0.5 VCC - 1V VCC/2 - 500 mV 0.0 VCC 0.8 VCC VCC/2 + 500 mV 1.0 10 -500 200 50 -200 N/A 85 90 19 mA VCC - 1.35 -0.5 VCC - 1V VCC/2 - 500 mV 0.0 0.45 0.45 VCC 1.35 VCC VCC/2 + 500 mV 1.0 10 V V V V V A A A A A mA mA Min 2.4 VCC -0.75 V Max CY7B9920 Min Max Unit V
ICCN
PD
78
104[5]
mW
Notes 4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are achieved. 5. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B9920 outputs are not short circuit protected. 6. Total output current per output pair is approximated by the following expression that includes device current plus load current: CY7B9910: ICCN = [(4 + 0.11F) + [((835 - 3F)/Z) + (.0022FC)]N] x 1.1 CY7B9920: ICCN = [(3.5+.17F) + [((1160 - 2.8F)/Z) + (.0025FC)]N] x 1.1 Where F = frequency in MHz C = capacitive load in pF Z = line impedance in ohms N = number of loaded outputs; 0, 1, or 2 FC = F < C. 7. Total power dissipation per output pair is approximated by the following expression that includes device power dissipation plus power dissipation due to the load circuit: CY7B9910: PD = [(22 + 0.61F) + [((1550 - 2.7F)/Z) + (.0125FC)]N] x 1.1 CY7B9920: PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1.See note 3 for variable definition.
Document Number: 38-07135 Rev. *B
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CY7B9910 CY7B9920
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter Description Test Conditions CIN Input Capacitance TA = 25C, f = 1 MHz, VCC = 5.0V Max 10 Unit pF
AC Test Loads and Waveforms
5V R1 CL R2 R1=130 R2=91 CL = 50 pF (CL = 30pF for -5 and - 2 devices) (Includes fixture and probe capacitance)
7B9910-3
3.0V 2.0V Vth =1.5V 0.8V 0.0V 1ns 2.0V Vth =1.5V 0.8V 1ns
7B9910-4
TTL AC Test Load (CY7B9910)
VCC R1 CL R2
7B9910-5
TTL Input Test Waveform (Cy7B9910)
VCC 80% Vth = VCC/2 20% 0.0V 3ns 80% Vth = VCC/2 20% 3ns
7B9910-6
R1=100 R2=100 CL = 50 pF (CL =30 pF for -5 and - 2devices) (Includes fixture and probe capacitance)
CMOS AC Test Load (CY7B9920)
CMOS Input Test Waveform (CY7B9920)
Switching Characteristics
Over the Operating Range [11] CY7B9910-2[8] Parameter fNOM Description Operating Clock Frequency in MHz FS = LOW[1, 2] FS = MID[1, 2] FS = HIGH[1, 2, 3] tRPWH tRPWL tSKEW tDEV tPD tODCV tORISE tOFALL tLOCK tJR REF Pulse Width HIGH REF Pulse Width LOW Zero Output Skew (All Outputs)[13, 14] Device-to-Device Skew
[14, 15]
CY7B9920-2[8] Min 15 25 40 5.0 5.0 Typ Max 30 50 80[12] ns ns 0.1 -0.25 -0.65 0.5 0.5 0.0 0.0 2.0 2.0 0.25 0.75 +0.25 +0.65 2.5 2.5 0.5 200 25 ns ns ns ns ns ns ms ps ps Unit MHz
Min 15 25 40 5.0 5.0
Typ
Max 30 50 80
0.1 -0.25 -0.65 0.15 0.15 0.0 0.0 1.0 1.0
0.25 0.75 +0.25 +0.65 1.2 1.2 0.5 200 25
Propagation Delay, REF Rise to FB Rise Output Duty Cycle Variation[16] Output Rise Time PLL Lock Time
[17, 18]
Output Fall Time[17, 18]
[19]
Cycle-to-Cycle Output Jitter Peak to Peak RMS
Document Number: 38-07135 Rev. *B
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CY7B9910 CY7B9920
CY7B9910-5 Parameter fNOM Description Operating Clock Frequency in MHz FS = LOW
[1, 2]
CY7B9920-5 Max Min 15 25 40 5.0 5.0 Typ Max 30 50 80[12] ns ns 0.25 -0.5 -1.0 0.5 0.5 0.0 0.0 2.0 2.0 0.5 1.0 +0.5 +1.0 3.0 3.0 0.5 200 25 ns ns ns ns ns ns ms ps ps Unit MHz
Min 15 25 40 5.0 5.0
Typ
30 50 80
FS = MID[1, 2] FS = HIGH[1, 2, 3]
tRPWH tRPWL tSKEW tDEV tPD tODCV tORISE tOFALL tLOCK tJR
REF Pulse Width HIGH REF Pulse Width LOW Zero Output Skew (All Outputs)[13, 14] Device-to-Device Skew[8, 15] Propagation Delay, REF Rise to FB Rise Output Duty Cycle Output Rise Time PLL Lock Variation[16]
[17, 18
0.25 -0.5 -1.0 0.15 0.15 0.0 0.0 1.0 1.0
0.5 1.0 +0.5 +1.0 1.5 1.5 0.5 200 25
Output Fall Time[17, 18] Time[19] RMS[8] Cycle-to-Cycle Output Jitter Peak to Peak[8]
Notes 8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 9. CMOS output buffer current and power dissipation specified at 50 MHz reference frequency. 10. Applies to REF and FB inputs only. 11. Test measurement levels for the CY7B9910 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B9920 are CMOS levels (VCC/2 to VCC/2). Test conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 12. Except as noted, all CY7B9920-2 and -5 timing parameters are specified to 80 MHz with a 30 pF load. 13. tSKEW is defined as the time between the earliest and the latest output transition among all outputs when all are loaded with 50 pF and terminated with 50 to 2.06V (CY7B9910) or VCC/2 (CY7B9920). 14. tSKEW is defined as the skew between outputs. 15. tDEV is the output-to-output skew between any two outputs on separate devices operating under the same conditions (VCC, ambient temperature, air flow, and so on). 16. tODCV is the deviation of the output from a 50% duty cycle. 17. Specified with outputs loaded with 30 pF for the CY7B99X0-2 and -5 devices and 50 pF for the CY7B99X0-7 devices. Devices are terminated through 50 to 2.06V (CY7B9910) or VCC/2 (CY7B9920). 18. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B9910 or 0.8VCC and 0.2VCC for the CY7B9920. 19. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
Document Number: 38-07135 Rev. *B
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CY7B9910 CY7B9920
Switching Characteristics
Over the Operating Range[11] (continued) CY7B9910-7 Parameter fNOM Description Operating Clock Frequency in MHz FS = LOW[1, 2] FS = MID[1, 2] FS = HIGH1, 2, 3] tRPWH tRPWL tSKEW tDEV tPD tODCV tORISE tOFALL tLOCK tJR tJR REF Pulse Width HIGH REF Pulse Width LOW Zero Output Skew (All Outputs)[13, 14] -0.7 -1.2 0.15 0.15 Peak to RMS[8] Peak[8] Device-to-Device Skew[8, 15] Propagation Delay, REF Rise to FB Rise Output Duty Cycle Output Rise PLL Lock Variation[16] Time[17, 18] 0.0 0.0 1.5 1.5 Min 15 25 40 5.0 5.0 0.3 0.75 1.5 +0.7 +1.2 2.5 2.5 0.5 200 25 -0.7 -1.2 0.5 0.5 0.0 0.0 3.0 3.0 Typ Max 30 50 80 Min 15 25 40 5.0 5.0 0.3 0.75 1.5 +0.7 +1.2 5.0 5.0 0.5 200 25 CY7B9920-7 Typ Max 30 50 80[12] ns ns ns ns ns ns ns ns ms ps ps Unit MHz
Output Fall Time17, 18] Time[19] Cycle-to-Cycle Output Jitter
Document Number: 38-07135 Rev. *B
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CY7B9910 CY7B9920
AC Timing Diagrams
Figure 1. AC Timing Diagrams
tREF tRPWH REF tPD tODCV tRPWL
tODCV
FB
Q tJR
tSKEW OTHER Q
tSKEW
Figure 2. Zero Skew and Zero Delay Clock Driver
REF Z0 SYSTEM CLOCK FB REF FS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 TEST Z0 Z0 LOAD Z0 LOAD LOAD
LOAD
Document Number: 38-07135 Rev. *B
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CY7B9910 CY7B9920
Operational Mode Descriptions
Figure 2 shows the device configured as a zero skew clock buffer. In this mode the 7B9910/9920 is used as the basis for a low skew clock distribution tree. The outputs are aligned and may each drive a terminated transmission line to an independent load. The FB input is tied to any output and the operating frequency range is selected with the FS pin. The low skew specification, coupled with the ability to drive terminated transmission lines (with impedances as low as 50 ohms), enables efficient printed circuit board design. Figure 1 shows the CY7B9910/9920 connected in series to construct a zero skew clock distribution tree between boards. Cascaded clock buffers accumulates low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers in series.
Figure 3. Board-to-Board Clock Distribution
REF Z0
FB SYSTEM CLOCK REF FS
LOAD
LOAD
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
FB REF FS
Z0
LOAD
Z0
TEST
Z0
TEST
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
LOAD
LOAD
Document Number: 38-07135 Rev. *B
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CY7B9910 CY7B9920
Ordering Information
Accuracy (ps) 250 Ordering Code CY7B9910-2SC CY7B9910-2SCT CY7B9920-2SC[20] CY7B9910-5SC CY7B9910-5SCT CY7B9910-5SI CY7B9910-5SIT CY7B9920-5SC CY7B9920-5SCT CY7B9920-5SI CY7B9910-7SC CY7B9910-7SI[20] CY7B9920-7SC[20] CY7B9920-7SI[20] CY7B9910-2SXC CY7B9910-2SXCT CY7B9910-5SXC CY7B9910-5SXCT CY7B9910-5SXI CY7B9910-5SXIT CY7B9910-7SXC CY7B9910-7SXCT Package Type 24-Pb Small Outline IC 24-Pb Small Outline IC - Tape and Reel 24-Pb Small Outline IC 24-Pb Small Outline IC 24-Pb Small Outline IC - Tape and Reel 24-Pb Small Outline IC 24-Pb Small Outline IC - Tape and Reel 24-Pb Small Outline IC 24-Pb Small Outline IC - Tape and Reel 24-Pb Small Outline IC 24-Pb Small Outline IC 24-Pb Small Outline IC 24-Pb Small Outline IC 24-Pb Small Outline IC 24-Pb Small Outline IC 24-Pb Small Outline IC - Tape and Reel 24-Pb Small Outline IC 24-Pb Small Outline IC - Tape and Reel 24-Pb Small Outline IC 24-Pb Small Outline IC - Tape and Reel 24-Pb Small Outline IC 24-Pb Small Outline IC - Tape and Reel Operating Range Commercial Commercial Commercial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Commercial Commercial
500
750
Pb-Free 250 500
750
Package Diagram
Figure 4. 24-Pin (300 Mil) Molded SOIC S13
51-85025-*C
Note 20. Not recommended for new design.
Document Number: 38-07135 Rev. *B
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CY7B9910 CY7B9920
Document History
Document Title: CY7B9910/CY7B9920 Low Skew Clock Buffer Document Number: 38-07135 REV. ** *A *B ECN NO. 110244 1199925 1353343 Issue Date Orig. of Change 10/28/01 See ECN See ECN SZV Description of Change Change from Specification number: 38-00437 to 38-07135
DPF/AESA Added Pb-free parts in Ordering Information Added Note 20: Not recommended for the new design AESA Change status to final
(c) Cypress Semiconductor Corporation, 2001-2007.The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07135 Rev. *B
Revised August 07, 2007
Page 11 of 11
PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders.
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