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Datasheet File OCR Text:

(R)
X5168, X5169
(Replaces X25268, X25169)
Data Sheet June 15, 2006 FN8130.2
CPU Supervisor with 16Kbit SPI EEPROM
These devices combine three popular functions, Power-on Reset Control, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The device's low VCC detection circuitry protects the user's system from low voltage conditions by holding RESET/RESET active when VCC falls below a minimum VCC trip point. RESET/RESET remains asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Intersil's unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold in applications requiring higher precision.
Features
* Low VCC Detection and Reset Assertion - Five standard reset threshold voltages - Re-program low VCC reset threshold voltage using special programming sequence - Reset signal valid to VCC = 1V * Long Battery Life with Low Power Consumption - <50A max standby current, watchdog on - <1A max standby current, watchdog off - <400A max active current during read * 16Kbits of EEPROM * Built-in Inadvertent Write Protection - Power-up/power-down protection circuitry - Protect 0, 1/4, 1/2 or all of EEPROM array with Block LockTM protection - In circuit programmable ROM mode * 2MHz SPI Interface Modes (0,0 & 1,1) * Minimize EEPROM Programming Time - 32-byte page write mode - Self-timed write cycle - 5ms write cycle time (typical) * 2.7V to 5.5V and 4.5V to 5.5V Power Supply Operation * Available Packages - 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP * Pb-Free Plus Anneal Available (RoHS Compliant)
Block Diagram
WP SI SO SCK CS Data Register Command Decode & Control Logic Protect Logic Status Register 4Kbits 4Kbits 8Kbits EEPROM Array
Reset Timebase Power-on and Low Voltage Reset Generation RESET/RESET
VCC VTRIP
+ -
X5168 = RESET X5169 = RESET
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X5168, X5169 Ordering Information
PART NUMBER RESET (ACTIVE LOW) X5168P-4.5A X5168PZ-4.5A (Note) X5168PI-4.5A X5168PIZ-4.5A (Note) X5168S8-4.5A X5168S8Z-4.5A (Note) X5168S8I-4.5A* PART MARKING X5168P AL PART NUMBER RESET (ACTIVE HIGH) X5169P-4.5A PART MARKING X5169P AL X5169P Z AL X5169P AM X5169P Z AM X5169 AL X5169 Z AL X5169 AM X5169 Z AM X5169V AL VCC RANGE VTRIP RANGE (V) (V) 4.5-5.5 4.5-4.75 TEMP RANGE (C) 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 4.5-5.5 4.25-4.5 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 2.7-5.5 2.85-3.0 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE 8 Ld PDIP 8 Ld PDIP** (Pb-free) 8 Ld PDIP 8 Ld PDIP** (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) PKG. DWG # MDP0031 MDP0031 MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027
X5168P Z AL X5169PZ-4.5A (Note) X5168P AM X5169PI-4.5A
X5168P Z AM X5169PIZ-4.5A (Note) X5168 AL X5168 Z AL X5168 AM X5169S8-4.5A X5169S8Z-4.5A (Note) X5169S8I-4.5A X5169S8IZ-4.5A (Note) X5169V14-4.5A
X5168S8IZ-4.5A* X5168 Z AM (Note) X5168V14-4.5A X5168V AL
14 Ld TSSOP M14.173 14 Ld TSSOP M14.173 (Pb-free) 14 Ld TSSOP M14.173 14 Ld TSSOP M14.173 (Pb-free) 8 Ld PDIP 8 Ld PDIP** (Pb-free) 8 Ld PDIP 8 Ld PDIP** (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) MDP0031 MDP0031 MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027
X5168V14Z-4.5A X5168V Z AL X5169V14Z-4.5A X5169V Z AL (Note) (Note) X5168V14I-4.5A X5168V AM X5169V14I-4.5A X5169V AM
X5168V14IZ-4.5A X5168V Z AM X5169V14IZ-4.5A X5169V Z AM (Note) (Note) X5168P X5168PZ (Note) X5168PI X5168P X5168P Z X5168P I X5169P X5169PZ (Note) X5169PI X5169P X5169P Z X5169P I
X5168PIZ (Note) X5168P Z I X5168S8* X5168S8Z* (Note) X5168S8I* X5168S8IZ* (Note) X5168V14* X5168V14Z* (Note) X5168V14I* X5168V14IZ* (Note) X5168P-2.7A X5168PZ-2.7A (Note) X5168PI-2.7A X5168PIZ-2.7A (Note) X5168S8-2.7A* X5168 X5168 Z X5168 I X5168 Z I X5168V X5168V Z X5168V I X5168V Z I X5168P AN
X5169PIZ (Note) X5169P Z I X5169S8* X5169S8Z* (Note) X5169S8I* X5169S8IZ* (Note) X5169V14* X5169V14Z* (Note) X5169V14I* X5169V14IZ* (Note) X5169P-2.7A X5169 X5169 Z X5169 I X5169 Z I X5169V X5169V Z X5169V I X5169V Z I X5169P AN X5169P Z AN X5169P AP X5169P Z AP X5169 AN X5169 Z AN X5169 AP X5169 Z AP
14 Ld TSSOP M14.173 14 Ld TSSOP M14.173 (Pb-free) 14 Ld TSSOP M14.173 14 Ld TSSOP M14.173 (Pb-free) 8 Ld PDIP 8 Ld PDIP** (Pb-free) 8 Ld PDIP 8 Ld PDIP** (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) MDP0031 MDP0031 MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027
X5168P Z AN X5169PZ-2.7A (Note) X5168P AP X5169PI-2.7A
X5168P Z AP X5169PIZ-2.7A (Note) X5168 AN X5169S8-2.7A X5169S8Z-2.7A (Note) X5169S8I-2.7A X5169S8IZ-2.7A (Note)
X5168S8Z-2.7A* X5168 Z AN (Note) X5168S8I-2.7A* X5168S8IZ-2.7A (Note) X5168 AP X5168 Z AP
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X5168, X5169 Ordering Information (Continued)
PART NUMBER RESET (ACTIVE LOW) X5168V14-2.7A PART MARKING X5168V AN PART NUMBER RESET (ACTIVE HIGH) X5169V14-2.7A PART MARKING X5168V AN VCC RANGE VTRIP RANGE (V) (V) 2.7-5.5 2.85-3.0 TEMP RANGE (C) 0 to 70 0 to 70 -40 to 85 -40 to 85 2.7-5.5 2.55-2.7 0 to 70 PACKAGE PKG. DWG #
14 Ld TSSOP M14.173 14 Ld TSSOP M14.173 (Pb-free) 14 Ld TSSOP M14.173 14 Ld TSSOP M14.173 (Pb-free) 8 Ld PDIP 8 Ld PDIP** (Pb-free) MDP0031 MDP0031 MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027
X5168V14Z-2.7A X5168V Z AN X5169V14Z-2.7A X5169V Z AN (Note) (Note) X5168V14I-2.7A X5168V AP X5169V14I-2.7A X5169V AP
X5168V14IZ-2.7A X5168V Z AP X5169V14IZ-2.7A X5169V Z AP (Note) (Note) X5168P-2.7 X5168PZ-2.7 (Note) X5168PI-2.7 X5168PIZ-2.7 (Note) X5168S8-2.7* X5168S8Z-2.7* (Note) X5168S8I-2.7* X5168S8IZ-2.7* (Note) X5168V14-2.7* X5168V14Z-2.7* (Note) X5168V14I-2.7* X5168P F X5168P Z F X5168P G X5168P Z G X5168 F X5168 Z F X5168 G X5168 Z G X5168V F X5168V Z F X5168V G X5169P-2.7 X5169PZ-2.7 (Note) X5169PI-2.7 X5169PIZ-2.7 (Note) X5169S8-2.7* X5169S8Z-2.7* (Note) X5169S8I-2.7* X5169S8IZ-2.7* (Note) X5169V14-2.7* X5169V14Z-2.7* (Note) X5169V14I-2.7* X5169P F X5169P Z F X5169P G X5169P Z G X5169 F X5169 Z F X5169 G X5169 Z G X5169V F X5169V Z F X5168V G
-40 to 85
8 Ld PDIP 8 Ld PDIP** (Pb-free)
0 to 70
8 Ld SOIC 8 Ld SOIC (Pb-free)
-40 to 85
8 Ld SOIC 8 Ld SOIC (Pb-free)
0 to 70 0 to 70 -40 to 85 -40 to 85
14 Ld TSSOP M14.173 14 Ld TSSOP M14.173 (Pb-free) 14 Ld TSSOP M14.173 14 Ld TSSOP M14.173 (Pb-free)
X5168V14IZ-2.7* X5168V Z G (Note)
X5169V14IZ-2.7* X5168V Z G (Note)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add "-T1" suffix for tape and reel. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Pin Configuration
14 LD TSSOP 8 LD SOIC/PDIP CS SO WP VSS 1 2 3 4 X5168/X5169 8 7 6 5 VCC RESET/RESET SCK SI CS SO NC NC NC WP VSS 1 2 3 4 5 6 7 X5168/X5169 14 13 12 11 10 9 8 VCC RESET/RESET NC NC NC SCK SI
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X5168, X5169 Pin Description
PIN (SOIC/PDIP) 1 PIN TSSOP 1 NAME CS FUNCTION Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS is required. Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to "lock" the setting of the watchdog timer control and the memory write protect bits. Ground Supply Voltage Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on powerup at about 1V and remains active for 200ms after the power supply stabilizes. No internal connections
2 5
2 8
SO SI
6
9
SCK
3 4 8 7
6 7 14 13
WP VSS VCC RESET/ RESET
3-5,10-12
NC
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X5168, X5169 Principles of Operation
Power-on Reset
Application of power to the X5168, X5169 activates a poweron reset circuit. This circuit goes active at about 1V and pulls the RESET/RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When VCC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET/RESET, allowing the processor to begin executing code.
Resetting the VTRIP Voltage
This procedure sets the VTRIP to a "native" voltage level. For example, if the current VTRIP is 4.4V and the VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the VTRIP voltage, apply a voltage between 2.7 and 5.5V to the VCC pin. Tie the CS pin, the WP pin, and the SCK pin HIGH. RESET/RESET and SO pins are left unconnected. Then apply the programming voltage VP to the SI pin ONLY and pulse CS LOW then HIGH. Remove VP and the sequence is complete.
Low Voltage Monitoring
During operation, the X5168, X5169 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms.
CS SCK VCC VP SI FIGURE 2. RESET VTRIP VOLTAGE
VCC Threshold Reset Procedure
The X5168, X5169 has a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or for higher precision in the VTRIP value, the X5168, X5169 threshold may be adjusted.
Setting the VTRIP Voltage
This procedure sets the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure directly makes the change. If the new setting is lower than the current setting, then it is necessary to reset the trip point before setting the new value. To set the new VTRIP voltage, apply the desired VTRIP threshold to the VCC pin and tie the CS pin and the WP pin HIGH. RESET/RESET and SO pins are left unconnected. Then apply the programming voltage VP to both SCK and SI and pulse CS LOW then HIGH. Remove VP and the sequence is complete.
CS VP SCK VP SI
FIGURE 1. SET VTRIP VOLTAGE
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VTRIP Programming
Execute Reset VTRIP Sequence
Set VCC = VCC Applied = Desired VTRIP
New VCC Applied = Old VCC Applied + Error
Execute Set VTRIP Sequence
New VCC Applied = Old VCC Applied - Error
Apply 5V to VCC
Execute Reset VTRIP Sequence
Decrement VCC (VCC = VCC - 10mV)
NO
RESET pin goes active? YES
Error Emax
Measured VTRIP Desired VTRIP Error = 0
Error > Emax
Emax = Maximum Desired Error
DONE
FIGURE 3. VTRIP PROGRAMMING SEQUENCE FLOW CHART
VP 4.7K NC VTRIP Adj. Program + 1 8 2 X5168/ 7 3 X5169 6 4 5 NC NC 4.7K RESET
10K
10K
Reset VTRIP Test VTRIP Set VTRIP
FIGURE 4. SAMPLE VTRIP RESET CIRCUIT
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X5168, X5169 SPI Serial Memory
The memory portion of the device is a CMOS serial EEPROM array with Intersil's block lock protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. It contains an 8-bit instruction register that is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW during the entire operation. All instructions (Table 1), addresses and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off.
Write Enable Latch
The device contains a write enable latch. This latch must be SET before a write operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 3). This latch is automatically reset upon a power-up condition and after the completion of a valid write cycle.
Status Register
The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows:
7 WPEN 6 FLB 5 0 4 0 3 BL1 2 BL0 1 WEL 0 WIP
The Write-In-Progress (WIP) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a "1", a nonvolatile write operation is in progress. When set to a "0", no write is in progress.
TABLE 1. INSTRUCTION SET INSTRUCTION NAME WREN SFLB WRDI/RFLB RDSR WRSR READ WRITE Note: INSTRUCTION FORMAT* 0000 0110 0000 0000 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 OPERATION Set the write enable latch (enable write operations) Set flag bit Reset the write enable latch/reset flag bit Read status register Write status register (watchdog, block lock, WPEN and flag bits) Read data from memory array beginning at selected address Write data to memory array beginning at selected address
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
TABLE 2. BLOCK PROTECT MATRIX WREN CMD WEL 0 1 1 1 STATUS REGISTER WPEN X 1 0 X DEVICE PIN WP# X 0 X 1 BLOCK PROTECTED BLOCK Protected Protected Protected Protected BLOCK UNPROTECTED BLOCK Protected Writable Writable Writable STATUS REGISTER WPEN, BL0, BL1 WD0, WD1 Protected Protected Writable Writable
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The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When WEL = 1, the latch is set HIGH and when WEL = 0 the latch is reset LOW. The WEL bit is a volatile, read only bit. It can be set by the WREN instruction and can be reset by the WRDS instruction. The block lock bits, BL0 and BL1, set the level of block lock protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM array. Any portion of the array that is block lock protected can be read but not written. It will remain protected until the BL bits are altered to disable block lock protection of that portion of memory.
STATUS REGISTER BITS BL1 0 0 1 1 BL0 0 1 0 1
WP is LOW and WPEN bit programmed HIGH disables all status register write operations.
In Circuit Programmable ROM Mode
This mechanism protects the block lock and watchdog bits from inadvertent corruption. In the locked state (programmable ROM mode) the WP pin is LOW and the nonvolatile bit WPEN is "1". This mode disables nonvolatile writes to the device's status register. Setting the WP pin LOW while WPEN is a "1" while an internal write cycle to the status register is in progress will not stop this write operation, but the operation disables subsequent write attempts to the status register. When WP is HIGH, all functions, including nonvolatile writes to the status register operate normally. Setting the WPEN bit in the status register to "0" blocks the WP pin function, allowing writes to the status register when WP is HIGH or LOW. Setting the WPEN bit to "1" while the WP pin is LOW activates the programmable ROM mode, thus requiring a change in the WP pin prior to subsequent status register changes. This allows manufacturing to install the device in a system with WP pin grounded and still be able to program the status register. Manufacturing can then load configuration data, manufacturing time and other parameters into the EEPROM, then set the portion of memory to be protected by setting the block lock bits, and finally set the "OTP mode" by setting the WPEN bit. Data changes now require a hardware change.
ARRAY ADDRESSES PROTECTED X5168/X5169 None $0600-$07FF $0400-$07FF $0000-$07FF
The FLAG bit shows the status of a volatile latch that can be set and reset by the system using the SFLB and RFLB instructions. The flag bit is automatically reset upon power-up. The nonvolatile WPEN bit is programmed using the WRSR instruction. This bit works in conjunction with the WP pin to provide an in-circuit programmable ROM function (Table 2).
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25
26 27 28 29 30
Instruction SI
16 Bit Address 15 14 13 3 2 1 0
SO
High Impedance
Data Out 7 MSB FIGURE 5. READ EEPROM ARRAY SEQUENCE 6 5 4 3 2 1 0
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Read Sequence
When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the read EEPROM array sequence (Figure 1). To read the status register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. Refer to the read status register sequence (Figure 2).
Operational Notes
The device powers-up in the following state: * The device is in the low power standby state. * A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. * SO pin is high impedance. * The write enable latch is reset. * The flag bit is reset. * Reset signal is active for tPURST.
Data Protection
The following circuitry has been included to prevent inadvertent writes: * A WREN instruction must be issued to set the write enable latch. * CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle.
Write Sequence
Prior to any attempt to write data into the device, the "Write Enable" Latch (WEL) must first be set by issuing the WREN instruction (Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the device. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the EEPROM memory array, the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written. Any unused address bits are specified to be "0's". The WRITE operation minimally takes 32 clocks. CS must go low and remain low for the duration of the operation. If the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written. For the page write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 4). To write to the status register, the WRSR instruction is followed by the data to be written (Figure 5). Data bits 0 and 1 must be "0". While the write is in progress following a status register or EEPROM sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be high.
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CS
0 SCK
1
2
3
4
5
6
7
8
9
10
11 12 13 14
Instruction SI
SO
High Impedance
Data Out 7 MSB 6 5 4 3 2 1 0
FIGURE 6. READ STATUS REGISTER SEQUENCE
CS 0 SCK 1 2 3 4 5 6 7
SI
SO
High Impedance FIGURE 7. WRITE ENABLE LATCH SEQUENCE
CS 0 SCK Instruction SI 16 Bit Address 15 14 13 3 2 1 0 7 6 5 4 Data Byte 1 3 2 1 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 6 5 4 3 2 1 0 7 6 5 Data Byte 3 4 3 2 1 0 6 5 Data Byte N 4 3 2 1 0
FIGURE 8. WRITE SEQUENCE
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CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction SI 7 6 5 4
Data Byte 3 2 1 0
SO
High Impedance FIGURE 9. STATUS REGISTER WRITE SEQUENCE
Symbol Table
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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Absolute Maximum Ratings
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on any Pin with Respect to VSS . . . . . . . . . . . . -1.0V to +7V DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300C
Recommended Operating Conditions
Temperature Range Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Supply Voltage Limits -2.7 or -2.7A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Blank or -4.5A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V-5.5V
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
DC Electrical Specifications
Over the recommended operating conditions unless otherwise specified. LIMITS
SYMBOL ICC1 ICC2 ISB ILI ILO VIL (NOTE 1) VIH (NOTE 1) VOL1 VOL2 VOL3 VOH1 VOH2 VOH3 VOLS
PARAMETER VCC write current (active) VCC read current (active) VCC standby current WDT = OFF Input leakage current Output leakage current Input LOW voltage Input HIGH voltage Output LOW voltage Output LOW voltage Output LOW voltage Output HIGH voltage Output HIGH voltage Output HIGH voltage Reset output LOW voltage
TEST CONDITIONS SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open CS = VCC, VIN = VSS or VCC, VCC = 5.5V VIN = VSS to VCC VOUT = VSS to VCC
MIN
TYP
MAX 5 0.4 1
UNIT mA mA A A A V V V V V V V V
0.1 0.1 -0.5 VCC x 0.7
10 10 VCC x 0.3 VCC + 0.5 0.4 0.4 0.4
VCC > 3.3V, IOL = 2.1mA 2V < VCC 3.3V, IOL = 1mA VCC 2V, IOL = 0.5mA VCC > 3.3V, IOH = -1.0mA 2V < VCC 3.3V, IOH = -0.4mA VCC 2V, IOH = -0.25mA IOL = 1mA VCC - 0.8 VCC - 0.4 VCC - 0.2
0.4
V
Capacitance
SYMBOL COUT (NOTE 2)
TA = +25C, f = 1MHz, VCC = 5V. TEST CONDITIONS VOUT = 0V VIN = 0V MAX. 8 6 UNIT pF pF
Output capacitance (SO, RESET/RESET)
CIN (NOTE 2) Input capacitance (SCK, SI, CS, WP) NOTES: 1. VIL min. and VIH max. are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested.
12
FN8130.2 June 15, 2006
X5168, X5169
Equivalent A.C. Load Circuit at 5V VCC
5V 5V
A.C. Test Conditions
Input pulse levels Input rise and fall times VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
2.06k
4.6k
Input and output timing level
Output 3.03k 100pF
RESET/RESET 30pF
AC Electrical Specifications
(Over recommended operating conditions, unless otherwise specified.) 2.7-5.5V
SYMBOL SERIAL INPUT TIMING fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI(3) tFI(3) tCS tWC(4) Clock frequency Cycle time CS lead time CS lag time Clock HIGH time Clock LOW time Data setup time Data hold time Input rise time Input fall time CS deselect time Write cycle time
PARAMETER
MIN
MAX
UNIT
0 500 250 250 200 200 50 50
2
MHz ns ns ns ns ns ns ns
100 100 500 10
ns ns ns ms
13
FN8130.2 June 15, 2006
X5168, X5169
Serial Input Timing
tCS CS tLEAD SCK tSU SI MSB IN tH tRI tFI LSB IN tLAG
SO
High Impedance
Serial Output Timing
2.7-5.5V SYMBOL fSCK tDIS tV tHO tRO(3) tFO(3) Clock frequency Output disable time Output valid from clock low Output hold time Output rise time Output fall time 0 100 100 PARAMETER MIN 0 MAX 2 250 200 UNIT MHz ns ns ns ns ns
Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
Serial Output Timing
CS tCYC SCK tV SO MSB Out MSB-1 Out tHO tWL LSB Out tDIS tWH tLAG
SI
ADDR LSB IN
14
FN8130.2 June 15, 2006
X5168, X5169
Power-Up and Power-Down Timing
VTRIP 0 Volts tR RESET (X5168) tPURST tPURST tF tRPD VTRIP
VCC
RESET (X5169)
RESET Output Timing
SYMBOL VTRIP PARAMETER Reset trip point voltage, X5168-4.5A, X5168-4.5A Reset trip point voltage, X5168, X5169 Reset trip point voltage, X5168-2.7A, X5169-2.7A Reset trip point voltage, X5168-2.7, X5169-2.7 VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) Power-up reset time out VCC detect to reset/output VCC fall time VCC rise time Reset valid VCC 100 100 1 100 MIN 4.5 4.25 2.85 2.55 TYP 4.63 4.38 2.93 2.63 20 200 280 500 MAX 4.75 4.5 3.0 2.7 UNIT V
VTH tPURST tRPD tF
(5)
mV ms ns s s V
(5) (5)
tR
VRVALID Note:
(5) This parameter is periodically sampled and not 100% tested.
VTRIP Set Conditions
tTHD VCC VTRIP tTSU tVPS tP tVPH tRP
CS VP SCK VP SI
tVPS
tVPH
tVPO
tVPO
15
FN8130.2 June 15, 2006
X5168, X5169
VTRIP Reset Conditions
VCC* tVPS tP tVP1
tRP
CS
tVPS
tVPH
tVPO
SCK
VCC VP tVPO
SI
*VCC > Programmed VTRIP
VTRIP Programming Specifications VCC = 1.7-5.5V; Temperature = 0C to 70C
PARAMETER tVPS tVPH tP tTSU tTHD tWC tRP tVPO VP VTRAN Vta1 Vta2 Vtr Vtv SCK VTRIP program voltage setup time SCK VTRIP program voltage hold time VTRIP program pulse width VTRIP level setup time VTRIP level hold (stable) time VTRIP write cycle time VTRIP program cycle recovery period (between successive programming cycles) SCK VTRIP program voltage off time before next cycle Programming voltage VTRIP programmed voltage range Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25C) Subsequent VTRIP program voltage accuracy [(VCC applied-Vta1)-VTRIP] (programmed at 25C) VTRIP program voltage repeatability (successive program operations) (programmed at 25C) VTRIP Program variation after programming (0-75C). (programmed at 25C) 10 0 15 1.7 -0.1 -25 -25 -25 18 5.0 +0.4 +25 +25 +25 DESCRIPTION MIN 1 1 1 10 10 10 MAX UNIT s s s s ms ms ms ms V V V mV mV mV
VTRIP programming parameters are periodically sampled and are not 100% tested.
16
FN8130.2 June 15, 2006
X5168, X5169 Typical Performance
VCC Supply Current vs. Temperature (ISB)
18 16 14 10 8 6 4 2 0 -40C Watchdog Timer Off (VCC = 3V, 5V) 25C Temp (C) 90C Watchdog Timer On (VCC = 5V) Time (ms) 12 Isb (A)
tPURST vs. Temperature
205
Watchdog Timer On (VCC = 5V)
200 195 190 185 180 175 170 165 160 -40 25 Degrees C 90
VTRIP vs. Temperature (programmed at 25C)
5.025 5.000 4.975 3.525 Voltage 3.500 3.475 2.525 2.500 2.475 0 25 Temperature 85 VTRIP = 2.5V VTRIP = 3.5V VTRIP = 5V
17
FN8130.2 June 15, 2006
X5168, X5169 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. L 2/01
18
FN8130.2 June 15, 2006
X5168, X5169 Plastic Dual-In-Line Packages (PDIP)
D E N PIN #1 INDEX
SEATING PLANE L e b
A2
A c
E1
A1 NOTE 5
eA eB
1
2 b2
N/2
MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL A A1 A2 b b2 c D E E1 e eA eB L N PDIP8 0.210 0.015 0.130 0.018 0.060 0.010 0.375 0.310 0.250 0.100 0.300 0.345 0.125 8 PDIP14 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 14 PDIP16 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 16 PDIP18 0.210 0.015 0.130 0.018 0.060 0.010 0.890 0.310 0.250 0.100 0.300 0.345 0.125 18 PDIP20 0.210 0.015 0.130 0.018 0.060 0.010 1.020 0.310 0.250 0.100 0.300 0.345 0.125 20 TOLERANCE MAX MIN 0.005 0.002 +0.010/-0.015 +0.004/-0.002 0.010 +0.015/-0.010 0.005 Basic Basic 0.025 0.010 Reference Rev. B 2/99 NOTES: 1. Plastic or metal protrusions of 0.010" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. 2 1 NOTES
19
FN8130.2 June 15, 2006
X5168, X5169 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 14 0o 8o 0o MAX 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 14 8o MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 2 4/06
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
A2 c
E1 e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 20
FN8130.2 June 15, 2006

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