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Ordering number : ENA0604
LB11921T
Overview
Monolithic Digital IC
Three-Phase Brushless Motor Driver
The LB11921T is a pre-driver IC designed for variable-speed control of 3-phase brushless motors. It can be used to implement a motor drive circuit with the desired output capacity (voltage, current) by using discrete transistors for the output stage. It implements direct PWM drive for minimal power loss. Since the LB11921T includes a built-in VCO circuit, applications can control the motor speed arbitrarily by varying the external clock frequency.
Functions
* Direct PWM drive output * Speed discriminator + PLL speed control circuit * Speed lock detection output * Built-in VCO circuit * Forward/reverse switching circuit * Braking circuit (short braking) * Full complement of on-chip protection circuits, including lock protection, current limiter, and thermal shutdown protection circuits.
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Output current Allowable power dissipation 1 Allowable power dissipation 2 Operating temperature Storage temperature Symbol VCC max IO max Pd max1 Pd max2 Topr Tstg UH, VH, WH, UL, VL, WL output Independent IC Mounted on a circuit board* Conditions Ratings 8 10 0.4 0.9 -20 to +80 -55 to +150 Unit V mA W W C C
* Mounted on a specified board: 114.3mmx76.1mmx1.6mm, glass epoxy.
Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein.
11707 MS IM 20060327-S00010 No.A0604-1/18
LB11921T
Allowable Operating Ranges at Ta = 25C
Parameter FG Schmitt output applied voltage FG Schmitt output current Lock detection applied voltage Lock detection output current Supply voltage Symbol VFGS IFGS VLD ILD VCC Conditions Ratings 0 to 7 0 to 5 0 to 7 0 to 20 4.4 to 7.0 Unit V mA V mA V
Electrical Characteristics at Ta = 25C, VCC = 5V
Parameter Supply current 1 Supply current 2 Output Block Output saturation voltage 1-1 Output saturation voltage 1-2 Output saturation voltage 2-1 Output saturation voltage 2-2 Hall Amplifier Input bias current Common-mode input voltage range 1 Common-mode input voltage range 2 Hall input sensitivity Hysteresis Input voltage low high Input voltage high low PWM Oscillator Output high-level voltage Output low-level voltage Oscillator frequency Amplitude CSD Oscillator Output high-level voltage Output low-level voltage External capacitor charge current External capacitor discharge current Oscillator frequency Amplitude VCO Oscillator C pin Output high-level voltage Output low-level voltage Oscillator frequency Amplitude VOH(C) VOL(C) f(C) V(C) 0.3 0.5 2.00 1.55 2.30 1.80 2.55 2.05 1.2 0.7 V V MHz Vp-p VOH(CSD) VOL(CSD) ICHG1 ICHG2 f(RK) V(RK) C = 0.047F 2.1 3.15 0.9 -9.0 2.4 3.5 1.1 -6.5 4.0 20 2.4 2.65 3.85 1.3 -3.9 6.0 V V A A Hz Vp-p VOH(PWM) VOL(PWM) f(PWM) V(PWM) C = 680pF 1.1 2.75 1.45 3.0 1.65 23 1.35 1.6 3.25 1.9 V V kHz Vp-p VIN(HA) VSLH VSHL IHB(HA) VICM1 VICM2 When Hall-effect sensors are used When one-side biased inputs are used (Hall-effect IC applications) Sine wave 50 9 4 -13 15 7 -8 26 13 -4 mVp-p mV mV mV -2 0.5 0 -0.1 VCC-2.0 VCC A V V VOsat1-1 VOsat1-2 VOsat2-1 VOsat2-2 At low level: IO = 500A At low level: IO = 5mA At high level: IO = -500A At high level: IO = -5mA VCC-0.2 VCC-0.4 0.1 0.3 VCC-0.1 VCC-0.2 0.2 0.5 V V V V Symbol ICC1 ICC2 In stop mode Conditions min Ratings typ 23 2.1 max 32 2.9 mA mA unit
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No.A0604-2/18
LB11921T
Continued from preceding page.
Parameter Current Limiter Operation Limiter Thermal Shutdown Operation Thermal shutdown operating temperature Hysteresis Low-voltage Protection Circuit Operating voltage Release voltage Hysteresis FG Amplifier Input offset voltage Input bias current Output high-level voltage Output low-level voltage FG input sensitivity Schmitt amplitude for the next stage Operating frequency range Open-loop gain Reference voltage FGS Output Output saturation voltage Output leakage current Speed Discriminator Output Output high-level voltage Output low-level voltage Counts Speed Control PLL Output Output high-level voltage Output low-level voltage Lock Detection Output saturation voltage Output leakage current Lock range Integrator Input offset voltage Input bias current Output high-level voltage Output low-level voltage Open-loop gain Gain-bandwidth product Reference voltage VB(INT) Design target value * -5% VIO(INT) IB(INT) VOH(INT) VOL(INT) IINTI = -0.1mA, No load IINT = 0.1mA, No load -10 -0.4 3.45 1.1 45 3.7 1.3 51 1.0 VCC/2 5% 10 0.4 3.95 1.5 mV A V V dB MHz V VOL(LD) IL(LD) ILD = 10mA VO = VCC -6.25 0.25 0.4 10 +6.25 V A % VOH(P) VOL(P) 3.25 1.25 3.50 1.60 3.85 1.85 V V VOH(D) VOL(D) VCC-1.0 VCC-0.7 0.8 512 1.1 V V VO(FGS) IL(FGS) IO(FGS) =2mA VO = VCC 0.2 0.4 10 V A VB(FG) f(FG) = 2kHz 45 -5% 51 VCC/2 5% VIO(FG) IB(FG) VOH(FG) VOL(FG) IFGI = -0.1mA, No load IFGI = 0.1mA, No load Gain: 100x -10 -1 3.6 0.7 3 100 180 250 2.34 3.95 1.05 10 1 4.3 1.4 mV A V V mV mV kHz dB V VSDL VSDH VSD 3.40 3.55 0.12 3.74 3.93 0.19 4.00 4.23 0.26 V V V TSD Design target value * 30 C TSD Design target value * 150 180 C VRF 0.24 0.26 0.28 V Symbol Conditions min Ratings typ max unit
*: Design target value and no measurement was made.
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No.A0604-3/18
LB11921T
Continued from preceding page.
Parameter FIL Output Output source current Output sink current S/S Pin Input high-level voltage Input low-level voltage Input open voltage Hysteresis Input high-level current Input low-level current Pull-up resistance F/R Pin Input high-level voltage Input low-level voltage Input open voltage Hysteresis Input high-level current Input low-level current Pull-up resistance BR Pin Input high-level voltage Input low-level voltage Input open voltage Hysteresis Input high-level Input low-level current Pull-up resistance CLK Pin Input high-level voltage Input low-level voltage Input open voltage Hysteresis Input high-level current Input low-level current Input frequency Pull-up resistance VIH(CLK) VIL(CLK) VIO(CLK) VIN(CLK) IIH(CLK) IIL(CLK) f(CLK) RU(CLK) 37 53.5 Design target value * VCLK = VCC VCLK = 0V 2.0 0 VCC-0.5 0.13 -10 -135 0.22 0 -93 2.34 70 VCC 1.0 VCC 0.31 10 V V V V A A kHz k VIH(BR) VIL(BR) VIO(BR) VIN(BR) IIH(BR) IIL(BR) RU(BR) VBR = VCC VBR = 0V 2.0 0 VCC-0.5 0.13 -10 -135 37 0.22 0 -93 53.5 70 VCC 1.0 VCC 0.31 10 V V V V A A k VIH(F/R) VIL(F/R) VIO(F/R) VIN(F/R) IIH(F/R) IIL(F/R) RU(F/R) VF/R = VCC VF/R = 0V 2.0 0 VCC-0.5 0.13 -10 -135 37 0.22 0 -93 53.5 70 VCC 1.0 VCC 0.31 10 V V V V A A k VIH(S/S) VIL(S/S) VIO(S/S) VIN(S/S) IIH(S/S) IIL(S/S) RU(S/S) VS/S = VCC VS/S = 0V 2.0 0 VCC-0.5 0.13 -10 -135 37 0.22 0 -93 53.5 70 VCC 1.0 VCC 0.31 10 V V V V A A k IOH(FIL) IOL(FIL) -17 7 -13 12 -7 17 A A Symbol Conditions min Ratings typ max unit
*: Design target value and no measurement was made.
No.A0604-4/18
LB11921T
Package Dimensions
unit : mm (typ) 3253B
9.75 36 19
1.2
Pd max - Ta
Mounted on a specified board: 114.3mmx76.1mmx1.6mm, glass epoxy
Allowable Power Dissipation, Pd max - W
1.0 0.9 0.8
5.6
7.6
0.5
0.6 0.504
(0.5) (0.63)
1 0.18
18 0.15
Independent IC
0.4
(1.0)
1.2max
0.2
0.224
0.08
0 -20
0
20
40
60
80
100 ILB01797
Ambient Temperature, Ta -C
SANYO : TSSOP36(275mil)
Pin Assignment
RFGND FGIN+ 20 17 NC IN1+ IN3+ IN1UH GND IN2FGIN19 18 FGOUT Top view No.A0604-5/18 IN2+ VCC IN3WH WL VH
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
RF 15 C
-
UL
VL
21
LB11921T
1 S/S
2 CLK
3 F/R
4 BR
5 FGS
6 LD
7 DOUT
8 POUT
9 INT.REF
10 INT.IN
11 INT.OUT
12 PWM
13 FIL
14 R
16 CSD
Three-Phase Logic Truth Table (A high (H) input is the state where IN+ > IN-.)
F/R=L IN1 1 2 3 4 5 6 H H H L L L IN2 L L H H H L IN3 H L L L H H IN1 L L L H H H F/R=H IN2 H H L L L H IN3 L H H H L L PWM VH WH WH UH UH VH Output
UL UL VL VL WL WL
LB11921T
Block Diagram
IN1+ IN1IN2+ IN2CSD IN3+ IN3-
VCC CSD OSC F/R F/R HALL HYS AMP LOGIC
WH VH PRI DRIVER UH WL VL UL
LOGIC BR BR TSD S/S INT OUT RES
RF COMP CURR LIM RFGND + S/S
INT IN INT REF POUT
1.3VREF PWM OSC PWM
VCC LVSD
LD
LD SPEED DISCRI SPEED PLL
DOUT
1/512
FGS
FG FILTER R VCO PLL VCO C FIL
FGOUT CLK VCC + FIL
+
-
GND
FGIN+
FGIN-
CLK
No.A0604-6/18
LB11921T
Pin Functions
Pin No. 1 Symbol S/S Start/stop control Low: 0V to 1.0V
50k 3.5k 1
Pin Description
VCC
Equivalent Circuit
High: 2.0V to VCC Goes high when left open. Low for start. The hysteresis is about 0.22V
2
CLK
External clock signal input Low: 0V to 1.0V High: 2.0V to VCC Goes high when left open. The hysteresis is about 0.22V. f = 2.34kHz, maximum
50k 3.5k 2
VCC 50k 3.5k 3 VCC 50k 3.5k 4
VCC
3
F/R
Forward/reverse control Low: 0V to 1.0V High: 2.0V to VCC Goes high when left open. Low for forward. The hysteresis is about 0.22V.
4
BR
Brake pin (short braking operation) Low: 0V to 1.0V High: 2.0V to VCC Goes high when left open. High or open for brake mode operation. The hysteresis is about 0.22V.
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No.A0604-7/18
LB11921T
Continued from preceding page.
Pin No. 5 Symbol FGS Pin Description FG schmitt comparator circuit output This is an open collector output.
5 VCC
Equivalent Circuit
6
LD
Speed lock detection output Goes low when the motor speed is within the speed lock range (6.25%).
VCC
6
7
DOUT
Speed discriminator output Acceleration high, deceleration low
V CC
7
8
POUT
Speed control system PLL output Outputs the phase comparison result for CLK and FG.
VCC
8
9
INT REF
Integrating amplifier non-inverting input (1/2 VCC potential)
VCC
10
INT IN
Integrating amplifier inverting input
30k 500 9 30k
500 10
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No.A0604-8/18
LB11921T
Continued from preceding page.
Pin No. 11 Symbol INT OUT Pin Description Integrating amplifier output
VCC
Equivalent Circuit
11 40k
12
PWM
PWM oscillator frequency setting. Connect a capacitor between this pin and ground.
VCC
300 12 7.5k
13
FIL
VCO system PLL output filter connection
VCC
300 13
14
R
Set the value of the charge/discharge current from the VCO circuit C pin. Insert a resistor between this pin and ground.
VCC
300 14
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No.A0604-9/18
LB11921T
Continued from preceding page.
Pin No. 15 Symbol C Pin Description VCO oscillator connection Insert a capacitor between this pin and ground. The oscillation frequency of the C pin must not exceed 1.2MHz.
VCC
Equivalent Circuit
300 15
16
CSD
Set the operating time of the constrained-rotor protection circuit. Insert a capacitor between this pin and ground. This pin also functions as the logic circuit block power-on reset pin.
300 16 VCC Reset circuit
17 18
NC FGOUT
There is unconnected pin, and can be used for wiring. FG amplifier output This pin is connected to the FG Schmitt comparator circuit internally in the IC.
VCC
18 40k FG Schmitt comparator
19 20
FGINFGIN
+
FG amplifier inverting input
VCC 300 FGOUT
FG amplifier noninverting input. The 1/2 VCC potential.
20k 500 20 20k
Insert a capacitor between this pin and ground.
500 19
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No.A0604-10/18
LB11921T
Continued from preceding page.
Pin No. 21 Symbol RF GND Pin Description Output current detection reference Connect to GND of the external resistor Rf.
VCC
Equivalent Circuit
21
22
RF
Output current detection Connect a low resistance resistor Rf between this pin and Rf GMD pin. This resistor sets the maximum output current IOUT to be 0.26/Rf.
VCC
22
23 24 25 26 27 28 29
GND UL UH VL VH WL WH
GND pin Outputs (that are used to drive external transistors). Duty cycle is controlled on the UH, VH, and WH side of these output. 24 26 28 50k 25 27 29 VCC
30
VCC
Power supply Connect a capacitor between this pin and ground for stabilization.
31 32 33 34 35 36
IN3IN3+ IN2IN2+ IN1IN1+
Hall-effect device inputs. The input is seen as a high-level input when IN+ > IN-, and as a low-level input for the opposite state. If noise on the Hall-effect device signals is a problem, insert capacitors between the corresponding IN+ and IN- inputs.
VCC
500 32 34 36
500 31 33 35
No.A0604-11/18
LB11921T
Sample Application Circuit 1 (P-channel + N-channel, Hall-effect sensor application)
24V
5V
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
IN2-
IN1+
UH
GND
IN3+
WH
IN1-
IN3-
RF
UL
VL
FGIN+
17
LB11921T
INT.REF INT.OUT INT.IN PWM CSD FGOUT
18
DOUT
S/S
POUT
FGS
CLK
F/R
BR
RFGND
FIL
R
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
S/S CLK F/R
BR FGS LD
NC
LD
FGIN-
IN2+
VCC
WL
VH
No.A0604-12/18
LB11921T
Sample Application Circuit 2 (PNP + NPN, Hall-IC application)
24V
5V
36 IN1+
35 IN1-
34 IN2+
33 IN2-
32 IN3+
31 IN3-
30 VCC
29 WH
28 WL
27 VH
26 VL
25 UH
24 UL
23 GND
22 RF
21 RFGND
20 FGIN+ 17 NC
19 FGIN18 FGOUT
LB11921T
INT.REF INT.IN INT.OUT DOUT POUT PWM FGS CSD 16 CLK S/S F/R BR FIL LD
R 14
1
2
3
4
5
6
7
8
9
10
11
12
13
15
S/S CLK F/R BR FGS LD
C
No.A0604-13/18
LB11921T
LB11921T Overview
1. Speed Control Circuit This IC implements speed control using the combination of a speed discriminator circuit and a PLL circuit. The speed discriminator circuit outputs (This counts a single FG period.) an error signal once every two FG periods. The PLL circuit outputs an error signal once every one FG Period. As compared to the earlier technique in which only a speed discriminator circuit was used, the combination of a speed discriminator and a PLL circuit allows variations in motor speed to be better suppressed when a motor that has large load variations is used. The FG servo frequency (fFG) is controlled to have the equal frequency with the clock signal (fCLK) which is input through the CLK pin. fFG = fCLK 2. VCO Circuit The LB11921T includes a built-in VCO circuit to generate the speed discriminator circuit reference signal. The reference signal frequency is given by the following formula. fVCO = fCLK x 512 fVCO: Reference signal frequency fCLK: Externally input clock frequency The range over which the reference signal frequency can be varied is determined by the resistor and capacitor components connected to the R and C pins (pins 14 and 15) and by the VCO loop filter constant (the values of the external components connected to pin 13). Reference value at VCC = 5V
fFG in the high-speed rotation mode 1.5kHz 2.0kHz R(k) 5.6 5.6 C(pF) 330 220
The components connected to the R, C, and FIL pins must be connected with lines to their ground pin (pin 23) that are as short as possible. 3. Output Drive Circuit To reduce power loss in the output, this IC adopts the direct PWM drive technique. The output transistors (which are external to the IC) are always saturated when on, and the motor drive output is adjusted by changing the duty with which the output is on. The PWM switching is performed on the UH, VH, and WH pins. The PWM switching side in the output can be selected to be either the high or low side depending on how the external transistors are connected. 4. Current Limiter Circuit The current limiter circuit limits the (peak) current at the value I = VRF/Rf (VRF = 0.26V (typical), Rf: current detection resistor). The current limitation operation consists of reducing the output duty to suppress the current. High accuracy detection can be achieved by connecting the RF and RFGND pin lines near the ends of the current detection resistor (Rf). 5. Speed Lock Range The speed lock range is 6.25% of the fixed speed. When the motor speed is in the lock range, the LD pin (an open collector output) goes low. If the motor speed goes out of the lock range, the motor on duty is adjusted according to the speed error to control the motor speed to be within the lock range. 6. Notes on the PWM Frequency The PWM frequency is determined by the capacitor (F) connected to the PWM pin. fPWM 1/(64000 x C) A PWM frequency of between 15 and 25kHz is desirable. If the PWM frequency is too low, the motor may resonate at the PWM frequency during motor control, and if that frequency is in the audible range, that resonation may result in audible noise. If the PWM frequency is too high, the output transistor switching loss will increase. To make the circuit less susceptible to noise, the connected capacitors must be connected to the GND pin (pin 23) with lines that are as short as possible.
No.A0604-14/18
LB11921T
7. Hall effect sensor input signals An input amplitude of over 100mVp-p is desirable in the Hall effect sensor inputs. The closer the input waveform is to a square wave, the lower the required input amplitude. Inversely, a higher input amplitude is required the closer the input waveform is to a triangular wave. Also note that the input DC voltage must be set to be within the commonmode input voltage range. If noise on the Hall inputs is a problem, that noise must be excluded by inserting capacitors across the inputs. Those capacitors must be located as close as possible to the input pins. When the Hall inputs for all three phases are in the same state, all the outputs will be in the off state. If a Hall sensor IC is used to provide the Hall inputs, those signals can be input to one side (either the + or - side) of the Hall effect sensor signal inputs as 0 to VCC level signals if the other side is held fixed at a voltage within the common-mode input voltage range that applies when a Hall effect sensors are used. 8. Forward/Reverse Switching The motor rotation direction can be switched using the F/R pin. However, the following notes must be observed if the motor direction is switched while the motor is turning. * This IC is designed to avoid through currents when switching directions. However, increases in the motor supply voltage (due to instantaneous return of motor current to the power supply) during direction switching may cause problems. The values of the capacitors inserted between power and ground must be increased if this increase is excessive. * If the motor current after direction switching exceeds the current limit value, the PWM drive side outputs will be turned off, but the opposite side output will be in the short-circuit braking state, and a current determined by the motor back EMF voltage and the coil resistance will flow. Applications must be designed so that this current does not exceed the ratings of the output transistors used. (The higher the motor speed at which the direction is switched, the more severe this problem becomes.) 9. Brake Switching The LB11921T provides a short-circuit brake implemented by turning the output transistors for the UH, VH, and WH pins for all phases on. (The opposite side transistors are turned off for all phases.) Note that the current limiter does not operate during braking. During braking, the duty is set to 100%, regardless of the motor speed. The current that flows in the output transistors during braking is determined by the motor back EMF voltage and the coil resistance. Applications must be designed so that this current does not exceed the ratings of the output transistors used. (The higher the motor speed at which braking is applied, the more severe this problem becomes.) The braking function can be applied and released with the IC in the start state. This means that motor startup and stop control can be performed using the brake pin with the S/S pin held at the low level (the start state). If the startup time becomes excessive, it can be reduced by controlling motor startup and stop with the brake pin rather than with the S/S pin. (Since the IC goes to the power saving state when stopped, enough time for the VCO circuit to stabilize will be required at the beginning of the motor start operation.) 10. Constraint Protection Circuit The LB11921T includes an on-chip constraint protection circuit to protect the IC and the motor in motor constraint mode. If the LD output remains high (indicating the unlocked state) for a fixed period in the start state, the PWM output (external) transistors are turned off. This time is set by the capacitance of the capacitor attached to the CSD pin. The set time (in seconds) is 15.1 x C (F) To clear the motor constrained protection state, the application must either switch to the stop or brake state for a fixed period (about 1ms or longer), or the power must be turned off and reapplied. If the motor constrained protection circuit is not used, a 360k resistor and a 3300pF capacitor must be connected in parallel between the CSD pin and ground. However, in that case, the clock disconnect protection circuit described below will no longer function. Since the CSD pin also functions as the power-on reset pin, if the CSD pin were connected directly to ground, the IC would go to the power-on reset state and motor drive operation would remain off. The power-on reset state is cleared when the CSD pin voltage rises above a level of about 0.25V. 11. Clock Disconnect Protection Circuit If the clock input goes to the no input state when the IC is in the start state, this protection circuit will operate and turn off the PWM output. If the clock is resupplied before the motor constraint protection circuit operates, the IC will return to the drive state, but if the motor constraint protection circuit does operate, the IC must either be set temporarily (approximately 1 ms or over) to the stop or brake state, or the power must be turned off and reapplied.
No.A0604-15/18
LB11921T
12. Low-Voltage Protection Circuit The LB11921T includes a low-voltage protection circuit to protect against incorrect operation when VCC power is applied or if the power supply voltage falls below its operating level. The (external) all output transistors are turned off if VCC falls under about 3.74 volts, and the protection function is cleared at about 3.93 volts or higher. 13. Power Supply Stabilization Since this IC is used in applications that draw large output currents, the power-supply line is subject to fluctuations. Therefore, capacitors with capacitances adequate to stabilize the power-supply voltage must be connected between the VCC pin and ground. If diodes are inserted in the power-supply line to prevent IC destruction due to reverse power supply connection, since this makes the power-supply voltage even more subject to fluctuations, even larger capacitors will be required. 14. Ground Lines The signal system ground and the output system ground must be separated and a single ground point must be taken at the connector. Since the output system ground carries large currents, this ground line must be made as short as possible. Output system ground --- Ground for Rf, output diodes, and 24V line capacitors Signal system ground --- Ground for the IC, external components, and 5V line capacitors 15. FG Amplifier The FG amplifier is normally implemented as a filter amplifier such as that shown in the application circuits to reject noise. Since a clamp circuit has been added at the FG amplifier output, the output amplitude is clamped at about 3Vp-p, even if the gain is increased. Since a Schmitt comparator is inserted after the FG amplifier, applications must set the gain so that the amplifier output amplitude is at least 250mVp-p. (It is desirable that the gain be set so that the amplitude is over 0.5Vp-p at the lowest controlled speed to be used.) The capacitor inserted between the FGIN+ pin (pin 20) and ground is required for bias voltage stabilization. To make the connected capacitor as immune from noise as possible, connect this capacitor to the GND pin (pin 23) with a line that is as short as possible. 16. Integrating Amplifier The integrating amplifier integrates the speed error pulses and phase error pulses and converts them to the speed controlling voltage. At the same time it also sets the control loop gain and frequency characteristics. External components necessary for the integrating amplifier must be placed as close to the IC as possible to reduce influence of noise. 17. FIL Pin External Components The capacitor inserted between the FIL pin and ground is used to suppress ripple on the FIL pin voltage. Therefore, application designers must select a capacitance value that provides fully adequate smoothing of the FIL pin voltage even at the lowest external clock input frequency used. Also, the FIL pin voltage convergence time (the time until the reference signal stabilizes) when the input clock frequency is switched is shortened by connecting a resistor and a capacitor in series between the FIL pin and ground. Therefore, designers must select values for the resistor and capacitor that give the required convergence time.
No.A0604-16/18
LB11921T
18. R and C Pin External Components The maximum range over which the reference signal frequency fVCO can be varied when 5V is used as the VCC supply voltage is about a factor of three. When it is desirable to make this range as wide as possible, since the values of the R pin external resistor (R) and the C pin external capacitor (C) are determined by the maximum value of the reference signal frequency (fVCO1) and the minimum value (VCCL) of the VCC power supply due to unit-to-unit variations, R and C can be determined using the following procedure as a reference. (1) Calculate R1 and C1 using the following formulas and determine values for R and C such that the conditions R R1 and C C1 will hold taking the sample-to-sample variations (including other issues such as temperature characteristics) into account. R1 = (VCCL-2.2 V)/370A C1 = (370A /0.9V) x (1/fVCO1) x 0.7 (2) The minimum value (fVCO2) for the reference signal frequency that can be set for the R and C values determined in step (1) can be calculated from the following formula if we let R2 and C2 be the smallest values for R and C due to the sample-to-sample variations (including other issues such as temperature characteristics). Therefore, the range over which the reference signal frequency can be set is fVCO1 to fVCO2. fVCO2 = 0.38/(R2 x C2) (3) The following are the conditions that must be met and the points that require care when determining the values of the external components connected to the R and C pins. 1. The maximum value of the set reference signal frequency must not exceed 1.2MHz. 2. The R pin voltage and the FIL pin voltage must be in the range 0.3V to (VCCL-2.2V). (VCCL is the lowest value of the VCC supply voltage given the unit-to-unit variations. VCCL is always greater than or equal to 4.4V.) However, the lower the R pin voltage, the more susceptible the system will be to ground line noise, and the reference signal frequency may become unstable as a result. Therefore the lower end of the R pin voltage range must not be used if there is much ground line noise in the system. 3. Set the value of the R pin external resistor to a value in the range 5.6k to 10k. Also, assure that the R pin current remains under 370A. 4. Set the value of the C pin external capacitor to a value in the range 220pF to 1000pF. 5. When it is desirable to make the range of the reference signal frequency as wide as possible, set the values of R and C to the largest possible values. (However, those values must be lower than the calculated values R1 and C1.) Use components with the smallest sample-to-sample variations possible. The VCC voltage must be made as much higher than 5V as possible to acquire the widest possible range for the reference signal frequency. 19. NC pin Since the NC pins are electrically open with respect to the IC itself, they can be used as intermediate connection points for lines in the PCB pattern.
No.A0604-17/18
LB11921T
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of January, 2007. Specifications and information herein are subject to change without notice.
PS No.A0604-18/18

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