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Triple, 6-Channel LCD Timing Delay-Locked Loop AD8389
PRODUCT FEATURES
High speed Up to 85 MHz clock rate Triple (R, G, B) output Matched delay lines Low power dissipation: 40 mW Reference to rising or falling edge of MONITI input Selectable loop delay Available in 48-lead 7 mm x 7 mm LFCSP
PRODUCT DESCRIPTION
The AD8389 is a triple 6-channel LCD microdisplay delaylocked timing loop. As part of a closed-loop system, the AD8389 maintains a constant delay between the common input, DXI, and each independent feedback reference, MONITxI. The AD8389 consists of a selectable fixed delay element, a phase detector, a charge pump, and six matched variable delay lines per color. The phase detector, charge pump, and master delay line form a closed loop when connected to a compatible LCD microdisplay. Five additional delay lines track the master for a complete set of matched timing signals. The AD8389 dissipates 40 mW nominal power. The AD8389 is offered in a 48-lead 7 mm x 7 mm LFCSP package and operates over the commercial temperature range of 0C to 85C.
APPLICATIONS
LCD microdisplay horizontal timing
FUNCTIONAL BLOCK DIAGRAM
AVDD(4) AVSS(4) DRVDD(2) DRVSS(2)
AD8389
COMPEDGE SLOW SELECTABLE DELAY PHASE DETECTOR CHARGE PUMP VCONTR
MONITRI DXRO ENBX1RO ENBX2RO ENBX3RO ENBX4RO CLXRO VCONTG
DXI ENBX1I ENBX2I ENBX3I ENBX4I CLXI
DXI
MATCHED VARIABLE DELAY LINES (6-CHANNEL)
6
/
6
/
PHASE DETECTOR
CHARGE PUMP
MONITGI DXGO ENBX1GO ENBX2GO ENBX3GO ENBX4GO CLXGO VCONTB
MATCHED VARIABLE DELAY LINES (6-CHANNEL)
6
/
PHASE DETECTOR
CHARGE PUMP
MONITBI DXBO ENBX1BO ENBX2BO ENBX3BO ENBX4BO CLXBO
MATCHED VARIABLE DELAY LINES (6-CHANNEL) CLK INTERNAL TIMING
6
/
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
04515-0-001
AD8389 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 Exposed Paddle............................................................................. 4 Maximum Power Dissipation ..................................................... 4 Pin Configuration and Function Descriptions............................. 5 Timing.................................................................................................6 Operating Principles .........................................................................7 Operation .......................................................................................7 Outline Dimensions ..........................................................................9 Ordering Guide .............................................................................9
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 12
AD8389 SPECIFICATIONS
Table 1. @ 25C, AVDD = DRVDD = 3.3 V, TMIN = 0C, TMAX = 85C, unless otherwise noted
Parameter LOGIC INPUTS CIN IIN VIH VIL VTH OUTPUTS VOH VOL TIMING SPECIFICATIONS Operating Frequency CLK, fCLK CLXI, ENBX(1-4)I DXI, MONITxI Input Low Pulse Width, t1--All Inputs except CLK DXI, MONITxI ENBX(1-4)I, CLXI CLK High Pulse Width, t2 CLK Low Pulse Width, t3 CLK to DXI Setup Time, t4 Output Rise, Fall Times--tr, tf Delay t5 Output Skew, t6 t5 130 ns t5 170ns t5 230ns Loop Delay, t7 COMPEDGE = H, SLOW = H COMPEDGE = H, SLOW = L COMPEDGE = L, SLOW = H COMPEDGE = L, SLOW = L POWER SUPPLIES AVDD Operating Range DRVDD Operating Range Total Operating Current Power Dissipation Operating Temperature Conditions Min Typ Max Unit pF A V V V V V
-2 2.0 AGND 1.5 IO = -2 A IO = +2 A DRVDD - 0.4
+2 AVDD 0.8
DVRSS + 0.4
60
75
85 (2t1)-1 (2t1)-1
MHz Hz Hz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
t5 230ns
280 30 4.7 4.7 2 22 0.3 0.45 0.7 9/(fCLK) + t4 15/(fCLK) + t4 26/(fCLK) + t4 32/(fCLK) + t4 3 3 3.6 3.6 11 40 0 85 5 350 2.5 3.4 5
CL = 30 pF DXI to DXxO CL = 30 pF
fCLK = 75 MHz, CL = 30 pF fCLK = 75 MHz, CL = 30 pF
V V mA mW C
Rev. 0 | Page 3 of 12
AD8389 ABSOLUTE MAXIMUM RATINGS
Table 2. AD8389 Stress Ratings1
Parameter Supply Voltages AVDDx - AVSSx DRVDDx - DRVSSx Input Voltages Maximum Digital Input Voltage Minimum Digital Input Voltage Internal Power Dissipation2 LFCSP Package @ TA = 25C Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 10 sec)
1
EXPOSED PADDLE
Rating 3.9 V 3.9 V AVDD + 0.3 V AVSS - 0.3 V 4.8 W 0C to 85C -65C to +125C 300C
To ensure high reliability, the exposed paddle must be soldered to GND.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8389 is limited by its junction temperature. The maximum safe junction temperature for plastic encapsulated devices as determined by the glass transition temperature of the plastic is approximately 150C. Exceeding this limit temporarily may cause a shift in the parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. To ensure operation within the specified operating temperature range, it is necessary to limit the maximum power dissipation as follows: PDMAX = (TJMAX - TA)/JA
5.0
Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum ratings for extended periods may reduce device reliability. 2 48-Lead LFCSP Package: JA = 26C/W (JEDEC Standard 4-layer PCB in still air) JC = 20C/W
4.5
POWER DISSIPATION (W)
4.0
3.5
3.0
2.5
25
35
45
55
65
75
85
95
AMBIENT TEMPERATURE (C)
Figure 2. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 4 of 12
04515-0-002
2.0
AD8389 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
47 COMPEDGE 45 ENBX4I 44 ENBX3I 43 ENBX2I 42 ENBX1I 38 DRVDD 37 DRVSS 40 SLOW 48 AVDD 46 CLXI 39 CLK 41 DXI
AVSS 1 MONITRI 2 MONITGI 3 MONITBI 4 AVDD 5 AVSS 6 VCONTR 7 AVDD 8 AVSS 9 VCONTG 10 VCONTB 11 AVSS 12
PIN 1 INDICATOR
36 35 34 33
DXRO ENBX1RO ENBX2RO ENBX3RO ENBX4RO CLXRO DXGO ENBX1GO ENBX2GO ENBX3GO ENBX4GO CLXGO
AD8389
TOP VIEW (Not to Scale) 48-LEAD LFCSP 7mm x 7mm
32 31 30 29 28 27 26 25
AVDD 13
NC 14
NC 15
DRVDD 16
DRVSS 17
CLXBO 18
ENBX4BO 19
ENBX3BO 20
ENBX2BO 21
ENBX1BO 22
DXBO 23
NC 24
NC = NO CONNECT
Figure 3. 48-Lead LFCSP, 7 mm x 7 mm Pin Configuration
Table 3. Pin Function Descriptions
Mnemonic AVDD, DRVDD AVSS, DRVSS CLK COMPEDGE Function Power Supply Ground Clock Edge Select Description Power Supply. Ground. Clock Input. Active edge is the rising edge. When set HIGH, the phase detector compares the falling edge of DXIN with the rising edge of MONITxI. When set LOW, the phase detector compares the rising edge of DXIN with the falling edge of MONITxI. When set HIGH and COMPEDGE = HIGH, the delay between the falling edges of DXI and the rising edges of MONITI is maintained at 9/(fCLK) + t4. The delay is maintained at 26/(fCLK) + t4 when COMPEDGE = LOW. When set LOW and COMPEDGE = HIGH, the delay between the falling edges of DXI and the rising edges of MONITI is maintained at 15/(fCLK) + t4. The delay is maintained at 32/(fCLK) + t4 with COMPEDGE = LOW. LCD Timing Input from the Image Processor. Used as the input to all phase detectors. LCD Timing Input from the Image Processor. LCD Timing Inputs from the Image Processor. Inputs from the LCD. Used as the feedback input to each phase detector. When the AD8389 forms part of a closed loop, it maintains a constant delay between the DXI input and this reference input pin.
SLOW
Delay Select
DXI CLXI ENBX(1-4)I MONITxI
Reference Input Input Inputs Feedback Inputs
DXxO CLXxO ENBX(1-4)xO VCONTx
Delayed Outputs Delayed Outputs Delayed Outputs Control Voltage
200 pF capacitors connected between these pins and the AVSS plane are required for proper operation of the internal charge pump.
Rev. 0 | Page 5 of 12
04515-0-003
AD8389 TIMING
Table 4. Timing Specifications
Parameter Operating Frequency CLK, fCLK CLXI, ENBX(1-4)I DXI, MONITxI Input Low Pulse Width, t1--All Inputs except CLK DXI, MONITxI ENBX(1-4)I, CLXI CLK High Pulse Width--t2 CLK Low Pulse Width--t3 CLK to DXI Setup Time--t4 Output Rise, Fall Time--tr, tf Delay--t5 Output Skew-- t6 t5 130 ns t5 170ns t5 230ns Loop Delay, t7 COMPEDGE = H, SLOW = H COMPEDGE = H, SLOW = L COMPEDGE = L, SLOW = H COMPEDGE = L, SLOW = L
t3 t2
CLK VTH
MONITxI DXI
Conditions
Min 60
Typ 75
Max 85 (2t1)-1 (2t1)-1
Unit MHz Hz Hz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
t5 230ns
280 30 4.7 4.7 2 22 0.3 0.45 0.7 9/(fCLK) + t4 15/(fCLK) + t4 26/(fCLK) + t4 32/(fCLK) + t4 5 350 2.5 3.4 5
CL = 30 pF DXI to DXxO CL = 30 pF
t7
t4
DXI
t4
VTH
04515-0-004
tEXT
DXO
t5
t1
Figure 4. CLK and DXI Timing
04515-0-005
DXxO CLXxO ENBX(1-4)XO
t6
Figure 5. Input and Output Waveforms at COMPEDGE = HIGH
Rev. 0 | Page 6 of 12
AD8389 OPERATING PRINCIPLES
MON MONITRI DX CLX, ENBX(1-4) VCONTR 200pF DXI DXRO CLXRO, ENBX(1-4)O MONITO DXI CLXIN, ENBX(1-4)I MONITI DXO CLXO, ENBX(1-4)O H SHIFT REGISTER
04515-0-006
AD8389
AD8384/AD8385
LEVEL SHIFTER SECTION
RED LCD
Figure 6. AD8389 Application in the Red Channel of an LCD Projection System
The image quality of an LCD system is dependent on the timing relationship between the control inputs, DX, CLX, ENBX(1-4), and the video channels. TFT delay and switching speed variations, due to temperature variations and LCD aging, degrade image quality if not compensated. An internal reference TFT connected to an internal pull-up resistor, as shown in Figure 6, characterizes the internal S/H TFTs of the LCD and monitors switching speed and delay variations due to aging and temperature. When the MON output of an LCD that includes such an internal reference TFT is connected to the reference input of the AD8389 delay-locked timing loop, continuously optimized timing of the LCD is maintained automatically.
OPERATION
As part of a closed loop, the AD8389 maintains a constant delay between the common input, DXI, and each independent feedback reference, MONITxI. The block diagram of such closed-loop system is shown in Figure 6. A constant delay, t7, selected via the COMPEDGE and SLOW control inputs, is applied to the DXI input to approximate the nominal, initially expected total delay, t7, through the level shifters and the LCD as shown in Table 5. Table 5
COMPEDGE 1 1 0 0 SLOW 0 1 0 1 Constant Delay 15/fCLK + t4 9/fCLK + t4 32/fCLK + t4 26/fCLK + t4
DX CONSTANT
MONITRI CONSTANT DX MONITRI
Rev. 0 | Page 7 of 12
AD8389
The phase detector compares the delayed DX and MONITxI reference inputs and automatically adjusts the variable delay (t5), maintaining the constant delay (t7) between the active edges of DX and MONITxI. Five matched delay lines maintain the phase relationship between DXxO, CLXxO, and ENBX(1-4)xO. When the loop is locked, t7 = t5 + tEXT, where tEXT is the total delay through the level shifter and the LCD. The external delay of a typical system is the sum of the level shifter delay (20 ns typical) and the LCD delay, (typically in the range of 20 ns to 120 ns). At a 75 MHz operating clock frequency, the maximum expected total delay of 140 ns is equal to 10.5 clock cycles, requiring COMPEDGE = 1, SLOW = 0 for systems using negative active edge for DX.
CLK CONSTANT DX MONITRI
AD8389 INPUTS LCD INPUTS AND OUTPUT
CLX ENBX1 ENBX2 ENBX3 ENBX4
DXO
MONITI
CLXO
ENBX1O
ENBX2O
ENBX3O
Figure 7. Typical Input Waveforms at the AD8389 and at the LCD. COMPEDGE = HIGH.
Rev. 0 | Page 8 of 12
04515-0-007
ENBX4O
AD8389 OUTLINE DIMENSIONS
7.00 BSC SQ 0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48
PIN 1 INDICATOR
1
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
BOTTOM VIEW
5.25 5.10 SQ 4.95
0.50 0.40 0.30
25 24
12 13
0.25 MIN 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 5.50 REF
1.00 0.85 0.80
12 MAX
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 8. 48-Lead Frame Chip Scale Package [LFCSP] (CP-48)
ORDERING GUIDE
Model AD8389ACPZ1 Temperature Range 0C to 85C Package Description 48-Lead Lead Frame Chip Scale Package Package Option CP-48
1
Z = lead-free.
Rev. 0 | Page 9 of 12
AD8389 NOTES
Rev. 0 | Page 10 of 12
AD8389 NOTES
Rev. 0 | Page 11 of 12
AD8389 NOTES
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04515-0-10/03(0)
Rev. 0 | Page 12 of 12

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