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FastEdgeTM Series CY2PP3210
Dual 1:5 Differential Clock/Data Fanout Buffer
Features
* Dual sets of five ECL/PECL differential outputs * Two ECL/PECL differential inputs * Hot-swappable/-insertable * 50 ps output-to-output skew * 150 ps device-to-device skew * 500 ps propagation delay (typical) * 0.8 ps RMS period jitter (max.) * 1.5 GHz Operation (2.2 GHz max. toggle frequency) * PECL mode supply range: VCC = 2.5V 5% to 3.3V5% with VEE = 0V * ECL mode supply range: VE E = -2.5V 5% to -3.3V5% with VCC = 0V * Industrial temperature range: -40C to 85C * 32-pin 1.4-mm TQFP package * Temperature compensation like 100K ECL * Pin compatible with MC100ES6210
Functional Description
The CY2PP3210 is a low-skew, low propagation delay dual 1-to-5 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz. The device features two differential input paths that are differential internally. The CY2PP3210 may function not only as a differential clock buffer but also as a signal-level translator and fanout distributing a single-ended signal. An external bias pin, VBB, is provided for this purpose. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypassed to ground via a 0.01-F capacitor. Traditionally, in ECL, it is used to provide the reference level to a receiving single-ended input that might have a differential bias point. Since the CY2PP3210 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2PP3210 delivers consistent performance over various platforms.
Block Diagram
QA0 QA0# QA1 QA1# QA2 QA2#
VEE
Pin Configuration
CLKA CLKA#
VCC
QA3 QA3# QA4 QA4# QB0 QB0# QB1 QB1# QB2 QB2#
VCC NC CLKA CLKA# VBB CLKB CLKB# VEE
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25
VCC QA0 QA0# QA1 QA1# QA2 QA2# VCC
CY2PP3210
24 23 22 21 20 19 18 17
QA3 QA3# QA4 QA4# QB0 QB0# QB1 QB1#
CLKB CLKB#
VEE
QB3 QB3# QB4 QB4# VBB
Cypress Semiconductor Corporation Document #: 38-07508 Rev.*C
*
3901 North First Street
*
San Jose, CA 95134
VCC QB4# QB4 QB3# QB3 QB2# QB2 VCC
9 10 11 12 13 14 15 16
VCC
* 408-943-2600 Revised July 28, 2004
FastEdgeTM Series CY2PP3210
Pin Definitions[1, 2, 3]
Pin 2 3 4 5 6 7 8 1,9,16,25,32 31,29,27,24,22 30,28,26,23,21 20,18,15,13,11 19,17,14,12,10 Name NC CLKA, CLKA# VBB[3] CLKB, CLKB# VEE[2] VCC QA(0:4) QA#(0:4) QB(0:4) QB#(0:4) I,PD O I,PD -PWR +PWR O O O O ECL/PECL Bias ECL/PECL Power Power I,PD/PU ECL/PECL I/O[1] Type No connect. ECL/PECL Differential Input Clocks. ECL/PECL Differential Input Clocks. Reference Voltage Output. ECL/PECL Differential Input Clocks. ECL/PECL Differential Input Clocks. Negative Supply. Positive Supply. Description
I,PD/PU ECL/PECL
ECL/PECL True output ECL/PECL Complement output ECL/PECL True output ECL/PECL Complement output
Governing Agencies
The following agencies provide specifications that apply to the CY2PP3210. The agency name and relevant specification is listed below in Table 2. Table 1. Agency Name JEDEC Specification JESD 020B (MSL) JESD 51 (Theta JA) JESD 8-2 (ECL) JESD 65-B (skew,jitter) 883E Method 1012.1 (Thermal Theta JC)
Mil-Spec
Notes: 1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power 2. In ECL mode (negative power supply mode), VEE is either -3.3V or -2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. 3. VBB is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|).
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FastEdgeTM Series CY2PP3210
Absolute Maximum Ratings
Parameter VCC VEE TS TJ ESDh MSL Description Positive Supply Voltage Negative Supply Voltage Temperature, Storage Temperature, Junction ESD Protection Moisture Sensitivity Level Assembled Die Condition Non-Functional Non-Functional Non-Functional Non-Functional Human Body Model 2000 3 50 Min. -0.3 -4.6 -65 Max. 4.6 0.3 +150 150 Unit V V C C V N.A. gates
Gate Count Total Number of Used Gates
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Operating Conditions
Parameter IBB LUI TA OJc OJa IEE CIN LIN VIN VTT VOUT IIN Description Output Reference Current Latch Up Immunity Temperature, Operating Ambient Dissipation, Junction to Case Dissipation, Junction to Ambient Maximum Quiescent Supply Current Input pin capacitance Pin Inductance Input Voltage Output Termination Voltage Output Voltage Input Current[7] Relative to VCC[6] Relative to VCC
[6]
Condition Relative to VBB Functional, typical Functional Functional Functional VEE pin[5]
Min. - 100 -40 29[4] 76[4] - - -0.3 -0.3
Max. |200| +85
Unit uA mA C C/W C/W
130 3 1 VCC + 0.3 VCC - 2 VCC + 0.3 l150l
mA pF nH V V V uA
Relative to VCC[6] VIN = VIL, or VIN = VIH
PECL DC Electrical Specifications
Parameter VCC VCMR VOH VOL VIH VIL VBB[3] Description Operating Voltage Differential Cross Point Voltage[8] Output High Voltage Output Low Voltage VCC = 3.3V 5% VCC = 2.5V 5% Input Voltage, High Input Voltage, Low Output Reference Voltage Condition 2.5V 5%, VEE = 0.0V 3.3V 5%, VEE = 0.0V Differential operation IOH = -30 mA[9] IOL = -5 mA[9] Single-ended operation Single-ended operation Relative to VCC[6] Min. 2.375 3.135 1.2 VCC - 1.25 VCC - 1.995 VCC -1.995 VCC - 1.165 VCC - 1.945
[10]
Max. 2.625 3.465 VCC VCC - 0.7 VCC - 1.5 VCC - 1.3 VCC - 0.880 [10] VCC - 1.625 VCC - 1.220
Unit V V V V V V V V V
VCC - 1.620
Notes: 4. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1 5. Power Calculation: VCC * IEE +0.5 (IOH + IOL) (VOH - VOL) (number of differential outputs used); IEE does not include current going off chip. 6. where VCC is 3.3V5% or 2.5V5% 7. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current. 8. Refer to Figure 1 9. Equivalent to a termination of 50 to VTT. IOHMIN=(VOHMIN-VTT)/50; IOHMAX=(VOHMAX-VTT)/50; IOLMIN=(VOLMIN-VTT)/50; IOLMAX=(VOLMAX-VTT)/50; 10. VIL will operate down to VEE; VIH will operate up to VCC
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FastEdgeTM Series CY2PP3210
ECL DC Electrical Specifications
Parameter VEE VCMR VOH VOL VIH VIL VBB[3] Description Negative Power Supply Differential cross point voltage[8] Output High Voltage Output Low Voltage VEE = -3.3V 5% VEE = -2.5V 5% Input Voltage, High Input Voltage, Low Output Reference Voltage Condition -2.5V 5%, VCC = 0.0V -3.3V 5%, VCC = 0.0V Differential operation IOH = -30 mA[9] IOL = -5 mA[9] Single-ended operation Single-ended operation Min. -2.625 -3.465 VEE + 1.2 -1.25 -1.995 -1.995 -1.165 -1.945
[10]
Max. -2.375 -3.135 0V -0.7 -1.5 -1.3 -0.880 [10] -1.625 - 1.220
Unit V V V V V V V
- 1.620
AC Electrical Specifications
Parameter VPP FCLK TPD Vo VCMRO tsk(0) tsk(PP) TPER tsk(P) TR,TF Description Differential Input Input Frequency Propagation Delay CLKA or CLKB to Output pair Output Voltage (peak-to-peak; see Figure 2) Output Common Voltage Range (typ.) Output-to-output Skew Part-to-Part Output Skew Output Period Jitter Output Pulse (rms)[12] Skew[13] 660 MHz [11], See Figure 3 660 MHz [11] 660 MHz [11] 660 MHz
[11],
Condition Differential operation 50% duty cycle Standard load 660 MHz [11]
Min. 0.1 280
Max. 1.3 1.5 750 -
Unit V GHz ps
Voltage[8]
< 1 GHz
0.375 VCC - 1.425 - - - See Figure 3 - 0.08
V V ps ps ps ps ns
50 150 0.8 50 0.3
Output Rise/Fall Time (see Figure 2)
660 MHz 50% duty cycle Differential 20% to 80%
Timing Definitions
VCC
VCM R Max = VCC
VIH
VPP
VPP range 0.1V - 1.3V
VCM R
VIL
VCMR M in = VEE + 1.2
VEE
Figure 1. PECL/ECL Input Waveform Definitions
Notes: 11. 50% duty cycle; standard load; differential operation 12. For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pulse Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000 data points 13. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.
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FastEdgeTM Series CY2PP3210
tr, tf, 20-80%
VO
Figure 2. ECL/LVPECL Output
In p u t C lo c k
VPP
TPLH, TPD O u tp u t C lo c k TPHL
VO
tS K (O )
A n o th e r O u tp u t C lo c k
Figure 3. Propagation Delay (TPD), output pulse skew (|tPLH-tPHL|), and output-to-output skew (tSK(O)) for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL
Test Configuration
Standard test load using a differential pulse generator and differential measurement instrument.
VTT RT = 50 ohm P u ls e G e n e ra to r Z = 50 ohm
5" VTT
RT = 50 ohm
Zo = 50 ohm RT = 50 ohm VTT DUT CY2PP3210
Zo = 50 ohm
5"
RT = 50 ohm
VTT
Figure 4. CY2PP318 AC Test Reference
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FastEdgeTM Series CY2PP3210
Applications Information
Termination Examples
CY2PP3210
VCC
5"
VTT RT = 50 ohm
Zo = 50 ohm
5"
RT = 50 ohm VTT
VEE
Figure 5. Standard LVPECL - PECL Output Termination
CY2PP3210
VCC
5"
VTT RT = 50 ohm
Zo = 50 ohm
5"
VTT R T = 50 ohm
V B B (3 .3 V ) VEE
Figure 6. Driving a PECL/ECL Single-ended Input
CY2PP3210
V C C = 3 .3 V
5"
3 .3 V 120 ohm
LVDS
Zo = 50 ohm
5"
33 ohm ( 2 p la c e s )
120 ohm 3 .3 V
51 ohm ( 2 p la c e s )
VEE = 0V
L V P E C L to LVDS
Figure 7. Low-voltage Positive Emitter-coupled Logic (LVPECL) to a Low-voltage Differential Signaling (LVDS) Interface
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FastEdgeTM Series CY2PP3210
VDD-2 X
VCC Y
Z
One output is shown for clarity
Figure 8. Termination for LVPECL to HTSL interface for VCC=2.5V would use X=50 Ohms, Y=2300 Ohms, and Z=1000 Ohms. See application note titled, "PECL Translation, SAW Oscillators, and Specs" for other signalling standards and supplies.
Ordering Information
Part Number CY2PP3210AI CY2PP3210AIT 32-pin TQFP 32-pin TQFP - Tape and Reel Package Type Product Flow Industrial, -40 to 85C Industrial, -40 to 85C
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FastEdgeTM Series CY2PP3210
Package Drawing and Dimension
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14
Dimensions are in mm
51-85088-*B
FastEdge is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
FastEdgeTM Series CY2PP3210
Document History Page
Document Title: CY2PP3210 FastEdgeTM Series Dual 1:5 Differential Clock/Data Fanout Buffer Document Number: 38-07508 REV. ** *A ECN NO. 122396 125458 Issue Date 02/12/03 04/17/03 Orig. of Change RGL RGL New Data Sheet Corrected pins 26 to 31 from Q2#, Q2, Q1#, Q1, Q0#, Q0 to QA2#, QA2, QA1#, QA1,QA0#, QA0 in the Pin Configuration diagram Changed pins 9, 16, 25, 32 from VCC to VCCO Changed the title to FastEdgeTM Series Dual 1:5 Differential Clock/Data Fanout Buffer Supplied data to all the TBD's to match the device Description of Change
*B *C
229370 247616
See ECN See ECN
RGL
RGL/GGK Changed VOH and VOL to match the Char Data
Document #: 38-07508 Rev.*C
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