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PRELIMINARY PRODUCT SPECIFICATION
1
Z80382, Z8L382
HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS
FEATURES
s
1
Embedded Z380 Microprocessor Maintains Object Code Compatibility with Z80 and Z180 Microprocessors Enhanced Instruction Set for 16-Bit Operation 16 MB Linear Addressing Two Clock Cycle Instruction Execution Minimum Four On-Chip Register Banks BC/DE/HL/IX/IY Augmented to 32 Bits Clock Divide-by-Two and Multiply-by-Two Options Fully Static CMOS Design with Low-Power Standby Mode 16-Bit Internal Bus Dynamic Bus Sizing (8/16-Bit Inter-Operability) 16550 Mimic with I/O Mailbox, DMA Mailbox, and 16 mA Bus Drive Three HDLC Synchronous Serial Channels Serial Data Rate of up to 10 Mbps GCI/SCIT Bus Interface
s s s s
Eight Advanced DMA Channels with 24-Bit Addressing Plug-and-Play ISA Interface PCMCIA Interface Two Enhanced ASCIs (UARTs) with 16-Bit Baud Rate Generators (BRG) Clocked Serial I/O Channel (CSIO) for Use with Serial Memory Two 16-Bit Timers with Flexible Prescalers Three Memory Chip Selects with Wait-State Generators Watch-Dog Timer (WDT) Up to 32 General-Purpose I/O Pins DC to 20 MHz Operating Frequency @ 5.0V DC to 10 MHz Operating Frequency @ 3.3V 144-Pin QFP and VQFP Style Packages
s
s s s s s s s
s
s
s
GENERAL DESCRIPTION
The Z80382 (Z382) is designed to address high-end data communication applications such as digital modems (ISDN, GSM, Mobitex & Modacom), xDSL and analog modems (V.34 and beyond). The Z382 provides a performance upgrade to existing Z80- and Z18x-based designs by utilizing the increased bandwidth of the 380C processor. The Z8L382 is a low voltage version of the device. Note: In this document the notation O380CO denotes the Z380-compatible CPU core which is embedded in the Z382. The 380C microprocessor is a high-performance processor with fast and efficient throughput and increased memory addressing capabilities. The 380C offers a continuing growth path for present Z80- or Z18x-based designs, while maintaining Z80 and Z180 object code compatibility. Its enhancements include added instructions, expanded16 MB address space and flexible bus interface timing. In the 380C, the basic addressing modes of the Z80 microprocessor have been augmented to include Stack Pointer Relative loads and stores, 16-bit and 24-bit indexed offsets, and more flexible Indirect Register addressing. Internally, all of the addressing modes allow up to 32-bit linear addressing; however, because the Z382 has only 24 address pins, it can only address 16 MB of memory.
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GENERAL DESCRIPTION (Continued)
Other additions to the instruction set include a full complement of 16-bit arithmetic and logical operations, 16-bit I/O operations, multiply and divide, and a complete set of register-to-register loads and exchanges. The 380C register file includes alternate versions of the IX and IY registers. There are four banks of registers in the 380C, along with instructions for switching among them. All of the 16-bit register pairs and index registers in the basic Z80 microprocessor register file are expanded to 32 bits. The Z382 includes dynamic bus sizing to allow any mix of 16- and 8-bit memory, and I/O devices in a system. One application for this capability would be to copy code from a low-cost, slow 8-bit ROM to 16-bit RAM, from which it can be executed at much higher speeds. Memory bus sizes can be configured internally by software to eliminate the need for external logic to drive MSIZE. Some features that have traditionally been handled by external peripherals have been incorporated in the Z382. These on-chip peripherals reduce system chip count and interconnections on the external bus. These peripherals, illustrated in the Z382 Block Diagram in Figure 1, are summarized below. HDLC Synchronous Channels. Three HDLC channels operate at serial data rates of up to 10 Mbps and feature 8-byte receive and transmit FIFOs. These can be used for modems, general data communications, and ISDN. The ISDN can be handled separately or through the GCI/SCIT bus interface. HDLC Channels always transfer data through the DMA channels. A transparent mode is selectable. Two of the HDLC cells can be pin multiplexed with the ASCIs (UARTs) to provide dynamically switchable (async-sync) DTE interfaces. DMA Channels. The eight DMA channels provide 24-bit memory addressing and can transfer memory block sizes of up to 64 KB (16-bits). These DMA channels can be dynamically assigned to serve the HDLC ports, Mimic COM port, Host DMA Mailbox, or ASCIs in any mixture. Linked list operation allows all HDLC transmitters and receivers to operate at or above E1 rates simultaneously without loading the bus bandwidth. 16550 Mimic. Provides connection to a PC ISA bus and emulation of the 16550 UART register set. Improvements include 16 mA output drivers and internal COM port address decoding to reduce external PC interface components. ASCI. Two flexible asynchronous serial channels with baud rate generators, modem control and status. CSIO. A clocked serial I/O channel which can be used for serial memory interface. Timers. Two 16-bit counter/timers with flexible prescalers for wide-range timing applications. GCI/SCIT Bus Interface. A common interface to ISDN interface devices. Internal signals from this module can be connected to the HDLC channels to provide B-channels and D-channel for ISDN. Plug-and-Play ISA Interface. Provides auto-configuration in ISA (AT bus) applications. PCMCIA Interface. Provides connectivity to a PCMCIA bus. 32-Bit General-Purpose I/O. For non-PC add-in applications, four 8-bit ports are provided for general- purpose I/O. In ISA or PCMCIA applications, the pins from two of the ports are reallocated to host bus signals and are not available. Pins from the other two ports are selectively multiplexed with on-chip peripheral functions (ASCIs, CSI/O, PRT). These pins are individually programmable for input/output mode. I/O Chip Selects. Two I/O chip selects are provided to support I/O access of external peripherals. Each has a programmable base address and provides I/O decode sizes ranging from 8 to 512 bytes. ROM/RAM Chip Selects with Wait-State Generators. Chip select outputs are provided to decode memory addresses and provide memory chip enables. Each chip select has its own Wait State Generator to allow use of memories with different speeds. Watch-Dog Timer. A Watch-Dog Timer (WDT) with a wide range of time-constants prevents code runaway and possible resulting system damage. The /RESET input can be forced as an output upon the terminal count of the WDT. This allows external peripherals to be reset along with the Z382.
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P C M C I A
PCMCIA Interface and Attribute RAM
32-Bit GP I/O
8
1
16550 Mimic Interface I S A B U S PC DMA and I/O Interface
380C
Z380-Compatible High Performance Processor Core
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Dual ASCI and CSIO
Dual Timer and WDT
8
Plug and Play ISA Interface and Configuration Registers
Chip Select and WSG Logic
16 8
External Memory (ROM/RAM)
8
DMA 0
DMA 1
DMA 2
DMA 3
DMA 4
DMA 5
DMA 6
DMA 7
Channel 0 HDLC Channel
Channel 1 HDLC Channel GCI/SCIT Serial Bus
Channel 2 HDLC Channel
Figure 1. Z80382 Block Diagram
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Z80382 PIN DESCRIPTION
FSC/RXD2 DD/TXD2 DCL/RXC2/BCL2 DU/TXC2/FSC2 Vss RXD1/RXA1 TXD1/TXA1 RXC1/BCL1/PC1 TXC1/FSC1/CKA1 RXD0/RXA0 TXD0/TXA0 RXC0/BCL0/PC0 TXC0/FSC0/CKA0 Vdd /TXEN1//RTS1 /TXEN0//RTS0 CKA0/HDRQ1/PCRESET TXA0/HDRQ0//PCCE1 RXA0//HDAK1//PCOE /DCD0//HDAK0//PCWE /RTS0/HINT2/STSCHG TXA1/HINT1//PCIRQ Vss PA0/HD0 PA1/HD1 PA2/HD2 PA3/HD3 PA4/HD4 PA5/HD5 PA6/HD6 PA7/HD7 Vdd PD0/HA0 PD1/HA1 PD2/HA2 PD3/HA3 105 PC2//TXEN2/TOUT /CTS1//TREFC /CTS0//TREFA /DCD0//TREFR Vdd IOCLK /IORQ /M1 /MSIZE /BHEN /BLEN /STNBY /HALT Vss /IOWR /MWR /IORD /MRD BUSCLK CLKI CLKO /WAIT Vdd /BUSACK /BUSREQ /RESET /NMI /INT0 /INT1 /INT2 /INT3 Vss A23 A22 A21 A20 110 70 100 95 90 85 80 75 PD4/HA4 PD5/HA5 PD6/HA6 PD7/HA7 Vss RXA1/HA8 DCD1/HA9 CKA1/HA10 CKS/HA11 RXS/HAEN//PCREG TXS//HDOEN//INPACK /CTS0//HRD//PCIORD /CTS1//HWR//PCIOWR Vdd PB0/CKS PB1/RXS PB2/TXS PB3/RXA1 PB4/TXA1 PB5/CKA0 PB6/RXA0 PB7/TXA0 Vss PC3/CKA1 PC4/IEO PC5/IEI TOUT//IOCS2 PC6//IOCS1 PC7//RAMCSH /RAMCSL /ROMCS Vdd D0 D1 D2 D3 115 65 120 60 125
Z80382 144-Pin QFP and VQFP
55
130 50
135 45
140 40
144 1 5 10 15 20 25 30 35
Figure 2. Z80382 144-Pin QFP and VQFP Pin Description
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A19 A18 A17 A16 Vdd A15 A14 A13 A12 A11 A10 A9 A8 Vss A7 A6 A5 A4 A3 A2 A1 A0 Vdd D15 D14 D13 D12 D11 D10 D9 D8 Vss D7 D6 D5 D4
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ABSOLUTE MAXIMUM RATINGS
Symbol VDD VIN TOPR TSTG Description Supply Voltage Input Voltage Operating Temp Storage Temp Value -0.3 to +7.0 -0.3 to VDD+0.3 0 to +70 -55 to +150 Unit V V C C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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STANDARD TEST CONDITIONS
The DC Characteristics which follow apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND (0V). Positive current flows into the referenced pin (Figure 3, Test Load Diagram).
s IOL = 2 mA
Operating temperature range: Standard: 0C to 70C
1.4V
Voltage Supply Range: +4.5V VDD +5.5V (Z80382 versions) +3.0V VDD +3.6V (Z8L382 versions) All AC parameters assume a load capacitance of 50 pF. Add 10 ns delay for each 50 pF increase in load up to a maximum of 150 pF for the data bus and 100 pF for address and control lines. AC timing measurements are referenced to 1.5 volts (except for clock, which is referenced to the 10% and 90% points). Maximum capacitive load for PHI is 125 pF.
s
100 pF
IOH = 250 mA
Figure 3. Test Load Diagram
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DC CHARACTERISTICS
Pin Numbers and Input/Output Classifications Pin /BHEN /BLEN /BUSACK /BUSREQ /CTS0//HRD//PCIORD /CTS0//TREFA /CTS1//HWR//PCIOWR /CTS1//TREFC /DCD0//HDAK0//PCWE /DCD0//TREFR /DCD1/HA9 /HALT /INT0-3 /IORD /IORQ /IOWR /M1 /MRD /MSIZE /MWR /NMI /RAMCSL /RESET /ROMCS /RTS0/HINT2/STSCHG /STNBY /TXEN1-0//RTS1-0 /WAIT A23-0 BUSCLK CKA0/HDRQ1/PCRESET CKA1/HA10 CKS/HA11 CLKI CLKO D15-0 DCL/RXC2/BCL2 DD/TXD2 DU/TXC2/FSC2 FSC/RXD2 IOCLK PA7-0/HD7-0 PB0/CKS Input Class1 Output Class1 O O O I I I I I I I I R I I I I I I I R R O Pin Number(s) 118 119 132 133 61 111 60 110 89 112 66 121 136 - 139 125 115 123 116 126 117 124 135 43 134 42 88 120 94 -93 130 141 - 144, 1 - 4, 6 - 13, 15 - 22 127 92 65 64 128 129 24 - 31, 33 - 40 106 107 105 108 114 78 -85 58
O O O O 3 3 3 3 3 D 3 O D H O O D 3 H H 3 3 O 3 D (DD) O (TXD2) D (DU) O (TXC2, FSC2) O H 3
I I I I I R I I I I I I I I
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Zilog Pin PB1/RXS PB2/TXS PB3/RXA1 PB4/TXA1 PB5/CKA0 PB6/RXA0 PB7/TXA0 PC2//TXEN2/TOUT PC3/CKA1 PC4/IEO PC5/IEI PC6//IOCS1 PC7//RAMCSH PD7-0/HA7-0 RXA0//HDAK1//PCOE RXA1/HA8 RXC1-0/BCL1-0/PC1-0 RXD1-0/RXA1-0 RXS/HAEN//PCREG TOUT//IOCS2 TXA0/HDRQ0//PCCE1 TXA1/HINT1//PCIRQ TXC1-0/FSC1-0/CKA1-0 TXD1-0/TXA1-0 TXS//HDOEN//INPACK VDD VSS Input Class1 i I I I I I I I I I I I I I I I I I I I I
Z80382/Z8L382 High-Performance Data Communications Processors Output Class1 3 3 3 3 3 3 3 3 3 3 3 3 3 3 D 3 3 O D 3 H H 3 O O Pin Number(s) 57 56 55 54 53 52 51 109 49 48 47 45 44 69 - 76 90 67 101, 97 103, 99 63 46 91 87 100, 96 102, 98 62 5, 23, 41, 59, 77, 95, 113, 131 14, 32, 50, 68, 86, 104, 122, 140
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Note: 1. Characteristics of each pin are listed in terms of the classifications in the DC Characteristics Tables 1 and 2 which follow.
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DC CHARACTERISTICS (Continued)
Specifications apply over Standard Operating Conditions unless otherwise noted. Table 1. Output Class Characteristics Output Class(1) O 3 H Type Totem Pole Tri-State High Drive Tri-State Open-Drain VOL Max. VOH Min. COUT Max.(2) 15 pF
D
0.4V @ IOL = 2.0 ma VDD - 1.2V @ IOH = 200 mA Slew Rate = 0.33 V/ns min @ CLOAD = 50 pF 0.4V @ IOL = 2.0 ma VDD - 1.2V @ IOH = 200 mA Slew Rate = 0.33 V/ns min @ CLOAD = 50 pF 0.4V max @ IOL = 16 mA, 2.4V min @ IOH = 5mA, VDD = 5V VDD = 5V Slew Rate = 0.33 V/ns min @ CLOAD = 50 pF 0.4V max @ IOL = 16 mA --
15 pF
15 pF
Notes: 1. The Pin Numbers and Input/Output Classifications table in the previous section identifies the specific output pins in each class. 2. Applies to Output only or I/O.
Table 2. Input Class Characteristics Input Class I
(1)
VIL Max. (Z80382) 0.8V
VIL Max. (Z8L382)
VIH Min. (Z80382)
VIH Min. (Z8L382)
Minimum Hysteresis 0.4V
0.6V 2.0V 2.0V II = 10 mA max, VI = 0 to 5V (includes leakage if I/O) CIN = 5 pF max (if input only, see output type if I/O)
Note: Inputs of this type include a weak-latch circuit, except that a register bit can disable those for pins PB7-0.
R
0.4V
0.4V
VDD - 0.6V VDD - 0.3V II = 10 mA max, VI = 0 to 5V CIN = 5 pF max
0.4V
Note: Inputs of this type except CLKI include a weak-latch circuit. Notes: 1. The Pin Numbers and Input/Output Classifications table in the previous section identifies the specific input pins in each class.
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Z80382/Z8L382 High-Performance Data Communications Processors Table 3. DC Electrical Characteristics
Symbol VIH VIL VOH VOL IIL
Item Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current, All Inputs Except CLKI, CLKO Tri-State Leakage Current VDD Supply Current (1, 3) Normal Operation
Condition
Min. See Table 2 See Table 2 See Table 1 See Table 1
Typ.
Max.
Unit V V V V mA mA mA mA mA mA mA mA
1
VIN = 0.5V to VDD - 0.5V VIN = 0.5 to VDD - 0.5 BUSCLK = 10 MHz VDD = 3.3V BUSCLK = 10 MHz VDD = 5V BUSCLK = 20 MHz VDD = 5V BUSCLK = 10 MHz VDD = 3.3V BUSCLK = 10 MHz VDD = 5V BUSCLK = 20 MHz VDD = 5V
1.0
ITL IDD
1.0 75 90 150 50 50 50
IDDS
VDD Supply Current Standby Mode (1, 2, 3)
Notes: 1. VIH min = VDD-1.0V, VIL max = 0.8V. All output terminals are at no load. 2. On-chip peripherals with independent clocks are inactive (not being clocked). 3. BUSCLK is the internal processor clock frequency.
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AC CHARACTERISTICS
380C Processor Timing (See Figure 4) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Z80382 Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 Parameter Clock Cycle Time Clock High Time Clock Low Time Clock Rise Time Clock Fall Time CLKI Low to BUSCLK High Delay CLKI High to BUSCLK Low Delay BUSCLK High to Output Valid BUSCLK Low to Output Valid Input Setup to BUSCLK Rise Input Hold from BUSCLK High /BUSREQ Setup to BUSCLK Fall /BUSREQ Hold from BUSCLK Low /WAIT Setup to BUSCLK Rise /WAIT Hold from BUSCLK High /WAIT Setup to BUSCLK Fall /WAIT Hold from BUSCLK Low /NMI Width Low /RESET Width Low /INT1, /INT2, /INT3 Low Width /INT1, /INT2, /INT3 High Width Min. 25 10 10 Max. DC 50 20 20 Z8L382 Min. Max. DC Notes 1 1 1 1 1 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t1 ns ns
3 3 25 25 10 10 10 0 10 0 10 0 15 0 15 10 15 15 15 0 15 0 15 0 15 0 15 10 15 15
5 5 35 35 10 10
2 3 4 4 5 5 6 6 6 6
7 7
Notes: 1. Applies to the oscillator or external clock input. The maximum internal clock frequency (BUSCLK) is limited to 20 MHz for the Z80382 and 10 MHz for the Z8L382. Input clock frequencies greater than these values must use the CLKI/2 mode for creating BUSCLK. This is the default state after Reset. 2. Applies to A23-0, /BHEN, /BLEN, IOCLK, /IOCS1, /IOCS2, /ROMCS, /RAMCSL, /RAMCSH, /M1, /BUSACK, /MRD, /MWR, /TREFA, /TREFC, /TREFR 3. Applies to D15-0, /HALT, /STNBY, /IORQ, /IORD, /IOWR, /MSIZE, /BUSACK, /MRD, /MWR, /TREFC, /TREFR 4. Applicable for Data Bus and /MSIZE inputs. 5. /BUSREQ can also be asserted/deasserted asynchronously. 6. External waits asserted at /WAIT input. 7. In edge-triggered mode.
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t3 CLK t5 t6 BUSCLK t4 t7
t2
1
OUTPUT t8 OUTPUT t9 INPUT t10, t14 t11, t15
INPUT t12, t16 t13, t17 INPUT t18, t19 INPUT t20 t21
Figure 4. 380C Processor Timing
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AC CHARACTERISTICS (Continued)
Host - PCMCIA Attribute Memory Read Timing (See Figure 5) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Z80382 Symbol t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 Parameter Address Setup to /PCCE1 Fall Address Setup to /PCOE Fall Address Hold from /PCCE1 High Address Hold from /PCOE High /PCCE1 Low to Data Active /PCOE Low to Data Active /PCCE1 Low to Data Valid /PCOE Low to Data Valid Data Invalid from /PCCE1 High Data Invalid from /PCOE High Data Tri-state from /PCCE1 High Data Tri-state from /PCOE High Min. 15 15 5 5 0 0 60 60 5 5 20 20 20 20 Max. Min. 20 20 5 5 0 0 5 5 Z8L382 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns
60 60
Note: Timings also apply for reads from registers located in the attribute memory space.
HA9-0
t25 PCREG t24 t28 t32 t26 /PCOE t29 t33 t23 HD7-0 t31 t27 t30
t22 /PCCE1
Figure 5. Host - PCMCIA Attribute Memory Read Timing
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Host - PCMCIA Attribute Memory Write Timing (See Figure 6) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Z80382 Symbol t34 t35 t36 t37 t38 t39 t40 t41 Parameter Address Setup to /PCCE1 Fall Address Setup to /PCWE Fall Address Hold from /PCCE1 High Address Hold from /PCWE High Data Setup to /PCCE1 Rise Data Setup to /PCWE Rise Data Hold from /PCCE1 High Data Hold from /PCWE High Min. 30 30 10 10 20 20 10 10 Max. Min. 35 35 10 10 20 20 10 10 Z8L382 Max. Unit ns ns ns ns ns ns ns ns
1
Note: Timings also apply for writes to registers located in the attribute memory space.
HA9-0
t37 PCREG t36
t34 /PCCE1
t40 t38 /PCWE
t35 HD7-0 t39
t41
Figure 6. Host - PCMCIA Attribute Memory Write Timing
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AC CHARACTERISTICS (Continued)
Host - PCMCIA I/O Read Timing (See Figure 7) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Z80382 Symbol t42 t43 t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 Parameter Address Setup to /PCIORD Fall /PCREG Setup to /PCIORD Fall /PCCE1 Setup to /PCIORD Fall /PCIORD Low Width /INPACK Low from /PCIORD Low Data Valid from /PCIORD Low Data Invalid from /PCIORD High /INPACK High from /PCIORD High /PCCE1 Hold from /PCIORD High /PCREG Hold from /PCIORD High Address Hold from /PCIORD High /PCIORD Low to Data Active Data Tri-state from /PCIORD High Min. 50 5 5 125 10 50 5 10 10 10 10 0 20 10 10 10 0 20 5 10 Max. Min. 50 5 5 125 10 50 Z8L382 Max.
Units ns ns ns ns ns ns ns ns ns ns ns ns ns
HA[9:0] t42 /PCREG t51 t43 /PCCE1 t44 t45 /PCIORD t46 /INPACK t48 t49 t50 t52
t47 HD[7:0] t53
t54
Figure 7. Host - PCMCIA I/O Read Timing
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Host - PCMCIA I/O Write Timing (See Figure 8) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Z80382 Symbol t55 t56 t57 t58 t59 t60 t61 t62 t63 Parameter Address Setup to /PCIOWR Fall /PCREG Setup to /PCIOWR Fall /PCCE1 Setup to /PCIOWR Fall /PCIOWR Low Width Data Setup to /PCIOWR Rise Data Hold from /PCIOWR High /PCCE1 Hold from /PCIOWR High /PCREG Hold from /PCIOWR High Address Hold from /PCIOWR High Min. 50 5 5 125 35 20 10 10 10 Max. Z8L382 Min. Max. 50 5 5 125 35 20 10 10 10
1
Units ns ns ns ns ns ns ns ns ns
HA[9:0] t63
t55 /PCREG t56 t62
/PCCE1 t57 t58 /PCIOWR t61
t59
t60
HD[7:0]
Figure 8. Host PCMCIA I/O Write Timing
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AC CHARACTERISTICS (Continued)
Timer Output Timing (See Figure 9) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Z80382 Symbol t64 Parameter BUSCLK Low to TOUT Valid Min. Max. 20 Min. Z8L382 Max. 20 Units ns
BUSCLK TIMER CLOCK (Internal)
t64
TOUT
Figure 9. Timer Output Timing
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CSI/O Receive/Transmit Timing (See Figure 10) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Z80382 Symbol t66 t67 t68 t71 Parameter CKS Low to TXS Valid RXS Setup to CKS Rise RXS Hold from CKS High CKS External Clock Period Min. 20 5 50 Max. 40 20 5 50 Min. Z8L382 Max. 40 Units ns ns ns ns
1
t71 CKS t66 TXS t67 RXS t68
Figure 10. CSI/O Receive and Transmit Timing
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AC CHARACTERISTICS (Continued)
ASCI Transmitter Timing (See Figure 11) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Z80382 Symbol t72 t73 t74 t75 t76 t77 Parameter External Transmit Clock Period External Transmit Clock Low Width External Transmit Clock High Width External Transmit Clock Fall Time External Transmit Clock Rise Time CKA Low to TXA Data Valid Min. 50 30 30 5 5 20 Max. Min. 50 30 30 10 10 30 Z8L382 Max. Units ns ns ns ns ns ns
t72 t73 CKA (input) t75 t76 t74
TXA t77
Figure 11. ASCI Transmitter Timing
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ASCI Receiver Timing (See Figure 12) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Z80382 Min. Max. 50 30 30 5 5 20 5 25 5 Z8L382 Min. Max. 50 30 30 10 10
1
Units ns ns ns ns ns ns ns
Symbol t79 t80 t81 t82 t83 t84 t85
Parameter External Receive Clock Period External Receive Clock Low Time External Receive Clock High Time External Receive Clock Fall Time External Receive Clock Rise Time RXA Setup to CKA Rise RXA Hold from CKA High
t79 t80 CKA (input) t82 t84 t83 t85 t81
RXA
Figure 12. ASCI Receiver Timing
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AC CHARACTERISTICS (Continued)
ASCI/CSIO Timing - Baud Rate Generator, /CTSA, /DCDA, and /RTSA Timing (See Figures 13, 14 and 15) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Z80382 Symbol t88 t89 t90 t91 t92 t93 t94 t95 Parameter BUSCLK High to BRG Output Delay BRG Output Fall Time BRG Output Rise Time /CTS Low Time /CTS High Time /DCD Low Time /DCD High Time BUSCLK Low to /RTS Valid Min. Max. 30 10 10 100 100 100 100 20 100 100 100 100 20 Min. Z8L382 Max. 40 15 15 Units ns ns ns ns ns ns ns ns
BUSCLK t88 t88
CKA or CKS (output) t89 t90
Figure 13. Baud Rate Generator Timing
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t91
1
t92
/CTS
t93 /DCD t94
Figure 14. /CTSA and /DCDA Timing
BUSCLK t95
/RTS
Figure 15. /RTSA Timing
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AC CHARACTERISTICS (Continued)
General-Purpose I/O Port Timing. (See Figure 16) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Z80382 Symbol t100 t101 t102 Parameter I/O Port Data Setup to /IORD Fall I/O Port Data Hold from /IORD High I/O Port Data Valid from /IOWR High Min. 10 5 20 Max. Min. 10 5 20 Z8L382 Max. Units ns ns ns
/IORD t100 t101 Port Input
/IOWR t102 Port Output
Figure 16. General-Purpose I/O Port Timing
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Z80382/Z8L382 High-Performance Data Communications Processors
HDLC Receive Timing- Full Time HDLC Mode (See Figures 17 and 18) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Z80382 Min. Max. 50 15 15 5 5 20 5 5 20 5 25 10 20 5 10 Z8L382 Min. Max. 50 15 15 10 10
1
Units ns ns ns ns ns ns ns ns ns ns Notes 1
No t103 t104 t105 t106 t107 t108 t109 t110 t111 t112
Parameter External Receive Clock Period External Receive Clock Low Time External Receive Clock High Time External Receive Clock Rise Time External Receive Clock Fall Time RxD Setup to RxC Edge (External RxC) RxD Hold from RxC Low/High (External RxC) RxC rise/fall time (Internal RxC) RxD Setup to RxC Edge (Internal RxC) RxD Hold from RxC Low/High (Internal RxC)
1 1 1 1 1
Note: 1. Receive clock sampling edge is configurable by means of RIRn[6]. See Z80382 User Manual.
t103 t104 t105
RxC(1) (input) t106 t107 t108 t109
RxD
Note 1. HDLC clock triggering polarity is configurable by means of RIRn[6]. See Z80382 User Manual.
Figure 17. HDLC Receive Timing (Full Time HDLC, RxC Input)
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AC CHARACTERISTICS (Continued)
RxC(1) (output) t110 t111 t112
RXD
Note 1. Receive clock sampling edge is configurable by means of RIRn[6]. See Z80382 User Manual.
Figure 18. HDLC Receive Timing (Full Time HDLC, RxC Output)
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Z80382/Z8L382 High-Performance Data Communications Processors
HDLC Transmit Timing- Full Time HDLC Mode (See Figure 19) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Z80382 Min. Max. 50 15 15 5 5 20 Z8L382 Min. Max. 50 15 15 10 10 25
1
Units ns ns ns ns ns ns Notes 1
Symbol t113 t114 t115 t116 t117 t118
Parameter External Transmit Clock Period External Transmit Clock High Time External Transmit Clock Low Time External Transmit Clock Fall Time External Transmit Clock Rise Time TxC Low to TxD Data Valid
t113 t114 TxC (input) t116 t117 t115
TxD t118
Figure 19. HDLC Transmit Timing (Full Time HDLC)
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AC CHARACTERISTICS (Continued)
HDLC Timing - Non-GCI TDM mode (See Figure 20) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Z80382 Min. Max. 30 20 50 15 15 15 15 15 15 15 5 20 20 5 Z8L382 Min. Max. 50 30 50 15 15 20 20 20
Symbol t120 t121 t122 t123 t124 t125 t126 t127 t128 t129 t130
Parameter FSC Setup to BCL Fall FSC Hold from BCL Low BCL Period BCL High Time BCL Low Time BCL High to TxEN Low BCL High to TxEN High BCL High to TxD Valid BCL High to TxD Invalid RxD Setup to BCL Fall (Rise) RxD Hold from BCL Low (High)
Units ns ns ns ns ns ns ns ns ns ns ns
Notes
1 1
Note: 1. Receive clock sampling edge is configurable by means of RIRn[6]. See Z80382 User Manual.
t120 BCL (input) 0 FSC (input) t121 TxEN 1 2 Number of clocks start 3
t122
t123
t124 t130
t125
t126
t127 TxD t129
t128
RxD
Figure 20. HDLC Timing - Non-GCI TDM Mode (Shown for Start = 3, Length = 2, Negative Edge RxD Sampling)
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Z80382/Z8L382 High-Performance Data Communications Processors
GCI/SCIT Timing - Slave Characteristics (See Figure 21) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Z80382 Symbol t131 t132 t133 t134 t135 t136 t137 t138 t139 Parameter DCL Data Clock Rise/Fall Time DCL Clock Period DCL Pulse Width High FSC Setup to DCL Fall FSC Hold from DCL Low DCL High to DU/DD Transmit Data Valid FSC High to DU/DD Transmit Data Valid DU/DD Receive Data Setup to DCL Fall DU/DD Receive Data Hold from DCL Low Min. 50 15 30 5 15 15 15 0 20 0 Max. 5 50 15 30 10 20 20 Min. Z8L382 Max. 10 Units ns ns ns ns ns ns ns ns ns
1
GCI/SCIT Timing - Master Characteristics (See Figure 21) Specifications apply over Standard Operating Conditions unless otherwise noted. CL = 50 pF for outputs. Z80382 Symbol t131 t132 t133 t134 t135 t136 t137 t138 t139 t140 Parameter DCL Data Clock Rise/Fall Time DCL Clock Period DCL Pulse Width High FSC Setup to DCL Fall FSC Hold from DCL Low DCL High to DU/DD Transmit Data Valid FSC High to DU/DD Transmit Data Valid DU/DD Receive Data Setup to DCL Fall DU/DD Receive Data Hold from DCL Low FSC High from DCL High Min. 50 15 30 5 15 15 15 0 0 20 0 0 Max. 5 50 15 30 10 20 20 Min. Z8L382 Max. 10 Units ns ns ns ns ns ns ns ns ns ns
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AC CHARACTERISTICS (Continued)
t131 DCL
t133
t131
t132 t140 FSC t137 t136 DU/DD transmit t134 t135
3
t139 t138 DU/DD receive
Figure 21. GCI/SCIT Slave and Master Timing
PIN FUNCTIONS
The tables which follow describe the input and output signals of the Z382. Signals are normally asserted in the High state and negated in the Low state. A hyphen (/) preceding the signal name indicates that the signal is asserted in the Low state and negated in the High state. Many pins have multiple functions, and thus may appear more than once in the pin description tables. In each table, such pins are described using their function in that mode. Likewise, some signals may be output on alternate pins depending on the mode under which the Z382 is operating. The notation Oxx/yyO in the Pin Number column indicates that the signal may be assigned to pin OxxO or pin OyyO.
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Z80382/Z8L382 High-Performance Data Communications Processors Table 4. MPU Signals
Pin Name A23 - 0
Pin Number(s) 141 - 144, 1 - 4, 6 - 13, 15 - 22 132
Description Address Bus (outputs, active High, tri-state): These non-multiplexed address signals provide a linear memory address space of 16 MB. The address signals are also used to access I/O devices. Bus Acknowledge (output, active Low, tri-state): This signal, when asserted, indicates that the 380C has accepted an external bus request and has tri-stated its output drivers for the address bus, databus and the bus control signals /TREFR, /TREFA, /TREFC, /BHEN, /BLEN, /MRD, /MWR, /IORQ, /IORD, and /IOWR. The 380C cannot provide any DRAM refresh transactions while it is in the bus acknowledge state. Byte High Enable (output, active Low, tri-state): This signal is asserted at the beginning of a memory or refresh transaction, to request an operation on D15-8. If software initiates a 16-bit memory operation, but /MSIZE is asserted indicating a byte-wide memory, only the data on D7-0 is transferred in the current transaction, and another transaction is performed to transfer the other data byte, also on D7-0. Byte Low Enable (output, active Low, tri-state): This signal is asserted at the beginning of a memory or refresh transaction, to request an operation on D7-0. If software initiates a 16-bit memory transaction, but /MSIZE is asserted indicating a byte-wide memory, only the data on D7-0 is transferred in the current transaction, and another transaction is performed to transfer the other data byte, also on D7-0. To align Z382 documentation and terminology with historical Z80 and industry (e.g., Intel) practice, the names of the /BHEN and /BLEN pins, as well as the D15-8 and D7-0 pins, have been swapped on the Z382 compared to the Z380. This fact should be significant only for those using a Z380 Emulator in a Z382-based project. Bus Request (input, active Low): When this signal is asserted, an external bus master is requesting control of the bus. /BREQ has higher priority than all nonmaskable and maskable interrupt requests. Bus Clock (output, active High, tri-state): This signal is the reference edge for the majority of other signals generated by the 380C. Its frequency may be that of the CLKI pin, or CLKI divided by two or times two. D15-0 Data Bus (input/output, active High, tri-state): This bidirectional 16-bit data bus is used for data transfer between the 380C and memory or I/O devices. In a memory word transfer, the even-addressed (A0=0) byte is transferred on D7-0, and the odd-addressed (A0=1) byte on D15-8. 8-bit memories should be connected to D7-0, while 8-bit I/O devices should be attached to D15-8 (this difference tends to equalize electrical loading). (See note under /BLEN pin description.) HALT, STANDBY Status (outputs, active Low): These two outputs indicate the status of the Z382 as follows: /HALT Mode /STNBY H H Normal instruction execution H L HALT instruction L H SLEEP Mode: clock runs but is blocked from most of the chip L L STANDBY Mode: oscillator is stopped Interrupt Requests (inputs): Asynchronous maskable interrupt inputs. Can be selected as low- or high-level sensitive, or as falling- or rising-edge triggered. Interrupt Request (input, active Low): /INT0 is logically ORed (positive-logic ANDed) with the interrupt requests from the on-chip Mimic, DMAs, and HDLC controllers, to create the processorOs /INT0 input.
1
/BUSACK
/BHEN
118
/BLEN
119
/BUSREQ
133
BUSCLK
127
D15-0
24 - 31 33 - 40
/HALT /STNBY
121 120
/INT3 /INT2 /INT1 /INT0
139 138 137 136
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PIN FUNCTIONS (Continued)
Table 4. MPU Signals Pin Name IOCLK Pin Number(s) 114 Description I/O Clock (output, active High, tri-state): This signal is a program controlled divided-down version of BUSCLK. The division factor can be two, four, six or eight with I/O transactions and interrupt-acknowledge transactions occurring relative to IOCLK. IOCLK can be disabled, in which case BUSCLK is the timing reference for I/O transactions. Note: The INTACK output of the Z380 has been omitted on the Z382 for pinning reasons. A similar signal can be easily obtained by low-active-ANDing (positive-logic ORing) the /M1 and /IORQ outputs. Input/Output Request (output, active Low, tri-state): This signal is active during all I/O read and write transactions and interrupt acknowledge transactions. Input/Output Read Strobe (output, active Low, tri-state): This signal is used to strobe data from the peripherals during I/O read transactions. Input/Output Write Strobe (output, active Low, tri-state): This signal is used to strobe data into the peripherals during I/O write transactions. I/O Chip Select (output, active Low): These outputs may be used to access external I/O devices. The base I/O address and range are programmable. Machine Cycle One (output, active Low, tri-state): This signal is active during instruction fetch and interrupt acknowledge transactions. Note that the Z382 does not support RETI decoding by Z80 peripherals (PIO), SIO, and CTC. It does support Z80-type interrupt daisy-chaining by devices that include explicit clearing of IUS (for example, SCC). Memory Read (output, active Low, tri-state): This signal indicates that the addressed memory location should place its data on the data bus. /MRD is active from the end of T1 until the end of T4 during memory read transactions. Memory Size (input/open-drain output, active Low): In 16-bit memory operations, this signal indicates whether the addressed memory location is word size (logic High) or byte size (logic Low). In the latter case, the 8-bit memory should be connected to the D7-0 lines, and an additional memory transaction on D7-0 will automatically be generated to transfer the other byte of the word. (See the note on pin name swapping after the /BLEN pin description.) /MSIZE is driven as an open-drain output by the memory decoding modules, when they are enabled in 8-bit mode and the address falls within their range.
/IORQ /IORD /IOWR /IOCS1 /IOCS2 /M1
115 125 123 45 46 116
/MRD
126
/MSIZE
117
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Z80382/Z8L382 High-Performance Data Communications Processors Table 4. MPU Signals
Pin Name /MWR
Pin Number(s) 124
Description Memory Write (output, active Low, tri-state): This signal indicates that the addressed memory location should store the data on the databus, as qualified by /BHEN and /BLEN. /MWR is active from the end of T2 until the end of T4 during memory write transactions. Nonmaskable Interrupt (input, falling edge-triggered): This input has higher priority than the maskable interrupt inputs /INT3-/INT0. Reset (input, active Low): This input must be active for a minimum of five BUSCLK periods to initialize the Z382. The effect of /RESET is described in detail in the Reset section. ROM Chip Select (output, active Low): After Reset, the Z382 drives this output and /MSIZE Low for all memory accesses with A23=0. Software can program the chip select logic to assert /ROMCS for a different range of memory addresses. If ROM is 16 bits wide and composed of two 8-bit devices, connect the Chip Select inputs of both devices to /ROMCS, and program the hardware not to force /MSIZE Low in the first two instructions of the ROM code. RAM Chip Select Low, High (outputs, active Low): After Reset, the Z382 drives /RAMCSL and /MSIZE Low for memory cycles with A23=1, and puts the /RAMCSH pin under control of its alternate use (a port pin). If RAM is only eight bits wide, connect its Chip Select input to /RAMCSL. If RAM is 16 bits wide, connect one of these pins to the chip select of each 8-bit RAM, and reprogram the hardware not to force /MSIZE Low, in which case /RAMCSL is qualified with /BLEN, and /RAMCSH is qualified with /BHEN. On the Z382 these signals have the same timing as address lines, so there is no timing penalty for this qualification. Timing Reference A (output, active Low, tri-state): This timing reference signal goes Low at the end of T2 and returns High at the end of T4 during a memory read, memory write or refresh transaction. It can be used to control the address multiplexer for a DRAM interface or as the /RAS signal at higher processor clock rates. /Timing Reference C (output, active Low, tri-state): This timing reference signal goes Low at the end of T3 and returns High at the end of T4 during a memory read, memory write or refresh transaction. It can be used as the /CAS signal for DRAM accesses. Timing Reference R (output, active Low, tri-state): This timing reference signal goes Low at the end of T1 and returns High at the end of T4 during a memory read, memory write or refresh transaction. It can be used as the /RAS signal for DRAM accesses. Wait (input, active Low): This input is sampled by BUSCLK or IOCLK, as appropriate, to insert Wait states into the current bus transaction.
1
/NMI /RESET /ROMCS
135 134 42
/RAMCSL /RAMCSH
43 44
/TREFA
111
/TREFC
110
/TREFR
112
/WAIT
130
. Table 5. UART, Timer and CSIO Signals Pin Name CKA0 CKA1 /CTS0 /CTS1 /DCD0 /DCD1 Pin Number(s) 53/92/96 49/65/100 61/111 60/110 89/112 66 Description Asynchronous Clock 0, 1 (Bidirectional): Clock signals to or from the asynchronous channels (ASCIs). Clear to Send 0, 1 (Inputs, active Low): Transmit control signals for the ASCI channels. Data Carrier Detect 0, 1 (Inputs, active Low): Receive control signals for the ASCI channels. /DCD1 is not available in ISA applications.
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PIN FUNCTIONS (Continued)
Table 5. UART, Timer and CSIO Signals /RTS0 /RTS1 RXA0 RXA1 TXA0 TXA1 CKS RXS TXS TOUT 88/93 94 52/90/99 55/67/103 51/91/98 54/87/102 58/64 57/63 56/62 46/109 Request to Send 0, 1 (Outputs, active Low, tri-state): Software-controlled output from the ASCI channels. Receive Data 0, 1 (Inputs): ASCI Receive data. Transmit Data 0, 1 (Outputs): ASCI Transmit data. Serial Clock (Bidirectional): The clock for the CSIO channel. Clocked Serial Receive Data (Input): Receive data for the CSIO channel. Clocked Serial Transmit Data (Output): Transmit data from the CSIO channel. Timer Out (Output, active High): Pulse output from PRT1.
Table 6. ISA Bus Signals Pin Name HD7-0 /HDOEN Pin Number(s) 78 - 85 62 Description Host Data Bus (Input/Output, tri-state): ISA or PCMCIA data bus. Host Data Output Enable (Output, active Low): This signal goes Low when the Host reads data from the Mimic, the I/O Mailbox, or the Plug and Play interface, and during Host DMA read cycles. Host Address (Input): Part of the ISA or PCMCIA address bus. The MS bits can be decoded by the built-in address decoder; bits 2-0 determine which Mimic register the Host accesses. Bits 11-10 are decoded only by the Plug and Play ISA module. Host Address Enable (Input): HAEN must be Low to qualify COM Port decoding, I/O Mailbox decoding, and Plug and Play decoding. To support 16-bit decoding of Host I/O addresses, provide an external decoder for HA15-12 and HAEN all Low and connect its Lowactive output to this pin. Host Write (Input, active Low): The Host drives this input Low to signal the Mimic that a write operation is taking place. Host Read (Input, active Low): This input is used by the Host to signal the Mimic interface that a read operation is taking place. Host Interrupt (Outputs, active High): One of these outputs is driven High by the Plug and Play module when the Mimic requests an interrupt from the Host. The unused signal is tristated. Host DMA Acknowledge (Inputs, active Low): These inputs indicate that the Host DMA controller has acknowledged the request and is transferring data. Host DMA Request (Outputs, active High, tri-state): These outputs request a DMA transfer operation from the Host.
HA11-0
64 - 67 69 - 76 63
HAEN
/HWR /HRD HINT1 HINT2 /HDAK0 /HDAK1 HDRQ0 HDRQ1
60 61 87 88 89 90 91 92
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Z80382/Z8L382 High-Performance Data Communications Processors Table 7. Parallel Ports
Pin Name PA7-0 PB7-0 PC7-0
Pin Number(s) 78 - 85 51 - 58 44 - 45, 47 - 49, 109, 101, 97 69 - 76
Description Parallel Ports A, B, C, D (Input/Outputs): These lines can be configured as inputs or outputs on a bit-by-bit basis. In an ISA or PCMCIA application, Ports A and D are not pinned out, the registers for Ports A and D are used by the Mimic function, and Ports B and C are selectively multiplexed with the on-chip peripherals (ASCIs, CSI/O, PRT). In other applications all four ports are available with minimal multiplexing.
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PD7-0
Table 8. HDLC Serial Channel and GCI/SCIT Signals Pin Name TxD0 TxD1 TxD2 RxD0 RxD1 RxD2 TxC0/FSC0 TxC1/FSC1 TxC2/FSC2 RxC0/BCL0 RxC1/BCL1 RxC2/BCL2 /TxEN0 /TxEN1 /TxEN2 DU DD DCL FSC Pin Number(s) 98 102 107 99 103 108 96 100 105 97 101 106 93 94 109 105 107 106 108 Description HDLC Transmit (outputs): These pins are used to transmit serial data from the HDLC controllers when they are not operating by means of the GCI/SCIT interface. HDLC Receive (inputs): These pins are used to receive serial data for the HDLC controllers when they are not operating by means of the GCI/SCIT interface. HDLC Transmit Clock/Frame Sync(input/outputs): In non-TDM, non-GCI modes, these can be used as external bit clock inputs or can be programmed to output the Tx clock. In non-GCI TDM mode, these pins carry the Frame Sync pulse. HDLC Clock/Bit Clock (inputs): Optional external bit clock inputs.
HDLC Transmit Enable (outputs, active Low): In a non-GCI TDM mode, these outputs indicate when an HDLC Transmitter is enabled and is in its active time slot. In non-GCI, nonTDM mode, these outputs are Low when the Transmitter is enabled. They can be used to enable an external driver on the TxD line. GCI/SCIT Data Upstream, Downstream (input/outputs, open-drain): The two bidirectional data streams of the GCI/SCIT interface. GCI/SCIT Clock (input): Bit clock for the GCI/SCIT interface. GCI/SCIT Frame Sync (input): This pin is used to synchronize the GCI/SCIT serial frames. This pin is driven active by Othe upstream deviceO (ISDN transceiver) at the start of each GCI/SCIT frame.
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PIN FUNCTIONS (Continued)
Table 9. PCMCIA Interface Signals Pin Name HA9-0 HD7-0 /PCIORD /PCIOWR /PCWE Pin Number(s) 66 - 67 69 - 76 78 - 85 61 60 89 Description PCMCIA Address Bus (inputs): Provide Host PC addressing of attribute memory, configuration registers, and Mimic. Decoded by the I/O address decoder. PCMCIA Data Bus (input/outputs): Used for data transfers between the Host PC and the Mimic, the attribute memory, and the configuration registers. PCMCIA I/O Read (input, active Low): Used to generate the INPACK signal when an I/O read cycle is within the configured range, and reads from the Mimic. PCMCIA I/O Write (input, active Low): This signal is used to write to the Mimic. PCMCIA Write Enable (input, active Low): Used to write to the attribute memory or to the configuration register which is addressed by means of HA9-1. Such an operation is recognized when /PCWE, /PCCE1, and /PCREG are all Low, and either the interface is configured for OI/O and memoryO operation, or /PCIRQ is High, signifying OreadyO, when configured as a Omemory onlyO interface. The data applied while /PCWE is Low are written to the attribute memory range on the positive edge of the /PCWE or Card-enable (/PCCE1) signal. PCMCIA Output Enable (input, active Low): /PCOE, /PCCE1, and /PCREG all Low signify a read from attribute memory or a configuration register as selected by HA9-1. PCMCIA Chip Enable 1 (input, active Low): /PCCE1 Low indicates a read or write access to: an even addressed byte in attribute memory, a configuration register, or the Mimic. PCMCIA Register Select (input, active Low): /PCREG Low indicates a read or write access to the attribute memory range or to the I/O address range. PCMCIA Input Acknowledge (Output, active Low): /INPACK goes Low while an I/O read access is performed within the configured I/O address range. If the PCMCIA interface is configured such that it reacts independent of the address to all I/O read cycles, then /INPACK is activated with /PCIORD. PCMCIA Interrupt Request (Output, active Low): After the PCMCIA interface is reset it is in a Omemory-onlyO mode, and this signal is driven Low to signify a Busy state until the 380C writes a register bit to say it is Ready. After the card is then configured by the Host, /PCIRQ goes Low to request a Host PC interrupt when the internal INT0 signal is asserted by the Mimic. /PCIRQ is monitored by the PCMCIA Host adapter and, dependent on the configuration, connected to one of the Host interrupts (for example, COM1 or COM2 interrupt). /PCIRQ can be programmed to be a pulsed interrupt with a minimal pulse length of one microsecond, or a level-interrupt that is reset when the interrupt is processed by the Host. This choice is made by means of bit 6 of the Configuration Option Register. PCMCIA Reset (input, active High): Setting PCRESET High resets the PCMCIA interface. The card configuration register is cleared and the PCMCIA interface operates in the Omemory-onlyO mode until it is configured again. The attribute memory has to be initialized by the controller, and the Ready/Busy (/PCIRQ) signal has to be deactivated. PCMCIA Status Change (output): This output is controlled by a bit in the PCMCIA moduleOs 380C Control Register.
/PCOE /PCCE1 /PCREG /INPACK
90 91 63 62
/PCIRQ
87
PCRESET
92
STSCHG
88
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Z80382/Z8L382 High-Performance Data Communications Processors Table 10. Other Signals
Pin Name CLKI
Pin Number(s) 128
Description
CLKO
IEI
IEO
VDD
VSS
Clock/Crystal (input, active High): An externally generated clock can be input at this pin. Alternatively, a crystal can be connected between CLKI and CLKO. In either case, the frequency at this pin can be used directly as the processor clock (BUSCLK), or divided by two or multiplied by two, under software control. 129 CLKO Crystal (output, active High): Crystal oscillator connection.This pin should be left open if an externally generated clock is input at the CLKI pin. Feedback on this pin can be disabled by software to save power and noise when an external clock is used. 47 Interrupt Enable In (input, active High): If external devices are connected to /INT0, and should have higher interrupt priority than the on-chip Mimic, DMAs, and HDLC controllers, this signal should be connected to the IEO output of the lowest-priority among such devices. 48 Interrupt Enable Out (output, active high): If external devices are connected to /INT0, and should have lower interrupt priority than the on-chip Mimic, DMAs, and HDLC controllers, this signal should be connected to the IEI input of the highest-priority such device. 5, 23, 41, 59, Power Supply: These eight pins carry power to the device. They must be tied to the same 77, 95, 113, voltage externally. 131 14, 32, 50, 68, Ground: These eight pins are the ground references for the device.They must be tied to 86, 104, 122, the same voltage externally. 140
1
FUNCTIONAL DESCRIPTION
The functional blocks within the Z382 can be broadly identified as central processing unit, host interface, serial communication channels, DMA control, timers and counters, and system interface logic. Each of these blocks will be further described in the sections which follow. For additional information, please refer to the Z382 UserOs Manual, available from your Zilog representative or distributor.
CENTRAL PROCESSING UNIT
The Central Processing Unit (CPU) core of the Z382 is the 380C (Z380), which is a binary-compatible extension of the Z80 and Z180 CPU architectures. High throughput rates for the 380C are achieved by a high clock rate, high bus bandwidth and instruction fetch/execute overlap. Communicating to the external world through an 8- or 16bit data bus, the 380C is a full 32-bit machine internally, with a 32-bit ALU and 32-bit registers. ros, as are the high-order words of the stack pointer and the I register. Thus, Native mode is fully compatible with the Z80 CPU's 64 KB address space. It is still possible to address memory outside of the 64 KB address space for data storage and retrieval in Native mode, however, as direct addresses, indirect addresses, and the high-order word of the SP, I and the IX and IY registers may be loaded with non-zero values. But executed code and interrupt service routines must reside in the lowest 64 KB of the address space. In Extended mode, all address manipulation instructions operate on 32 bits, potentially allowing access to a 4 GB address space. In both Native and Extended modes, however, the Z382 outputs only 24 bits of the address onto the external address bus, limiting the actual usable address space to 16 MB. Only the width of manipulated addresses distinguish Native from Extended mode. The 380C implements one instruction to allow switching from Native to Extended mode, but once in Extended mode, only Reset returns the CPU to Native mode. This restriction applies 35
Modes of Operation
The 380C can operate in either Native or Extended mode, as controlled by a bit in the Select Register (SR). In Native mode (the default configuration after Reset), all address manipulations are performed modulo 65536 (16 bits). In this mode the Program Counter (PC) only increments across 16 bits, all address manipulation instructions (increment, decrement, add, subtract, indexed, stack relative, and PC relative) only operate on 16 bits, and the Stack Pointer (SP) only increments and decrements across 16 bits. The program counter high-order word is left at all ze-
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CENTRAL PROCESSING UNIT (Continued)
because of the possibility of "misplacing" interrupt service routines or vector tables during the translation from Extended mode back to Native mode. In addition to Native and Extended mode, which is specific to memory space addressing, the 380C can operate in either Word or Long Word mode specific to data load and exchange operations. In Word mode (the reset configuration), all word load and exchange operations manipulate 16-bit quantities. For example, only the low-order words of the source and destination are exchanged in an exchange operation, with the high-order words unaffected. In Long Word mode, all 32 bits of the source and destination are exchanged. The 380C implements two instructions plus decoder directives to allow switching between Word and Long Word modes. The two instructions perform a global switch, while the decoder directives select a particular mode only for the instruction that they precede. Note that all word data arithmetic (as opposed to address manipulation arithmetic), rotate, shift and logical operations are always in 16-bit quantities. They are not controlled by either the Native/Extended or Word/Long Word selections. The exceptions to the 16-bit quantities are, of course, those multiply and divide operations with 32-bit products or dividends. Lastly, all word input/output operations are performed on 16-bit values. programmer to exchange the active file with the inactive file. The accumulator is the destination register for 8-bit arithmetic and logical operations. The six general-purpose registers can be paired (BC, DE, and HL), and are extended to 32 bits by the OzO extension to the register to form three 32-bit general-purpose registers. The HL register serves as the 16-bit or 32-bit accumulator for word operations. CPU Flag Register. The Flag register contains six flags that are set or reset by various CPU operations: Carry Add/Subtract Parity/Overow Half Carry Zero Sign
Index Registers. The four Index registers, IX, IXO, IY and IYO, each hold a 32-bit base address that is used in the Indexed addressing mode. The Index registers can also function as general-purpose registers with the upper and lower bytes of the lower 16 bits being accessed individually. Interrupt Register. The Interrupt register (I) is used in interrupt modes 2 and 3 for /INT0 to generate a 32-bit indirect address to an interrupt service routine. The I register supplies the upper 24 or 16 bits of the indirect address and the interrupting peripheral supplies the lower 8 or 16 bits. In the Assigned Vectors mode for /INT1-3, the upper 16 bits of the vector are supplied by the I register; bits 15-9 are the assigned vector base and bits 8-0 are the assigned vector unique to each of /INT1-3. Program Counter. The Program Counter (PC) is used to sequence through instructions in the currently executing program and to generate relative addresses. The PC contains the 32-bit address of the current instruction being fetched from memory. In the Native mode, the PC is effectively only 16 bits long, as carries from bit 15 to bit 16 are inhibited in this mode. In Extended mode, the PC is allowed to increment across all 32 bits. R Register. The R register can be used as a general-purpose 8-bit read/write register.
CPU Address Spaces
The 380C architecture supports five distinct address spaces corresponding to the different types of locations that can be accessed by the CPU. These five address spaces are: CPU register space, CPU control register space, memory address space, and I/O address space (on-chip and external). CPU Register Space The CPU register space is shown in Figure 26 and consists of all of the registers in the CPU register file. These CPU registers are used for data and address manipulation, and are an extension of the Z80 CPU register set, with four sets of this extended Z80 CPU register set present in the 380C. Access to these registers is specified in the instruction, with the active register set selected by bits in the Select Register (SR) in the CPU control register space. Primary and Working Registers. The working register set is divided into the two register files; the primary file and the alternate file (designated by O). Each file contains an 8bit Accumulator (A), a Flag register (F), and six generalpurpose registers (B, C, D, E, H, and L). Only one file can be active at any given time, although data in the inactive file can still be accessed. Exchange instructions allow the 36
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4 Sets of Registers A B D H IXU IYU A' B' D' H' IXU' IYU' F C E L IXL IYL F' C' E' L' IXL' IYL'
1
BCz DEz HLz IXz IYz
BCz' DEz' HLz' IXz' IYz'
Iz SPz PCz
R I SP PC
Figure 22. 380C Processor Core Register Set
Stack Pointer. The Stack Pointer (SP) is used for saving information when an interrupt or trap occurs and for supporting subroutine calls and returns. Stack Pointer relative addressing allows parameter passing using the SP. Select Register. The Select Register (SR) controls the register set selection and the operating modes of the 380C CPU. CPU Control Register Space The CPU control register space consists of the 32-bit Select Register (SR). The contents of SR determine the CPU operating mode, which register bank will be used, the interrupt mode in effect, and other items of this type. Memory Address Space The memory address space can be viewed as a linear space of 4 GB. The actual usable memory space in the Z382, however, is 16 MB, since only the lower 24 bits of the address are output on the external address bus. The 8bit byte is the basic addressable element in the 380C memory address space. However, there are other addressable data elements; bits, 2-byte words, byte strings, and 4-byte words. The size of the data element being ad-
dressed depends on the instruction being executed as well as the Word/Long Word mode. When a word is stored in memory, the least significant byte precedes the more significant byte of the word, as in the Z80 CPU architecture. Also, the lower-addressed byte is present on the upper byte of the external data bus. On-Chip and External I/O Address Space The 380C CPU architecture distinguishes between the memory and I/O spaces and, therefore, requires specific I/O instructions. I/O instructions are used to access the Z382Os internal peripherals as well as a number of control registers which deal with functions such as interrupts and traps. I/O instructions are also used to access external peripheral controllers connected to the Z382Os external address, data and control busses.
Data Types
The Z380 CPU can operate on bits, Binary-Coded Decimal (BCD) digits (4 bits), bytes (8 bits), words (16 bits or 32 bits), byte strings, and word strings. Bits in registers can be set, cleared, and tested. BCD digits, packed two to a byte, can be manipulated with the Decimal Adjust Accumulator instruction (in conjunction with binary addition and subtrac37
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CENTRAL PROCESSING UNIT (Continued)
tion) and the Rotate Digit instructions. Bytes are operated on by 8-bit load, arithmetic, logical, and shift and rotate instructions. Words are operated on in a similar manner by the word load, arithmetic, logical, and shift and rotate instructions. Block move and search operations can manipulate byte strings and word strings up to 64 KB or words long. Block I/O instructions have identical capabilities. Program Counter Relative Addressing An 8-, 16- or 24-bit displacement contained in the instruction is added to the Program Counter to generate the effective address. This mode is available only for Jump and Call instructions. Stack Pointer Relative Addressing The effective address of the operand is the location computed by adding the two's-complement signed displacement contained in the instruction to the contents of the Stack Pointer. Eight bits of index is the norm, but the DDIR IB and DDIR IW decoder directives allow 16- and 24-bit indexes, respectively.
Addressing Modes
Addressing modes are used by the 380C to calculate the effective address of an operand needed for execution of an instruction. Seven addressing modes are supported by the CPU. Of these seven, one is an addition to the Z80 CPU addressing modes (Stack Pointer Relative) and the remaining six modes are either existing or extensions to the Z80 CPU addressing modes. Register Addressing The operand is one of the 8-bit registers (A, B, C, D, E, H, L, IXU, IXL, IYU, IYL, A', B', C', D', E', H' or L'); or is one of the 16-bit or 32-bit registers (BC, DE, HL, IX, IY, BC', DE', HL', IX', IY' or SP) or one of the special registers (I or R). Immediate Addressing The operand is in the instruction itself and has no effective address. The DDIR IB and DDIR IW decoder directives allow specification of 24-bit and 32-bit immediate operands, respectively. Indirect Register Addressing The contents of a register specify the effective address of an operand. The HL register is the primary register used for memory accesses, but BC and DE can also be used. (For the JP instruction, IX and IY can also be used for indirection.) The BC register is used for I/O space accesses. Direct Addressing The effective address of the operand is the location whose address is contained in the instruction. Depending on the instruction, the operand is either in the I/O or memory address space. Sixteen bits of direct address is the norm, but the DDIR IB and DDIR IW decoder directives allow 24-bit and 32-bit direct addresses, respectively. Indexed Addressing The effective address of the operand is the location computed by adding the two's-complement signed displacement contained in the instruction to the contents of the IX or IY register. Eight bits of index is the norm, but the DDIR IB and DDIR IW decoder directives allow 16-bit and 24-bit indexes, respectively.
Instruction Set
The 380C instruction set is an expansion of the Z80 instruction set; the enhancements include support for additional addressing modes and a number of new instructions. The 380C is opcode compatible with the Z80 CPU and Z180 MPU. Thus, a Z80/Z180 program can be executed on the 380C without modification. The instruction set is divided into 12 groups by function; these are listed below. Consult the Z380 UserOs Manual for additional details on the instruction set. 8-bit Load/Exchange 16/32-bit Load, Exchange, Swap and Push/Pop Block Transfers and Search 8-bit Arithmetic and Logical Operations 16/32-bit Arithmetic Operations 8-bit Bit Manipulation, Rotate and Shift 16-bit Rotates and Shifts Program Control I/O Operations (Internal) I/O Operations (External) CPU Control Decoder Directives
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HOST INTERFACE
The host interface block in the Z382 includes the 16550 Mimic, the Host DMA Mailbox, the ISA PnP Interface and the PCMCIA Interface. Baud Rate Generator in the Mimic, allowing a wide range of data rates to be emulated. Two additional 8-bit timers are available for programming the FIFO timeout feature (Four Character-Time Emulation) for both the Receiver and the Transmitter FIFOs. The 16550 Mimic supports the PC Host interrupt structure by means of the Plug and Play ISA or PCMCIA interface modules. COM Port decoding is also provided by the same modules. A bit in the Z382 System Configuration Register controls whether the registers of the 16x50 Mimic interface are accessible in any page of I/O space, as on the Z8018x family, because only the lowest eight address lines are decoded, or whether A15-8 must be zero to access the registers. The Mimic Interface can transfer both Transmit and Receive data under control of the Z382Os DMA channels, thus minimizing processor overhead and maximizing throughput in high-speed applications.
1
16550 Mimic
The Z382 includes a 16x50 Mimic interface that allows it to emulate the operation of a PC UART. The interface allows the Z382 to be connected directly to an ISA bus or PCMCIA bus without any external circuitry. The Mimic contains the 16x50 register set and the same interrupt structure. The data path allows parallel transfer of data to and from the register set by the internal processor of the Z382. Control of the register set is maintained by six priority encoded interrupts to the Z382. When the PC Host reads or writes to certain Mimic registers, an interrupt to the Z382 is generated. Each interrupt can be individually masked off or all interrupts can be disabled by writing a single bit. Two 8-bit timers are also available to control the data transfer rate of the Mimic interface. Their input is tied to a
COM Port Decode from Plug and Play ISA or PCMCIA
16550 Mimic Side or Host Side Interface
4 Host Address Decode
Receive Timer Transmit Timer Z80380 Control/ Addr Conguration Register 380C MPU Side Interface 39
16550 Mimic Register Set 6
8
Z382 IRQ Control 8 Internal Data Bus
2 Host IRQ Host IRQ Host DMA Mailbox
Host DMA Control
Figure 23. 16550 Mimic Block Diagram
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HOST INTERFACE (Continued)
Mimic Receiver FIFO The receiver FIFO is 16-words deep and stores eight data bits and three error bits (Parity error, Framing error and Break detect) for each character received. The data and error bits move together in the FIFO. The error bits become available to the Host side of the interface when that particular location becomes the next address to read (top of FIFO). At that time they may either be read by the Host or they may cause an interrupt to the Host interface if so enabled. The error bits are set by the error status of the byte at the top of the FIFO but may only be cleared by reading the Line Status Register (LSR). If successive reads of the receiver FIFO are performed without reading the LSR, the status bits will be set if any of the bytes read have the respective error bit set. The Host interface may be interrupted when 1, 4, 8 or 14 bytes are available in the receiver FIFO. If the FIFO is not empty, but below the programmed trigger value, a timeout interrupt is available if the receiver FIFO is not written by the 380C or read by the Host by an interval determined by the Character Timeout Timer. This is an additional timer with 380C access only which is used to emulate the 16550 four-character timeout delay. The timer receives the BRG as its input clock. Software must determine the correct values to program into the Receiver Timeout Register and the BRG to achieve the correct delay interval for timeout. These interrupts are cleared by the FIFO reaching the trigger point or by resetting the Timeout interval timer by a FIFO 380C write or Host read access. With FIFO mode enabled, the 380C is interrupted when the receiver FIFO is empty. This bit corresponds to a Host read of the receiver buffer in non-FIFO (16450) mode. The interrupt source is cleared when the FIFO becomes nonempty or the 380C reads the IUS/IP register.
MPU Write LSR Shadow B2-B4 Internal Clock 380C MPU Side Interface MPU Control Line
3
3
PC Read LSR Shadow B2-B4 Internal Clock 16550 Mimic or PC Side Interface
16 x 8 Data Bits
16 x 3 Error Bits
READ BUFFER
Sync
WRITE BUFFER
Sync
PC Control Line
MPU Databus (MPU Side Write) Internal Clock MPU IRQ
8
8
PC Databus (PC Side Read) FIFO Control Register PC IRQ
Write Pointer
ALU
Read Pointer
5
Figure 24. 16550 Mimic Receiver FIFO Block Diagram
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Zilog Transmitter FIFO The transmitter FIFO is 16-bytes deep with Host write and 380C read access. In FIFO mode, the Host will receive an interrupt when the transmitter FIFO becomes empty. The interrupt is cleared when the transmitter FIFO becomes non-empty or the IIR register is read by the Host.
Z80382/Z8L382 High-Performance Data Communications Processors On the 380C interface, the transmit FIFO can be programmed to interrupt the 380C on 1, 4, 8 or 14 bytes of available data. A timeout feature exists, Transmitter Timeout Timer, which is an additional 8-bit timer with the BRG as the input source. If the transmitter FIFO is non-empty and no Host write or 380C read of the FIFO has taken place within the timer interval, a timeout will occur, causing a corresponding interrupt to the 380C.
1
Internal Clock MPU Control Line
Internal Clock PC Control Line
READ BUFFER
Sync
Sync
MPU Side Interface
16X8 Data Bits
MPU Databus (MPU Side Read) FIFO Control Register MPU IRQ 5
8
8
PC Databus (PC Side Write) Internal Clock PC IRQ
Read Pointer
ALU
Write Pointer
Figure 25. 16550 Mimic Transmitter FIFO Block Diagram
Transmit And Receive Timers Because of the speed at which data transfers can take place between the Z382 and the Host, two timers have been added to alleviate any software problems that a high speed data transfer might cause. These timers allow the programmer to slow down the data transfer to simulate the Mimic receiving and transmitting the data serially. The timers receive their input from the Mimic BRG clock. This allows the programmer access to a 24-bit timer to slow down the data transfers.
Mimic Programming Registers The Mimic module contains a set of registers for programming various aspects of Mimic operation. These are: 380C I/O Address %00FF %00EF %00FE %00FD %00FC %00EC %00EA %00EB %00FA %00FB
Register Mimic Master Control Register Mimic DMA Control Register Mimic IUS/IP Register Interrupt Enable Register Interrupt Vector Register FIFO Status and Control Register Rx Timeout Time Constant Register Tx Timeout Time Constant Register Transmitter Time Constant Register Receiver Time Constant Register
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Z80382/Z8L382 High-Performance Data Communications Processors
Zilog
HOST INTERFACE (Continued)
Mimic-Host Interface Registers In addition to the Mimic programming registers, the Z382 contains a register set for interfacing with the Host by means of the Mimic. These registers are used to emulate the 16550 UART so that the Host can access these registers just as if it was interfacing with the UART. This provides software compatibility with existing Host communication software. The registers are: Host Address1 %002 %002 %012 %02 %03 %04 %05 %06 %07 %013 %003 %02 -380C I/O Address %00F0 %00F0 %00F1 -%00F3 %00F4 %00F5 %00F6 %00F7 %00F9 %00F8 %00E9 %00E9
Host DMA Mailbox
The Host DMA Mailbox facility provides a path for Host DMA data transfers separate from the Mimic COM port. Commands and data flow over the COM port, while the DMA path can be used for other purposes. The Host DMA Mailbox feature includes control registers that allow Host DMA data transfer between Host memory and, for example, a modem speaker/microphone codec. Transfers are driven by the HostOs DMA on one side; Z382 DMA channel(s) or programmed I/O can be used on the other side. Thus, several modes of operation can be programmed: Host DMA Write, Z382 Polled Input Host DMA Read, Z382 Polled Output Host DMA Write with Z382 DMA Host DMA Read with Z382 DMA
Register Receiver Buffer Register Transmit Holding Register Interrupt Enable Register Interrupt ID Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratch Register Divisor Latch MS Byte Divisor Latch LS Byte FIFO Control Register Mimic Modication Reg.
On the ISA bus, the Z382 can use two independent DMA Mailbox facilities. When either of these facilities is enabled in the Plug and Play module, that module signals a DMA request by driving HDREQ0 or HDREQ1 High; if a facility is disabled, the corresponding HDREQ pin is tri-stated. A Low on one of the Acknowledge signals, /HDACK0 or /HDACK1, more or less simultaneously with /HWR or /HRD Low when the corresponding HDREQ line is being driven High, indicates a DMA cycle. In a PCMCIA socket, only one DMA Mailbox can be used. When an option bit in one of the PCMCIA registers is 1, a DMA request is signalled by setting the /INPACK output low. A DMA cycle is signalled by having the /PCREG line High while /PCIORD or /PCIOWR goes Low.
Note: 1. The host address is relative to the Mimic base address d coded by the PnP ISA or PCMCIA modules in the Z382. 2. DLAB (LCR[7]) = 0. 3. DLAB (LCR[7]) = 1.
Baud Rate Generator The Baud Rate Generator (BRG) provides emulation timing for the Mimic. The BRG output clocks the Mimic emulation counter, while the BRG itself is clocked by the BUSCLK output of the 380C. Two 8-bit registers are provided to program the BRG time constant. Design is such that onthe-fly modification of the registers does not cause irregular BRG output.
Plug and Play Interface
This module, with support from appropriate Z382-based firmware, complies with version 1.0a of the Microsoft /Intel OPlug and Play ISAO specification. The Z382Os PnP module provides for I/O address decoding, interrupt channel selection and DMA channel selection. Pin limitations constrain the internal address decoding for I/O addresses to 12 bits. Since 16-bit decoding is preferred for full Plug and Play compliance, an additional input, HAEN, is provided which must be Low for a valid address decode. This permits external decoding of HA15-12.
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Internal Address/Data/Control Bus
1
Key Detect
Isolation, Identification and Configuration Controller
ISA - PnP Read/Write Logic Address Port Write Data Port Read Data Port
PnP Registers Control I/O Address Decoder Interrupt Request Router DMA Req/Ack Router Mimic I/O Mailbox Z382 Interrupt Request Z80382 DMA Req/Ack
Configuration
Host ISA Address/Data/Control Bus
Figure 26. Plug and Play Interface
ISA Ports The PnP interface implements three 8-bit ports on the ISA bus. The OAddressO port is a write-only port at the fixed address 0279H. The OWrite DataO port is a write-only port at the fixed address 0A79H. The ORead DataO port is a readonly port at a programmable address among 0203H, 0207H, 020BH, ..., 03FFH. The Host may write to the Address port for three reasons: 1. As part of sending an OInitiation keyO to all the PnP cards in the system. 2. To select a register on one or all PnP cards as the destination of a subsequent write to the Write Data port. 3. To select a register on one card, or the OIsolationO facility on multiple cards, as the source of data in a subsequent read from the Read Data port.
Basic Operation The space that the Host can access by writing to the Address port, and then writing to the Write Data port or reading from the Read Data port, is in large part also accessible to the 380C processor. Its 256 locations are sparsely populated with hardware registers. After reset, and on command from host software, including in normal operation, the PnP interface is said to be in OWait for KeyO state. In this state, none of the PnP locations are accessible to the Host on the ISA bus. Before accessing any of these locations, the Host must first do a specified sequence of 34 write operations, called an Initiation key, to the Address port before it can access any of the registers of the PnP interface. The Initiation key is detected by the PnP interface hardware.
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HOST INTERFACE (Continued)
Each PnP card manufactured must have a non-zero 64-bit identity value that is divided into a 16-bit vendor ID, a 16bit product ID including revision, and a 32-bit serial number. 380C firmware has complete control of this number; no mechanism for storing or determining it is included in the PnP interface. After sending an Initiation key, the Host can only access a few of these registers in a defined sequence, called the Isolation protocol, which selects the PnP card with the 64bit value having the most low-order ones, among those in the system. The timing requirements of the Isolation protocol are quite slow compared to the speed of the 380C processor, and the 64-bit ID and an associated 8-bit checksum are sequenced to the PnP interface by the 380C, on a polled or interrupt-driven basis. After OisolatingO a card by means of the Isolation protocol, host software assigns the OisolatedO card a OCard Select NumberO (CSN), starting with 01H and ascending for subsequent cards. Assigning a CSN eliminates the card from future repetitions of the protocol. Then, or later, host software reads the characteristics of the card, called the Resource Data, in a handshake manner with 380C firmware. Host software repeats this process until it determines that it has seen all of the PnP cards in the system. Then it allocates resources including memory and I/O space addresses, interrupt levels, and DMA channels, and uses the various cardsO CSNs to write these allocations to OConfiguration registersO in the PnP register space. Finally, host software places all the PnP interfaces in the system back in OWait for KeyO state, in which they perform address decoding and interface the interrupt and DMA requests and acknowledgments, but have no affect on other system operations. If the host software thereafter determines that the system needs reconfiguring, it sends another Initiation key. In this case, however, it can address a specific card using the previously assigned CSN. Configuration Registers The following Configuration registers are implemented in the Z382 to provide for the resources required by the host to interface to the host-accessible functions within the chip: I/O Mailbox I/O Address Mimic I/O Address Interrupt Request Level - can be selected to be output on either of the two available interrupt output lines. A unique Z382 feature allows these two pins to be congured to be any two of the ISAbus interrupt lines. DMA Channel 0, DMA Channel 1 - A unique Z382 feature allows the two DMA pin pairs to be congured to be any two of the seven ISA-bus DMA channels.
Host writes to the Configuration registers are effective immediately, in hardware, so there is no urgent need for the 380C processor to OtranslateO them into other register values. But the 380C processor can use the interrupt that occurs when the Host terminates Configuration state to examine what the Host has done to the Configuration registers, and operate accordingly in the future.
PCMCIA Interface
The PCMCIA Interface block integrates all the functions necessary for the operation of I/O interface cards in a PCMCIA 2.0 and 3.0 socket. These functions are: PCMCIA Interface Control Attribute Memory Conguration Registers I/O Interface Congurable Address Decoder Congurable Interrupt Logic Z380 Interface
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Internal Address/Data/Control Bus
1
Attribute Memory
(see Figure 32 below)
PCMCIA Interface Control
Configuration Registers
I/O Address Decoder
Mimic Chip Select
Host PCMCIA Address/Data/Control Bus
Figure 27. PCMCIA Interface
PCMCIA I/O Interface Control The I/O interface contains the main functionality of the PCMCIA block. The interface decodes addesses for I/O accesses by the Host according to the PCMCIA standard. The Host writes to the Configuration Option Register an index to select the base address of the desired I/O address range. After configuration, I/O accesses to this address range are recognized, and the Mimic chip select is asserted when a valid I/O access is performed and the address is in the configured address range. Attribute Memory The attribute memory is the primary mechanism for transfers of configuration data and status between the host system and the PCMCIA card. As shown in Figure 32, the attribute memory is segmented into several sections. The Card Information section is 240 bytes of RAM which is loaded by the 380C with information describing the card and its resource requirements, data needed by the Host to configure the card. A portion of the attribute memory allows the host to access the I/O Mailbox registers. Lastly,
sections in the attribute memory space are assigned to the Configuration Registers and the Base Address Registers. On the Host side, attribute memory is accessible only on even byte addresses. On the 380C side it can be accessed as bytes or words.
0206
I/O Mailbox
0200 01FE 01FF
Card Information (RAM)
0110 010E 0100 00FE 00F0 00EE 0188 0187 0180 017F 0178 0177
Conguration Registers Base Address Registers
Card Information (RAM)
0000 0100
Figure 28. PCMCIA Attribute Memory Organization
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Host Address
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HOST INTERFACE (Continued)
Base Address Registers These seven registers are written by the 380C with the base addresses of 8-byte windows in the hostOs I/O address space which the host can use to communicate with the host-accessible registers in the Mimic. Configuration Registers There are five configuration registers of the PCMCIA 3.0 standard and additionally a version number register, two image base address registers, and the seven base address registers described above. The Host accesses these registers to configure the interface and to retrieve status. Configuration Option Register. This register is used on one side to configure the PCMCIA interface, controlling items such as type of interrupt, DMA enable, and selection of the Base Address Register. On the other side, a reset can be triggered by setting a certain bit. Card Configuration and Status Register. This register contains information about the status of the interface, including whether certain signals have changed, interrupts, and power down. Pin Replacement Register. This register is used to provide the status information which is otherwise provided on the /PCIRQ pin (RDY/BSY). Socket and Copy Register. The Socket and Copy register is implemented for PCMCIA hosts expecting this optional PCMCIA register in a PCMCIA card. The register has no function in the Z382. Extended Status Register.The extended status register is used to enable and provide status information of external events. Image Base Address Registers. These registers deliver a copy of the configured base address. Interface Version Number Register. This register provides the version number of the PCMCIA interface. It also contains a bit which can be written to disable attribute memory write protection, allowing the host to write to the attribute memory. Z380 Control Register. The Z380 Control Register (ZCR) controls the functions of the PCMCIA block by means of the Z380 controller. Accessible only to the 380C, it controls access to the attribute memory by the 380C and allows the 380C to signal major status changes to the host. Decoding and Routing Functions The PCMCIA interface uses the values programmed in the Configuration Registers to decode a Mimic chip select when the host I/O address signals match the programmed conditions. Unlike the Plug and Play interface the PCMCIA interface does not perform any routing functions on interrupt and DMA control signals. These are performed at the PCMCIA socket controller on the host side.
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DMA CHANNELS
The DMA channels of the Z382 build on ZilogOs experience with the Z16C32 IUSC. They have only one mode of operation, which combines features of the IUSCOs Array and Linked List modes. Each DMA channel has a pointer into a list structure, entries in which contain the addresses and lengths of data buffers. Since the on-chip peripherals of the Z382 all operate with 8-bit data only, particularly the HDLC channels which the DMA channels are primarily intended to serve, the DMA channels also perform only 8-bit data transfers when operating with data buffers. However, because fetching a new list entry is an overhead operation that can compromise maximum data rates, list accesses use 16-bit transfers. proceeds to fetch the first Olist entryO from memory, beginning at the address in the LAR. List entries always begin at an 8-byte boundary, that is, at an address having its LS three bits O000O. The general format of a list entry includes eight bytes: Address of Byte Address 7-0 Address 15-8 Address 23-16 should be 00 Type/Status should be 00 Length 7-0 Data Request Terminate Type Fetch Data Acknowledge End of Buffer Store Status Device to DMA Device to DMA DMA to device DMA to device DMA to device DMA to device Length 15-8 [LAR23-3] + 000 [LAR23-3] + 001 [LAR23-3] + 010 [LAR23-3] + 011 [LAR23-3] + 100 [LAR23-3] + 101 [LAR23-3] + 110 [LAR23-3] + 111
1
DMA Channel/Device Interface
The interface between the DMA channel and its client device includes six lines:
Figure 29. General Format of a DMA List Entry The Type/Status byte defines various kinds of list entries, as follows: 00 01 02 03 04 05 40-7F 80-BF C0-FF End of List Transfer in List Ready Buffer, no Command, no End of Buffer notication Ready Buffer, no Command, notify device at End of Buffer Buffer in Progress Completed Buffer (no Status) Ready Buffer, with Command, no End of Buffer notication Ready Buffer, with Command, notify device at End of Buffer Completed Buffer (with Status)
All of these lines are bused, and are driven by the DMA channel and its client device that are currently selected by the DMA scanner.
Operation
A DMA channel starts operating when software loads an address into its List Address Register (LAR). Writing the final (MS) byte of this register sets the channelOs Run bit, which makes it request bus access from the processor. When the processor grants bus access, the DMA channel
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Zilog
DMA CHANNELS (Continued)
On fetching any Type/Status value except Transfer in List or Ready Buffer, the DMA channel clears its Run bit and requests an interrupt if its List Interrupt Enable bit is 1. This checking of the Type/Status byte helps prevent disorderly operation as well as buffer-ring wraparound. On fetching a Transfer in List entry, the DMA channel fetches the Address portion of the entry, loads it into its LAR, and proceeds to fetch another list entry from that address. This is the mechanism by which buffer rings and linked lists are constructed. If software needs to know when a certain amount of data has been sent or received, such as an Address field in a received HDLC frame, it can set up a buffer of that length with its own list entry. The DMA channel can provide an interrupt at the end of the buffer if desired. When a DMA channel fetches a Type/Status byte from memory, it asserts the Type Fetch signal to its client device. This prompts the client device to capture the Command if bits D7-6 of the Type/Status byte are 01 or 10. For example, the HDLC Transmitter uses the three LS bits of such a Type/Status byte to indicate how many bits to send from the last byte of the frame. The HDLC Receiver doesnOt use any Command bits, so that Ready Buffer codes, with and without Command, are equivalent for HDLC reception. Upon fetching any Ready Buffer entry, the DMA channel rewrites the Type/Status byte to the OBuffer in ProgressO code, and then fetches the Address and Buffer Length fields and loads them into its Buffer Address and Length Registers (BAR and BLR) respectively. Thereafter the DMA channel transfers data into or out of the buffer, under control of the Data Request line from its client device. If there is no request at this point, as would typically be the case when software starts a OreceiveO channel, the DMA channel relinquishes bus control to the processor or another DMA channel, and goes idle until the device asserts Data Request and/or Terminate. For Type/Status bytes requesting ONotify device at end of bufferO, the DMA channel will assert its clientOs End of Buffer line at the appropriate time. Once a DMA channel has been started and has fetched its first list entry, it does nothing further unless and until its client device asserts Data Request and/or Terminate. When the client devices does so, the DMA channel requests bus access from the processor. When access is granted, or when it is continuing operation after fetching a list entry, the DMA channel proceeds as follows: If the device is asserting Data Request, with or without Terminate: a. The DMA channel asserts Data Acknowledge to the device. b. If its BLR indicates the buffer is ending, and the Status/Type byte for this buffer said ONotify DeviceO, the DMA channel also asserts the End of Buffer signal. c. At the same time, the DMA channel places the address in its BAR on the address bus, and sets the control signals for a memory read or write per the I/O bit in its DMA Control/Status Register (DCSR). d. Depending on the data direction, Data Acknowledge makes the device either provide a byte of data on the data bus, or capture a byte of data from the data bus. How (and whether) a client device uses OEnd of BufferO is device-dependent. The HDLC Transmitter passes this indication through its TxFIFO, and terminates the Tx frame after sending the data with which the DMA channel asserted End of Buffer. (Because of this facility, the only time that an OunderrunO may occur at the HDLC Transmitter is when the DMA doesnOt provide data fast enough, INSIDE a frame.) The HDLC Receiver doesnOt do anything with OEnd of Buffer,O so Ready Buffer codes with or without OEOBO are equivalent for HDLC receiving. At the end of each data transfer, the DMA channel increments the BAR by 1 and decrements the BLR by 1. If the device signalled Data Request but not Terminate, and the Buffer Length Register has not been counted down to zero, and the Burst bit in the channelOs DCSR is set, the DMA channel checks Data Request again. If Burst is 0, and/or if the device negates Data Request, the channel gives the bus back to the processor or another DMA channel, else it goes back to do another data transfer.
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Zilog If the device signalled Data Request, but not Terminate, and the Buffer Length Register has now been counted down to zero, the DMA channel proceeds as follows: a. It puts the address of the Type/Status byte (from the LAR) on the address bus, and writes the code for OCompleted Buffer (no Status)O into that byte. If the DMA channelOs Buffer IE field indicates Ointerrupt for all buffersO, or Ointerrupt for Notify buffersO and this was a Notify buffer, it sets its IP bit to request an interrupt. It increments the LAR to the address following this list entry, and goes back to fetch a new list entry from that address, as described above.
Z80382/Z8L382 High-Performance Data Communications Processors
Per-Channel Registers
There are eight DMA channels in the Z382. Each channel includes the following registers: List Address Register Buffer Address Register Buffer Length Register DMA Control/Status Register (LAR, 21 bits) (BAR, 24 bits) (BLR, 16 bits) (DCSR, 8 bits)
1
b.
c.
The LAR and DCSR are read/write registers; software can track the progress of a DMA by monitoring its LAR. BARs and BLRs are accessible only by using special modes selected in the centralized DMA Control Register; the channel stores ending BLR values in the list. List Address Register A three-byte register whose 21 most significant bits contain the base address of the current list. The DMA channel begins operation when the 380C writes the most significant byte of this register. The DMA controller updates this register as it processes new lists in response to links from previous lists. The three LS bits of the LAR are ignored on writing, and always read back as 100 (thus pointing at the current Type/Status byte in the list). Buffer Address Register The DMA controller loads the initial value of the current buffer address into this register from the address field of the current list. At the end of each data transfer, the DMA channel increments the BAR by one. Buffer Length Register The DMA controller loads the initial value of the current buffer length into this register from the buffer length field of the current list. At the end of each data transfer, the DMA channel decrements the BLR by one.
Terminate The HDLC receiver asserts this signal for an End of Frame, Abort, or Overrun condition. The HDLC Transmitter does so for an Underrun condition. After the DMA channel transfers a byte, if the device signals Data Request and Terminate, or if the device signals Terminate without Data Request, the DMA channel proceeds as follows: Note: If the device encounters an error from which operation canOt continue without processor attention, then after signalling Terminate and storing a status byte as described above, the device should refrain from asserting Data Request until software has done so. (The HDLC Transmitter does this for Underrun.) a. It places the address of the Length field on the address bus, and writes the current (16-bit) value in its BLR to memory at that address and the next higher address. This value enables software to tell how much data was actually written into, or read out of, this buffer. It puts the address of the Type/Status byte on the address bus, sets the control signals for a memory write, signals OCompleted Buffer (with Status)O, and asserts the Store Status signal to the device. In response to Store Status, the device can place up to 6 bits of status on D5-0. For the HDLC receiver, this status includes Overrun, End of Frame, Abort, CRC Error, and the residual bit count. For the HDLC Transmitter, only Underrun will prompt a Terminate indication, so the specific status bits are unimportant.
1. After the Type/Status byte has been written, the DMA channel advances the LAR over this list entry, in other words, to the address of the next entry.
b.
c.
d.
e.
f.
If the DMA channelOs Buffer IE field indicates anything other than Ono buffer interruptsO, it requests an interrupt. The DMA channel then goes back to fetch another list entry from the address in the LAR, as described above.
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DMA CHANNELS (Continued)
DMA Control/Status Register Controls items such as I/O Direction, enabling/disabling Burst Mode, and enabling and disabling interrupts. Also provides certain per channel DMA and interrupt status conditions. DMA Control Register (DMACR) This register controls when bus control is returned to the 380C processor after a DMA channel has operated. It also provides modes whereby the Buffer Address and Buffer Length per-channel registers can be read and written. DMA Vector Register (DMAVR This register contains the base interrupt vector for the DMA channels. It also identifies, during an interrupt acknowledge cycle, the interrupting DMA Channel.
Centralized DMA Registers
Two registers provide overall control and status of the DMA subsystem:
s s
DMA Control Register DMA Vector Register
(DMACR) (DMAVR)
SERIAL COMMUNICATION CHANNELS
The Z382 provides several means of serial data communications. These are the Asynchronous Serial Communication Interface (ASCI), the HDLC controllers, the GCI/SCIT interface and the Clocked Serial I/O Channel.
s
Up to three modem control signals per channel, depending on operating mode of the Z382 Programmable interrupt conditions Four level data/status FIFOs for the receivers Receive parity, framing and overrun error detection Optional operation with on-chip DMA controllers
s s s s
Asynchronous Serial Communications Interface (ASCI)
The Z382 provides two independently programmable ASCIs (UARTs), each including a flexible baud rate generator. Key features of the ASCIs include:
s s
Full-duplex operation Programmable data format 7- or 8- data bits with optional ninth bit for multiprocessor communication One or two stop bits Odd, even or no parity Programmable baud rate generator Divide-by-one, divide-by-16 and divide-by-64 modes
Figure 34 below illustrates the major functional blocks within the ASCI. Transmit Data Register Data written to the ASCI Transmit Data Register (TDR) is transferred to the Transmit Shift Register (TSR) as soon as the TSR is empty. Data can be written while the TSR is shifting out the previous byte of data, providing double buffering for the transmit data. Data transfers into the TDR can be performed using I/O instructions or by using one of the DMA channels. This DMA process loads characters into the TDR as an associated status bit indicates that it has become available for data.
s
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Z80382/Z8L382 High-Performance Data Communications Processors
Internal Address/Data Bus
1
ASCI Transmit Data Register Ch 0: TDR0 TXA0 ASCI Transmit Shift Register * Ch 0: TSR0 ASCI Receive Data FIFO Ch 0: RDR0 RXA0 /RTS0 /CTS0 /DCD0 ASCI Receive Shift Register * Ch 0: RSR0 ASCI Control Register A Ch 0: CNTLA0 ASCI Control Register B Ch 0: CNTB0 ASCI Status FIFO/Register Ch 0: STAT0 ASCI Extension Control Reg. Ch 0: ASEXT0 ASCI DMA Control Ch 0: ADCR0 ASCI Time Constant High Ch 0: ASTC0H ASCI Time Constant Low Ch 0: ASTC0L CKA0 Baud Rate Generator Channel 0 Note: ASCI Control Interrupt Request ASCI Transmit Data Register Ch 1: TDR1 ASCI Transmit Shift Register * Ch 1: TSR1 ASCI Receive Data FIFO Ch 1: RDR1 ASCI Receive Shift Register * Ch 1: RSR1 ASCI Control Register A Ch 1: CNTLA1 ASCI Control Register B Ch 1: CNTB1 ASCI Status FIFO/Register Ch 1: STAT1 ASCI Extension Control Reg. Ch 1: ASEXT1 ASCI DMA Control Ch 1: ADCR1 ASCI Time Constant High Ch 1: ASTC1H ASCI Time Constant Low Ch 1: ASTC1L Baud Rate Generator Channel 1 CKA1 RXA1 /RTS1 /CTS1 /DCD1 TXA1
*Not Program Accessible
Figure 30. Asynchronous Serial Communications Interface (ASCI) Block Diagram
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SERIAL COMMUNICATION CHANNELS (Continued)
Transmit Shift Register When the ASCI Transmit Shift Register receives data from the ASCI Transmit Data Register, the data is shifted out to the TxA pin. When transmission is completed, the next byte (if available) is automatically loaded from the TDR into the TSR and the next transmission starts. If no data is available for transmission, the TSR idles at a continuous High level. Receive Shift Register When the receiver is enabled, the RXA pin is monitored for a low. One-half bit time after a low is sensed at RXA, the ASCI samples RXA again. If it has gone back to High, the ASCI ignores the previous low and resumes looking for a new one, but if RXA is still low, it considers this a start bit and proceeds to clock in the data based upon the internal baud rate generator or the external clock at the CKA pin. The number of data bits, parity, multiprocessor and stop bits are selected by means of control bits in the CNTLA and CNTLB registers. After the data has been received, the appropriate MP, parity and one stop bit are checked. Data and any errors are clocked into the receive data and status FIFOs during the stop bit if there is an empty position available. Interrupts, Receive Data Register Full Flag, and DMA requests will also go active during this time. If there is no space in the FIFO at the time that the RSR attempts to transfer the received data into it, an overrun error occurs. Receive Data FIFO When a complete incoming data byte is assembled in the RSR, it is automatically transferred to the FIFO, which serves to reduce the incidence of overrun errors. The top (oldest) character in the FIFO (if any) can be read by means of the Receive Data Register (RDR). An overrun occurs if the receive FIFO is still full when the receiver completes assembly of a character and is ready to transfer it to the FIFO. If this occurs, the overrun error bit associated with the previous byte in the FIFO is set. The latest data byte is not transferred from the shift register to the FIFO in this case, and is lost. Once an overrun occurs, the receiver does not place any further data in the FIFO until the last good byte received has come to the top of the FIFO and sets the Overrun latch, and software then clears the Overrun latch. When a break occurs (defined as a framing error with the data equal to all zeros), the all-zero byte with its associated error bits are transferred to the FIFO if it is not full. If the FIFO is full, an overrun is generated, but the break, framing error and data are not transferred to the FIFO. Any time a break is detected, the receiver will not receive any more data until the RXA pin returns to a high state. Data transfers from the receive FIFO can be performed using I/O instructions or by using one of the DMA channels. This DMA process reads characters from the RDR as an associated status bit indicates that data is available. The RxDMA request is disabled when any of the error flags (PE, FE or OVRN) is set, so that software can identify with which character a problem is associated. ASCI Status FIFO/Register This FIFO contains Parity Error, Framing Error, Rx Overrun, and Break status bits associated with each character in the receive data FIFO. The status of the oldest character (if any) can be read from the ASCI status register, which also provides several other, non-FIFOed status conditions. The outputs of the error FIFO go to the set inputs of software-accessible error latches in the status register. Writing a 0 to the Error Flag Reset (EFR) bit in CNTLA is the only way to clear these latches. In other words, when an error bit reaches the top of the FIFO, it sets an error latch. If the FIFO has more data and the software reads the next byte out of the FIFO, the error latch remains set and does so until the software writes a 0 to the EFR bit. The error bits are cumulative, so if additional errors are in the FIFO they will set any unset error latches as they reach the top. Baud Rate Generator The baud rate generator has two modes. The first is the same as that used in most previous Zilog processors, such as the Z80180, and provides a dual set of fixed clock divide ratios. In the second mode, the BRG is configured as a sixteen-bit down counter that divides the processor clock by the value in a software accessible, sixteen-bit, time constant register. This allows virtually any frequency to be created by appropriately selecting the main processor clock frequency. The BRG can also be disabled in favor of an external clock on the CKA pin. The Receiver and Transmitter will subsequently divide the output of the Baud Rate Generator (or the signal from the CKA pin) by 1, 16 or 64 under program control.
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Zilog ASCI Register Set Each ASCI contains a set of registers for programming various aspects of its operation. These registers are:
s s s s s s s s s s
Z80382/Z8L382 High-Performance Data Communications Processors Software can select whether each channelOs I/O is on device pins or on the internal TDM highway (the GCI/SCIT bus in the Z382). If device pins are used, they can be configured as either a classic synchronous serial interface, or as the interface to an external TDM highway or highways. The differences in pin use are as follows: Full Time Operation
Control Register A Control Register B Time Constant High Register Time Constant Low Register Extension Control Register Status Register Receive Data Register Transmit Data Register DMA Control Register Control Register A
1
Pin TxD
TDM Operation
HDLC Serial Channels
The Z382 features three high-speed serial channels, each comprised of a transmitter and a receiver, which can operate in HDLC or transparent (unframed) modes. All data transfers to and from the HDLC channels are carried out by the DMA channels. Thus, each HDLC channel must have an assigned DMA channel to perform its function. Facilities for interrupt-driven or polled transfer of HDLC data are not provided.
Tri-stated outside the timeDriven full time slot. RxD Sampled within the time Sampled in every slot. bit time RxC/BCL Common clock for Rx and Rx Clock, optional Tx. Tx Clock TxC/FSC Frame Sync pulse for Rx Tx Clock in or out. and Tx. TxEN Asserted within the time Asserted slot, optional enable for an whenever Tx is external driver. enabled. Eight-character FIFOs on both the transmit and receive side reduce the possibility of overrun and underrun conditions to a minimum, at data rates up to and beyond E1 (2.048 Mbps).
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SERIAL COMMUNICATION CHANNELS (Continued)
Internal Address/Data Bus
Transmit DMA Controller DMA #x
Receive DMA Controller DMA #y
Transmit FIFO * Ch 0 TXD0 Transmit Shift Register * Ch 0 Transmitter State Machine Transmit Mode Register Ch 0: TMR0 Transmit Control/Status Reg. Ch 0: TCSR0 Transmit Fill Register Ch 0: TFR0 Transmit Interrupt Register Ch 0: TIR0 Transmit TDM Start ^ Ch 0 Transmit TDM Length ^ Ch 0 Transmit Time Slot Assigner Ch 0 Clocking Control Logic
Receive FIFO * Ch 0 Receive Shift Register * Ch 0 Receiver State Machine Receive Mode Register Ch 0: RMR0 Receive Interrupt Register Ch 0: RIR0 Receive TDM Start ^ Ch 0 Receive TDM Length ^ Ch 0 Receive Time Slot Assigner Ch 0 Interrupt Request RXD0
HDLC Control Logic RXC0/ TXC0/ BCL0 FSC0 DMA Select Register Ch 0: DSR0 Counter Access Port Ch 0: CAP0 Baud Rate Generator MSB ^ Ch 0 BUSCLK Baud Rate Generator LSB ^ Ch 0 Global HDLC Vector Register HDLCV
GCI/SCIT Interface
From Tx To Rx
Notes:
*Not Program Accessible
^ Accessed by means of Counter Access Port
Figure 31. HDLC Channel Block Diagram (One of Three Channels Shown)
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Zilog Interface with a Common TDM Module (for example, GCI/SCIT) The interface between an HDLC channel and the GCI/SCIT module includes: A bused line onto which HDLC Transmitters place data in their time slots, as directed by software programming. RxD A bused line from which HDLC Receivers take data in their time slots, as directed by software programming. BCL A common bit clock for HDLC Transmitters and Receivers. Transmitters change data on TxD on falling edges of BCL, and Receivers sample data from RxD on rising edges of BCL. FSC Frame Sync, synchronous to BCL. Transmitters and Receivers measure their time slots independently from the rising edge of this signal. The duration of FSC can be one or more BCL cycles. TxEN An output from each Transmitter to the common TDM module, indicating its time slot, that is, when it is placing data on TxD. TDM Processing When the Transmit (Receive) TDM Length register is nonzero, the Transmitter (Receiver) activates its Time Slot Assigner to clock Tx (Rx) data only within the time slot. If a TDM Start register is non-zero, then after each pulse on Frame Sync, the Time Slot Assigner blocks clocking for the number of bits specified by the TDM Start register. Then, or immediately at Frame Sync if the Start value is zero, it enables clocking for the number of bits specified by the TDM Length register. Thereafter, it again blocks clocking until the next Frame Sync pulse. For example, the Start and Length values for the GCI subchannels are: Channel B1 (64K bps) B1 (56K) B2 (64K) B2 (56K) D IC1 IC2 Start 0 0 8 8 24 32 40 Length 8 7 8 7 2 8 8 TxD
Z80382/Z8L382 High-Performance Data Communications Processors Type/Status Bytes in Transmitter DMA Lists. In HDLC mode, a frame to be transmitted can be contained in one or more DMA buffers. The DMA list entry for the last (or only) buffer of a frame should have its Type/Status byte coded as OReady Buffer, notify at End of BufferO. This makes the Transmitter send the CRC (if enabled) and a closing Flag after the last byte of the buffer. Buffers that do not include the end of a frame should have their Type/Status bytes coded as OReady Buffer, no End of Buffer NotificationO. Two control fields for the Transmitter do not reside in processor-accessible register bits, but can be controlled separately for each frame in Type/Status bytes in the DMA list: 1. How many bits the Transmitter sends from the last byte of the frame. 2. Whether the Transmitter sends its accumulated CRC at the end of the frame. Either of these items can be changed automatically from one frame to the next if the Type/Status byte for the frame is coded as OReady Buffer, with CommandO and the control bits of that byte are set appropriately. In HDLC modes or in Transparent mode with the Underrun Wait bit set to 1, completed Buffer codes in Type/Status bytes in Transmitter DMA lists are stored as Owith StatusO if the Transmitter encountered an Underrun while sending the data in the buffer. In all other cases, Type/Status bytes in Transmitter DMA lists are stored as Ono status.O Type/Status Bytes in Receiver DMA Lists. HDLC receivers do not use the Command nor End of Buffer notification features of the DMA channels. Thus all OReady BufferO codes in Type/Status bytes in Receiver DMA lists are equivalent. A received frame can be contained in one DMA buffer, or can span two or more buffers. The end of a frame always makes the Receiver terminate its current DMA buffer and store frame status in its Type/Status byte. When a buffer is filled with receive data, without the last character of the frame being stored in that buffer, that bufferOs Type/Status byte is stored as OCompleted Buffer (no Status)O. Buffers that include the last character of a frame, and buffers that couldnOt be completed because the Receiver encountered an Overrun condition, are stored as OCompleted Buffer (with Status)O. The least significant five bits of such a Type/Status byte indicate the status of the buffer.
1
Type/Status Bytes in DMA Lists Note: Please refer to the description of Type/Status bytes in the section on the DMA channels in conjunction with this topic.
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SERIAL COMMUNICATION CHANNELS (Continued)
Baud Rate Generator and DPLL If an HDLC channelOs Tx clock is taken from its Baud Rate Generator (BRG), and/or its Rx clock is taken from its DPLL, then the channelOs BRG operates. A BRG counts down from the 16-bit value programmed into its Time Constant LS and MS registers, using the processorOs BUSCLK. Each time the value is zero, the BRG toggles its output to the DPLL, and one clock later it reloads the value from the Time Constant registers. If an HDLC channelOs Rx clocking is taken from its DPLL, software should program the channelOs Time Constant registers with a 16-bit value that corresponds to 16 times the nominal data rate. Conceptually, when the DPLL detects a change on the raw Rx Data (before NRZI decoding), it clears a counter that is incremented at 16X the nominal bit rate. Half a bit time thereafter, it provides an active edge on its Rx clock output. Thereafter, in the absence of further data transitions it provides the Rx clock as the BRG output divided by 16. Per-Channel Registers Each HDLC channel includes the following I/O-mapped registers that can be read and written by the 380C processor:
s s s s s s s s
Transmit Interrupt Register. Controls and provides status of potential interrupting conditions in the transmitter. It also provides the mechanism for clearing conditions which are causing an interrupt. Transmit Fill Register. Holds a character that can be sent between frames in HDLC mode, or in case of an Underrun in Transparent mode. Receive Mode Register. Selects the main operating mode of the Receiver (transparent, HDLC, NRZI HDLC), its I/O configuration (TDM, I/O by means of device pins, and so on), when DMA data transfers are requested, when the receiver begins assembling characters when it is switched from the inactive state to transparent mode, and the type of CRC used in HDLC modes. Receive Interrupt Register. Most of the interrupt requirements for HDLC reception can be handled by enabling Status interrupts in the DMA channel associated with each Receiver. The only Receiver interrupt condition that is not handled by this means is the Idle condition. Idle interrupts are controlled by this register. This register also allows several commands which deal with interrupts and Hunt mode to be issued to the receiver. DMA Select Register. Selects the DMA channels to be used by the receiver and transmitter and enables their operation. Counter Access Port. Allows the 380C to write and read the starting values for various counters in the HDLC channel. These are the Baud Rate Generator time constant, the Transmitter TDM start and length values, and the Receiver TDM start and length values. Global HDLC Vector Register This register provides the base interrupt vector for the HDLC channels and identifies the HDLC device which is causing an interrupt to be issued.
Transmit Mode Register Transmit Control/Status Register Transmit Interrupt Register Transmit Fill Register Receive Mode Register Receive Interrupt Register DMA Select Register Counter Access Port
Transmit Mode Register. Selects the main operating mode of the Transmitter (transparent, HDLC, NRZI HDLC), its I/O configuration (TDM, I/O by means of device pins, and so on), when DMA data transfers are requested, and action to be taken if an underrun occurs. Tx Control/Status Register. Controls the minimum number of bits sent between frames and the minimum number of bits sent after the Transmitter is enabled before the first data character of a frame is sent, what the Transmitter sends between frames, and the type of CRC used. It also provides feedback on the current state of the transmitter.
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Z80382/Z8L382 High-Performance Data Communications Processors Monitor Channels. There are two channels, monitor 0 and monitor 1. Each channel consists of eight bits of data and two associated handshake bits, MR and MX, that control data flow. D Channel. The 16 Kbps D channel (2 bits per frame) provides a connection between the layer two and layer one components.
GCI/SCIT Interface
GCI/SCIT Frame Structure (Terminal Mode) GCI/SCIT includes three sub-frames called channels 0, 1, and 2; each containing 32 bits. This 12-byte frame is repeated at a rate of 8 KHz, which gives an aggregate data rate of 768 Kbits/second. The frame structure is shown in Figure 36 below. B Channels. B1 and B2 are the first two 8-bit time slots after the frame sync pulse. Each B channel provides 64 Kbps of user data to/from the network.
1
FS 8 DD DU B1 B1 8 B2 B2 8 2 4 2 MR-MX MR-MX 8 IC1 IC1 8 IC2 IC2 8 MON1 MON1 6 C/I1 C/I1 2 MR-MX MR-MX 8 8 8 2 4 C/I2 C/I2 GCI Channel 2 2
MON0 D C/I0 MON0 D C/I0 GCI Channel 0
GCI Channel 1
Figure 32. GCI/SCIT Frame Structure
Command/Indicate Channels. Three command/indicate channels, C/I0, C/I1 and C/I2 are provided. Each subframe has one. (C/I2 is the same as TIC, as indicated below.) These channels provide real-time status between devices connected by means of the GCI/SCIT bus. Intercommunication Channels. Two intercommunication subchannels are provided in GCI channel 1. These provide 64 Kbps data paths between user devices. TIC Bus. This is the same as C/I2 and is used for D channel access with some GCI/SCIT devices. It allows multiple layer-2 devices to individually gain access to the D and C/I channels located in the first sub-frame. The data signals on the GCI/SCIT bus are called Data Upstream (DU) and Data Downstream (DD). While each of these is a bus that can be sensed as well as driven in an open-drain (open-collector) fashion by the Z382 and other devices, GCI practice defines certain fields on each line to flow in certain directions.
The Z382 always receives from DD and (when enabled) drives DU in the B2, MON0, D, C/I0, and MX0 fields. The 382 always receives from DU and (when enabled) drives DD in the MR0 bit. Which line is driven and which is received can be selected by software for the IC1, IC2, MON1, and C/I1 fields and the MX1 and MR1 bits, with MR1 always being in the opposite direction from MON1 and MX1. Monitor Channel Operation The monitor channels are full duplex and operate on a pseudo-asynchronous basis, in other words, data transfers take place synchronized to frame sync but the flow is controlled by a handshake procedure using the MX and MR bits. The handshake procedure (flow of events) is shown in Figure 37 below. Idle: The MX and MR pair being held inactive (High) for two or more frames constitutes the channel being idle in that direction. The data received in the monitor channel is invalid and should be O11111111.O
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SERIAL COMMUNICATION CHANNELS (Continued)
Start of Transmission: The first byte of data is placed on the bus and MX is activated (Low). MX remains active, and the data is repeated until an inactive-to-active transition of MR is received, indicating that the data has been captured by the receiver. Subsequent Transmissions: The second and subsequent bytes are placed on the bus after the inactive to active transition of MR. At the time that the second byte is transmitted, MX is returned inactive for one frame time only; the data is valid in the same frame. In the following frame, MX returns active again and the same byte is transmitted. Data is repeated in subsequent frames and MX remains active until acknowledgment is detected (MR transition from inactive to active). Maximum Speed Case: The transmitter is capable of minimizing the delay between bytes to achieve higher data throughput than is provided by the general case described above. The first and second bytes are transmitted normally, However, starting with the third byte, the transmitter will deactivate MX and transmit new data one frame time after MR is deactivated. In this way, the transmitter is anticipating that MR will be reactivated, which it will do one frame time after it is deactivated, unless an abort is signalled by the receiver. End of Message (EOM): The transmitter sends an EOM, normally after the last byte of data has been transmitted, by not reactivating MX after deactivating it in response to MR going inactive. Reception: At the time the receiver sees the first byte, indicated by the inactive-to-active transition of MX, MR is by definition inactive. In response to the activation of MX, the data is read off the bus and MR is activated. MR remains active until the next byte is received or an end of message is detected. Subsequent data is received from the bus on each falling edge of MX, and a monitor channel receive data available interrupt is generated. Note that the data may actually be valid at the time that MX went inactive, one frame time prior to going active. MR is deactivated after the data is read and reactivated one frame time later. The transmitter will detect MR going inactive and anticipate its reactivation one frame later. The reception of data is terminated by the reception of an end of message indication. Abort: The abort is a signal from the receiver to the transmitter indicating that the data has been missed. It is not an abort in the classical sense, which is an indication that the current message should be ignored. The receiver indicates an abort by holding MR inactive for two or more frames in response to MX going inactive. Flow Control: The receiver can hold off the transmitter by keeping MR active until the receiver is ready for the next byte. The transmitter will not start the next transmission cycle until MR goes inactive.
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MX /MX MR Receiver /MR
125 msec ACK First Byte New Byte
Z80382/Z8L382 High-Performance Data Communications Processors
Transmitter
EOM Last Byte
1
ACK
ACK
a. General Case MX /MX MR Receiver /MR b. Abort Request from the Receiver Transmitter MX /MX MR Receiver /MR
ACK First Byte ACK 2nd Byte ACK 3rd Byte First Byte 2nd Byte 3rd Byte EOM Abort Request New Byte
Transmitter
EOM
c. Maximum Speed Case
Figure 33. Monitor Handshake Timing
Monitor Channel Handling Before transmitting data on a monitor channel, the processor should look at the Monitor 0 or 1 active status bit in GCI Status Register 2 to verify that the channel is inactive. The processor can then write the data to the Monitor Transmit Data Register. This will enable the GCI hardware to proceed with the transmission of this data according to the monitor channel protocol. On receiving an acknowledge from the receiver, the transmit data request bit in GCI Status Register 1 is set, indicating that the monitor channel is ready to transmit another byte of data. When the last byte has been acknowledged by the receiver, the processor can set the EOM request bit in the GCI Control Register and the monitor channel will then send an end of message signal. On receiving the monitor data, the receiver will write this data to the monitor receive register and set the appropriate status bit. This will generate a monitor receive data available interrupt, instructing the processor to read this data. Succeeding bytes of data are received in accordance to the monitor channel protocol and the processor is inDS97Z382000
formed by means of the monitor receive data available interrupt. The processor can force the receiver to ask for an abort by setting the abort request bit. The receiver will ask for an abort in transmission by sending an inactive MR for two consecutive frames. The abort transmission is indicated in the status bit by the transmitter. C/I Channel Operation Data on C/I0 and C/I1 is transmitted continuously in each frame until new data is to be sent. A change in C/I channel data is considered valid if it has been received in two consecutive frames. GCI/SCIT Bus Activation and Deactivation Deactivation, Upstream to Downstream. The upstream (clock master) unit can initiate deactivation by issuing a series of software handshakes by means of the C/I0 channel. Having done so, the upstream unit waits for a deactivation indication from all downstream (clock slave) units. Once this is received, a deactivation confirmation is issued, followed by stopping the clocks (forcing them Low) and placing the data pin in a high impedance state. After the clocks are stopped, the input pin is monitored for the presence of 59
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SERIAL COMMUNICATION CHANNELS (Continued)
a timing request from the downstream unit (the pin being pulled Low). Deactivation Request, Downstream to Upstream: Deactivation is normally initiated by the upstream device as described above. When the downstream device receives the deactivation request over the C/I0 channel, it must respond by sending the deactivation indication. Activation Request, Downstream to Upstream: The downstream device can request that the clocks be started by pulling its data output line low. Once the clocks are started, the downstream unit requests activation by sending an activation request over the C/I0 channel. Activation, Upstream to Downstream: The upstream unit activates the bus by starting the clocks and following the C/I0 channel-based activation procedure. B1, B2, D, IC1, IC2 Channel Data: Rx data and the bit clock are supplied to the HDLC cells, and Tx data is taken from the HDLC cells. Each HDLC Transmitter and Receiver includes a Time Slot Assigner which can be programmed for any of the subchannels shown above. Note: The HDLC Transmitters signal when they are sending data. This signalling should not conflict with transmission by the GCI/SCIT module, but if it should, the HDLC modules have priority. GCI/SCIT Registers The GCI/SCIT interface includes the following I/O-mapped registers that can be read and written by the 380C processor:
s s s s s s s s s s s s
Monitor 0, Monitor 1, C/I0 - C/I2 and C/I1Transmit Data Registers. Data written into these registers is transmitted on the respective channels in accordance with the GCI/SCIT protocol. Monitor 0, Monitor 1, C/I0 - C/I2 and C/I1Receive Data Registers. Data received from the respective channels in accordance with the GCI/SCIT protocol is written into these registers. GCI Status Register 1. Provides receive and transmit status conditions for Monitor 0 and 1 channels. GCI Status Register 2. Provides additional status conditions for the GCI/SCIT module. GCI Interrupt Enable Register. Provides control of interrupts from the various channels in the GCI/SCIT module.
Clocked Serial I/O (CSIO)
The Z382 includes a synchronous serial I/O port (CSI/O) which provides half-duplex transmission/reception of fixed 8-bit data at a speed of up to BUSCLK/20 bits/second. The CSI/O is ideal for implementing a multiprocessor communication link between multiple Z80xxx family members. A block diagram of the CSI/O is illustrated below.
Internal Address/Data Bus
TXS RXS
GCI Control Register Monitor 0 Transmit Data Register Monitor 0 Receive Data Register Monitor 1 Transmit Data Register Monitor 1 Receive Data Register C/I0 - C/I2 Transmit Data Register C/I0 - C/I2 Receive Data Register C/I1 Transmit Data Register C/I1 Receive Data Register GCI Status Register 1 GCI Status Register 2 GCI Interrupt Enable Register
CSI/O Transmit/Receive Data Register: TRDR CSI/O Control Register: CNTR
Interrupt Request
Baud Rate Generator
CKS f
Figure 34. CSI/O Block Diagram Note that the three pins associated with the CSI/O are multiplexed with other signals and must be configured for CSI/O operation in order to use the CSI/O as described in this section.
GCI Control Register. Controls the Monitor 1 and C/I1 Direction, the clock activation request to the master, enabling/disabling Monitors 1 and 0, and Monitors 1 and 0 EOM and Abort requests.
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Zilog CSI/O Registers The CSI/O channel includes the following I/O-mapped registers that can be read and written by the 380C processor:
s s
Z80382/Z8L382 High-Performance Data Communications Processors CSI/O Tx/Rx Data Register. TRDR is used for both CSI/O transmission and reception in a half-duplex protocol. Thus, the system design must ensure that transmit and receive operations do not occur simultaneously. For example, if a CSI/O transmission is attempted while the CSI/O is receiving data, a CSI/O will not work. Also, the TRDR is not buffered. Thus, attempting to perform a CSI/O transmit while the previous transmit data is still being shifted out causes the shift data to be immediately updated, corrupting the transmit operation in progress. Similarly, reading TRDR while a transmit or receive is in progress must be avoided.
Transmit/Receive Data Register CSI/O Control Register
1
CSI/O Control Register. CNTR is used to monitor CSI/O status, enable and disable the CSI/O, enable and disable interrupt generation, and select the data clock speed and source.
COUNTERS, TIMERS AND OTHER MISCELLANEOUS LOGIC Programmable Reload Timer
Internal Address/Data Bus Interrupt Request
Timer Reload Reg. High Ch 0: RLDR0H Timer Data Reg. High Ch 0: TMDR0H Timer Reload Reg. Low Ch 0: RLDR0L Timer Data Reg. Low Ch 0: TMDR0L Timer Control Register TCR Timer Prescale Register TPR Timer Reload Reg. Low Ch 1: RLDR1L Timer Data Reg. Low Ch 1: TMDR1L Timer Reload Reg. High Ch 1: RLDR1H Timer Data Reg. High Ch 1: TMDR1H
BUSCLK
TOUT
Figure 35. Programmable Reload Timer Block Diagram
The Z382 contains two separate 16-bit Programmable Reload Timers (PRT). Each PRT channel contains a 16-bit down counter and a 16-bit reload register. The down counter can be directly read and written and a down counter overflow interrupt can be programmably enabled or disabled. Also, PRT1 can be programmed to set the TOUT pin High or Low or to toggle it when the channel counts down to zero. Thus, PRT1 can perform programmable output waveform generation. The two channels share a common status/control register and a Timer Prescale Register which allows the time base for each PRT to be programmed as the Z382 BUSCLK divided by a power of two. PRT Common Registers The PRTs share two I/O-mapped registers that can be read and written by the 380C processor:
s s
Timer Prescale Register. Selects the rates at which each PRT is clocked, providing for BUSCLK divisors ranging from 1 to 32,768. Timer Control Register. The TCR monitors the status of both PRT channels and controls enabling and disabling of down counting and interrupts. It also controls the effect of PRT1 on the TOUT output pin. PRT Per Channel Registers The I/O-mapped per-channel registers in each PRT are:
s s
Timer Data Registers High/Low Timer Reload Registers High/Low
Timer Prescale Register Timer Control Register
Timer Data Registers. Each PRT has a 16-bit Timer Data Register (TMDR). TMDR is decremented once every clock output from the timer prescaler, which divides the BUSCLK signal of the Z382 by a value which is specified, independently for PRT1 and PRT0, in the TPR. When TMDR
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COUNTERS, TIMERS AND OTHER MISCELLANEOUS LOGIC (Continued)
counts down to 0, it is automatically reloaded with the value contained in its Timer Reload Register (RLDR). Timer Reload Registers. Each PRT has a 16-bit Timer Reload Register (RLDR) When a PRT channelOs TMDR counts down to 0, it is automatically reloaded with the contents of its RLDR. Figure 40 below illustrates the operation of the PRT.
Timer Data Register Write (0004H) Reset Timer Data Register FFFFH 0004H
0f
f
f
f
f
f
f
f
0003H
0002H
0001H 0000H
0003H
0002H
0001H
0000H
0003H
Timer Reload Register Write (0003H) Timer Reload Register
Reload
Reload
FFFFH
0003H Write O1O to TDE
Timer Downcount Enable Timer Interrupt Flag Timer Data Register Read Note: f is BUSCLK divided by the value specified in TPR. Timer Control Register Read
Figure 36. PRT Operation
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Z80382/Z8L382 High-Performance Data Communications Processors Because of pin multiplexing, ports A and D are available only in non-Host applications, and the registers for Ports A and D are used by the Mimic feature in Host applications. Additional information on the multiplexing of the Port pins is provided in the Device Configuration section of this document. Each port contains two registers accessible in the 380COs I/O address space:
s s
Watch-Dog Timer
A Watch-Dog Timer (WDT) with programmable timeout intervals prevents code runaway and possible resulting system damage. The /RESET input can be forced as an output upon the terminal count of the WDT, allowing external peripherals to be reset along with the Z382. Unlike other on-chip functions, the WDT is enabled at Reset and must be disabled by software if its function is not desired. If software does not disable the WDT, it must periodically clear the WDT in order to avoid a hardware reset of the entire chip. The block diagram of the WDT is shown below (Figure 41).
1
Port Direction Register Port Data Register
Internal Address/Data Bus
Bit 3 in the System Configuration Register controls whether only the lowest eight address lines are decoded, allowing the port data and direction registers to be accessed in any page of I/O space (as on the Z18x family), or whether access is limited to a single page (A[15-8] = 0). Port Direction Register The Direction Register determines which pins of the port are inputs and which are outputs. In Host applications, the Port A and D Direction Registers are used to buffer data between the HostOs HD7-0 lines and the Z382 for the OHost DMA MailboxO and OHost I/O MailboxO functions.
WDT Out
WDT Master Register WDTMR WDT Command Register WDTCR
f
Timeout Generator
Figure 37. WDT Block Diagram WDT Registers The CSI/O channel includes the following I/O-mapped registers that can be read and written by the 380C processor:
s s
Port Data Register When the 380C writes to the Data Register of an available port, the data is stored in this register. Any pins that are identified as output in the corresponding Port Direction Register are then driven with the new data. When the 380C reads the Data Register of an available port, the data on the external pins is returned. In Host applications, the Port A and D Data Registers are used for implementation of the OHost I/O MailboxO feature.
WDT Master Register WDT Command Register
I/O Chip Selects
Two I/O chip selects, /IOCS1 and /IOCS2, are provided to support I/O access of external peripherals. These chip selects are asserted Low when some number of the 16 LSBs of the current 380C address match the values programmed in the IOCS registers.The number of bits actually compared is specified in one of the registers, providing I/O decode sizes ranging from 8 to 512 bytes. Address comparisons take place during both memory and I/O cycles. The I/O Chip Selects are not asserted in INTACK cycles.
Watch-Dog Timer Master Register. This register controls enabling/disabling of the WDT, its period, and whether the /RESET pin is driven to reset external devices when the WDT times out. WDT Command Register. The WDT decodes two values written to this register.One value is used to reset the WDT to a count of zero, the second value must be written to this register in order to disable the WDT.
Parallel Ports
The Z382 has four 8-bit bidirectional ports called ports A through D. A Direction Register associated with each port allows each bit of the port to be programmable as an input or an output.
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COUNTERS, TIMERS AND OTHER MISCELLANEOUS LOGIC (Continued)
I/O Chip Select Registers The following I/O-mapped registers are associated with the I/O chip selects and can be read and written by the 380C processor:
s s
lect, and specifies the number of T1 wait states for the RAM chip select. Memory Mode Register 2. Enables the RAM chip select, specifies 8- or 16-bit memory accesses for the RAM and ROM chip selects independently, and specifies the number of T2 and T3 wait states for the RAM chip select.
I/OCS1 High and Low Address Registers I/OCS2 High and Low Address Registers
I/O Chip Select 1/2 High and Low Address Registers. Specify the base address and the I/O block size for I/O Chip Selects 1 and 2.
Interrupt Logic
The Z382Os interrupt structure provides compatibility with the existing Z80 and Z180 with the following exception: the undefined Opcode trapOs occurrence is with respect to the Z380 instruction set, and its response is improved (versus the Z180) to make trap handling easier. The Z380 offers additional features to enhance flexibility in system design. Of the five external interrupt inputs provided, /NMI is a nonmaskable interrupt. The remaining inputs, /INT3-0, are asynchronous maskable interrupt requests. In an Interrupt Acknowledge transaction, address outputs A23-4 are driven to a logic High. One output among A3-0 is driven Low to indicate the maskable interrupt request being acknowledged. For example, when /INT0 is being acknowledged, A3-1 are High and A0 is Low. Interrupt modes 0 through 3 are supported for maskable interrupt request /INT0, which can be driven by external and on-chip sources. Modes 0, 1 and 2 have the same schemes as those in the Z80 and Z180. Mode 3 is similar to mode 2, except that 16-bit interrupt vectors are expected from the I/O devices. Note that 8-bit and 16-bit I/O devices can be intermixed in this mode by having external pull up resistors at the data bus signals D15-8, for example. The external maskable interrupt requests /INT3-1, as well as the less complex on-chip peripherals (PRTs, ASCIs, and CSI/O) are handled in an assigned interrupt vectors mode. INT3-1 can be used as Low or High active levelsensitive inputs, or as falling or rising edge-triggered inputs. The Z382 can operate in either the Native or Extended Mode. In Native Mode, PUSHing and POPing of the stack to save and retrieve interrupted PC values in interrupt handling are done in 16-bit sizes, and the stack pointer rolls over at the 64-KB boundary. In Extended Mode, the PC PUSHes and POPs are done in 32-bit sizes, and the stack pointer rolls over at the 4-GB memory space boundary. The Z382 provides an Interrupt Register Extension, whose contents are always output as the address bus signals A23-16 when fetching the starting addresses of service routines from memory in interrupt modes 2 and 3 and the assigned vectors mode. In Native Mode, such fetches are automatically done in 16-bit sizes and in Extended Mode, DS97Z382000
RAM AND ROM Chip Selects
Three memory chip select outputs are provided: /ROMCS, /RAMCSL, and /RAMCSH. They support both 8- and 16bit memories, and are asserted for a selected address range (4 KB to 8 MB) during both memory and I/O cycles. Unlike Chip Select and /MSIZE signalling, wait state generation can be specified which occurs only during memory cycles. For the selected ROM and/or RAM range, the /MSIZE pin can be programmed to be forced Low in an open-drain fashion when the address is in the programmed range, thus forcing 8-bit accesses in one or both ranges. When /MSIZE is forced for 8-bit RAM in this way, /RAMCSL is asserted for all cycles in the selected address range, and the /RAMCSH pin assumes its alternate use as port pin PC7. When /MSIZE is not forced for 8-bit RAM, /RAMCSL is qualified by /BLEN, and /RAMCSH acts as a chip select output pin and is qualified by /BHEN. RAM and ROM Chip Select Registers The following I/O-mapped registers are associated with the RAM and ROM chip selects and can be read and written by the 380C processor:
s s s s
RAM Address High and Low Registers ROM Address High and Low Registers Memory Mode Register 1 Memory Mode Register 2
RAM Address High and Low Registers: Specify which bits of the address bus are used in the address comparison and thus, implicitly, the memory block size. This can range from 4 KB to 8 MB. ROM Address High and Low Registers: Specify which bits of the address bus are used in the address comparison and thus, implicitly, the memory block size. This can range from 4 KB to 8 MB. Memory Mode Register 1. Enables the ROM chip select, specifies the number of wait states for the ROM chip se-
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Zilog in 32-bit sizes. These starting addresses should be evenaligned in memory locations. That is, their least significant bytes should have addresses with A0 = 0. Interrupt Priority Ranking The Z382 assigns a fixed priority ranking to handle its major categories of interrupt sources, as follows: Priority Highest Interrupt Sources Trap (undened opcode) /NMI /INT0 (includes DMAs, Mimic, HDLC controllers) /INT1 /INT2 GCI/SCIT PRT0 PRT1 CSI/O ASCI0 ASCI1 Plug and Play ISA or PCMCIA I/O Mailbox /INT3
Z80382/Z8L382 High-Performance Data Communications Processors quest being recognized as A8-0. The assigned vectors are as follows: Assigned Interrupt Vector 00H 04H 08H 0CH 10H 14H 18H 1CH 20H 24H 28H 2CH
Interrupt Source /INT1 /INT2 Reserved GCI/SCIT PRT0 PRT1 CSI/O ASCI0 ASCI1 Plug and Play or PCMCIA I/O Mailbox /INT3
1
Lowest
INT0 Peripherals Those on-chip peripherals capable of generating their own interrupt vectors, including the Mimic, DMAs, and HDLC controllers, have their interrupt requests logically OROed with the external /INT0 pin to produce the INT0 signal presented to the 380C processor. These interrupt sources are consecutive in the INT0 daisy-chain, but their relative priority can be programmed in the System Configuration Register. Their priority relative to external INT0 sources is controlled by how the Z382Os IEI and IEO pins are connected. Assigned Interrupt Vectors Mode (INT1-3, PRTs, CSI/O, ASCIs) When the Z382 recognizes /INT1-3, or a request from an on-chip peripheral that cannot supply an interrupt vector (a PRT, CSI/O, or ASCI), it generates an Interrupt Acknowledge transaction which is different from that for /INT0. This Interrupt Acknowledge transaction has /IORQ active for external monitoring purposes, but /M1, /IORD, and /IOWR inactive so as not to stimulate external devices. The interrupted PC value is PUSHed onto the stack. IEF1 and IEF2 are cleared, disabling further maskable interrupt requests. The starting address of an interrupt service routine is fetched from a table entry and loaded into the PC to resume execution. The address of the table entry is composed of the I Extend contents as A31-16, the seven Vector Base bits of the Assigned Vectors Base Register as A15-9 and an assigned interrupt vector specific to the re-
Trap Interrupt The 380C generates a trap when an undefined opcode is encountered. The trap is enabled immediately after reset, and it is not maskable. This feature can be used to increase software reliability or to implement extended instructions. An undefined opcode can be fetched from the instruction stream, or it can be returned as a vector in an interrupt acknowledge transaction in interrupt mode 0. Nonmaskable Interrupt The nonmaskable interrupt input /NMI is edge sensitive, with the 380C internally latching the occurrence of its falling edge. When the latched version of /NMI is recognized, the interrupted PC (Program Counter) value is pushed onto the stack, certain status flag manipulations are performed, and the 380C commences to fetch and execute instructions from address 00000066H. RETI Instruction The original Z80 family I/O devices (PIO, SIO, CTC) are designed to monitor the Return from Interrupt Opcodes in the instruction stream, signifying the end of the current interrupt service routine. On the Z382, the M1 signal is active during all instruction fetch transactions. Since the Z382 may not execute an RETI that it fetches, and because it supports a 16-bit data bus, only half of which is visible to an 8-bit peripheral, the Z382 does not support RETI decoding by the PIO, SIO, and CTC.
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COUNTERS, TIMERS AND OTHER MISCELLANEOUS LOGIC (Continued)
Interrupt Registers The following I/O-mapped registers are associated with interrupts and can be read and written by the 380C processor:
s s s s
Interrupt Enable Register Assigned Vectors Base Register INT3-1 Control Register Trap and Break Register
I/O Bus Control The Z382 is designed to interface easily with external I/O devices that can be of either the Z80 or Z8500 product family by supplying four I/O bus control signals: /M1, /IORQ, /IORD, and /IOWR. In addition, the Z382 supplies an IOCLK that is a divided down version of its BUSCLK. Programmable wait states can be inserted in the various I/O transactions. DRAM Refresh The Z382 is capable of providing refresh transactions to dynamic memories that have internal refresh address counters. A user can select how often refresh requests should be made to the Z80Os External Interface Logic, as well as the burst size (number of refresh transactions) for each request iteration. The External Interface Logic grants these requests by performing refresh transactions with CAS-before-RAS timing on the /TREFR, /TREFA and /TREFC bus control signals. In these transactions, /BHEN, /BLEN and the user specified chip select signal(s) are driven active to facilitate refreshing all the DRAM modules at the same time. A user can also specify the T1, T2 and T3 waits to be inserted. Note: The Z382 cannot provide refresh transactions when it relinquishes the system bus, with its /BREQ input active. In that situation, the number of missed refresh requests are accumulated in a counter, and when the Z382 regains the system bus, the missed refresh transactions will be performed. Low Power Standby Mode The Z382 provides an optional standby mode to minimize power consumption during system idle time. If this option is enabled, executing the Sleep instruction stops the Z382Os oscillator if it is in use, and in any case stops clocking internal to the Z382 (except to PRT0 if it is enabled) and at the BUSCLK and IOCLK outputs. The /STNBY and /HALT signals go Low to indicate that the Z382 is entering the standby mode. All Z382 operations are suspended, the bus control signals are driven inactive and the address bus is driven High. Standby mode can be exited by asserting any of the /RESET, /NMI, /INT3-/INT0 (if enabled), or optionally, /BREQ inputs. If standby mode is not enabled, the Sleep instruction does not stop the Z382Os oscillator if it is in use, but blocks clocking from internal modules, except PRT0 if it is enabled. In this case, /STNBY (but not /HALT) goes Low to indicate the Z382Os status.
Interrupt Enable Register. Provides the current status of the /INT3-0 pins and controls whether /INT3, /INT2, /INT1, and /INT0 are enabled or disabled. Note that these flags are also affected by enable and disable interrupt instructions (DI (n) and EI (n)). Assigned Vectors Base Register. The Interrupt Register Extension, Iz, together with the contents in bits 1-7 of this register, define the base address of the assigned interrupt vectors table in memory space. INT3-1 Control Register. Controls when and how the Z382 recognizes an interrupt on the corresponding pins (High or Low Level sensitive, Falling or Rising Edge Triggered) and provides the means for clearing edge triggered interrupt requests if such are specified for /INT3-1. Trap and Break Register. Two bits of this register provide status on traps. One bit is set if an undefined opcode is fetched in the instruction stream. A second bit is set if an undefined opcode is returned as a vector in an interrupt acknowledge transaction in mode 0.
Z380-Compatible Peripheral Functions
The Z382 incorporates a number of Z80380 compatible functions. The Z382Os I/O bus can be programmed to run at a slower rate than its memory bus. In addition, a heartbeat transaction can be generated on the I/O bus that emulates a Z80 instruction fetch cycle. Such cycles are needed for a particular Z80 family I/O device to perform its interrupt functions. Finally, a DRAM refresh function is incorporated, with programmable refresh transaction burst size.
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Zilog Peripheral Function Control Registers The functions described above are controlled by a number of I/O mapped on-chip registers:
s s s s s
Z80382/Z8L382 High-Performance Data Communications Processors Refresh Register 2. Enables the refresh function and defines the number of refresh transactions per refresh request made to the Z382Os External Interface Logic. Refresh Wait Register. Defines the number of T1, T2 and T3 wait states to be inserted in refresh transactions. Standby Mode Control Register. Enables the Z382 to go into low-power standby mode when the Sleep instruction is executed, allows asserting /BREQ to exit the mode, and specifies the approximate running duration of a warm-up counter that provides a delay before the Z382 resumes its clocking and operations, from the time an interrupt or bus request (if so enabled) is asserted to exit standby mode.
Clock Control Register I/O Waits Register Refresh Registers 0, 1 and 2 Refresh Wait Register Standby Mode Control Register
1
Clock Control Register. Controls how BUSCLK is derived from the input clock (CLKI, CLKI/2 or CLKI x 2), provides a means of disabling CLKO to save power and reduce noise if an external clock is used, and controls the I/O Clock Rate (BUSCLK/8 to BUSCLK). I/O Waits Register. Allows for up to seven wait states to be inserted in external I/O read and write transactions, and at the latter portions of interrupt transactions to capture interrupt vectors. Also allows for up to seven wait states to be inserted at the early portions of interrupt acknowledge transactions, for the interrupt daisy chain through on-chip and possibly external I/O devices to settle. Refresh Register 0. Defines the interval between refresh requests to the Z382Os External Interface Logic. Refresh Register 1. Provides the Missed Requests Count. This count increments by one when a refresh request is made and decrements by one when the Z382Os External Interface Logic completes each burst of refresh transactions. A user can read the count status, and if necessary, take corrective actions such as adjusting the burst size.
Device Configuration
In addition to the configuration options provided in the registers associated with each of the major functional blocks in the Z382, there are two registers which control the overall device configuration:
s s
System Configuration Register Pin Multiplexing Register
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COUNTERS, TIMERS AND OTHER MISCELLANEOUS LOGIC (Continued)
System Configuration Register The System Configuration Register controls the major modes of the Z382:
s
In addition to the control above, certain pins are multiplexed automatically based on the state of register bits in their associated functions. Pin Multiplexing Register The Pin Multiplexing Register controls smaller-scale pin multiplexing issues than those handled in the System Configuration Register.
s
How pins 60 - 92 are used: connected to the ISA bus of a host PC; connected to the PCMCIA bus of a host PC; used for the ASCIs, CSI/O, and ports A and D, except that the full-time outputs among these signals (TXA0, TXA1, RTS0, TxS) are disabled; used for the ASCIs, CSI/O, and ports A and D, including the TXA0, TXA1, RTS0, and TxS outputs. How pins 110-112 are used: /DCD0, /CTS0, /CTS1 ASCI control signals; TREFA, TREFC, and TREFR DRAM control signals. D15 - 0 use during reads from on-chip I/O devices: the D15-0 pins are driven as outputs from the Z382; the pins are left tri-stated to reduce power consumption, noise, and EMI/RFI to some extent. I/O address decoding of the Mimic and Parallel Ports: A15-8 must be zero to access these features; the address decoding for these ports disregards address lines above A7, so that these devices are replicated in each 256-byte OpageO of I/O space as on the Z80182, 187, and 189. The relative interrupt priority of the Mimic, HDLC channels, and DMA channels on the INT0 daisy chain.
Whether the pins normally used for HDLC 0 are used for ASCI0 signals instead. Whether the pins normally used for HDLC 1 are used for ASCI1 signals instead. The functions of pins 47, 48, 49, 53, 56, 57, 58 and 109.
s
s
s
Programable Low Noise Drivers
To help reduce noise generated by the output switching of the Z382, selected outputs can be placed in a reduced drive configuration. When a pin is placed in low noise mode, its drive is reduced to 1/3 of its normal output drive current. This decreases the slew rate of the driver, which reduces current spikes induced onto the power bussing of the Z382. The Output Drive Control Register provides this function for a number of groups of Z382 output or I/O pins.
s
s
s
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Z382 I/O REGISTER MAPS Z80380-COMPATIBLE REGISTERS
Register Name Assigned Vectors Base Register Trap and Break Register I/O Waits Register Refresh Waits Register Clock Control Register Refresh Register 0 Refresh Register 1 Refresh Register 2 Standby Mode Control Register Interrupt Enable Register Chip Version ID Register Z382 Address %0018 %0019 %001E %001F %0021 %0023 %0024 %0025 %0026 %0027 %0020 Z380 Address %0018 %0019 %000E %000F %0011 %0013 %0014 %0015 %0016 %0017 %00FF Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO
1
Z80382 ASCI, PRT, CSIO, WDT REGISTERS
Register Name ASCI Control Register A Ch 0 ASCI Control Register A Ch 1 ASCI Control Register B Ch 0 ASCI Control Register B Ch 1 ASCI Status Register Ch 0 ASCI Status Register Ch 1 ASCI TX Data Register Ch 0 ASCI TX Data Register Ch 1 ASCI RX Data Register Ch 0 ASCI RX Data Register Ch 1 CSI/O Control Register CSI/O Tx/Rx Data Register Timer Data Register Ch OL Timer Data Register Ch OH Reload Register Ch OL Reload Register Ch OH Timer Control Register Timer Prescale Register ASCI0 Extension Control Register ASCI1 Extension Control Register I/O Address %0000 %0001 %0002 %0003 %0004 %0005 %0006 %0007 %0008 %0009 %000A %000B %000C %000D %000E %000F %0010 %0011 %0012 %0013 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
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Z80382 ASCI, PRT, CSIO, WDT REGISTERS (Continued)
Register Name Timer Data Register Ch 1L Timer Data Register Ch 1H Reload Register Ch 1L Reload Register Ch 1H ASCI0 Time Constant Low ASCI0 Time Constant High ASCI1 Time Constant Low ASCI1 Time Constant High WDT Master Register WDT Command Register I/O Address %0014 %0015 %0016 %0017 %001A %001B %001C %001D %0028 %0029 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W WO
PORT AND NEW Z80382 REGISTERS
Register Name IOCS1 Low Register IOCS1 High Register IOCS2 Low Register IOCS2 High Register RAM Low Register RAM High Register ROM Low Register ROM High Register Memory Mode Register 1 Memory Mode Register 2 System Conguration Register Pin Multiplexing Register ASCI0 DMA Control Register ASCI1 DMA Control Register Output Drive Control Register INT3-1 Control Register Port A Data Register Port A Data Direction Register Port B Data Register Port B Data Direction Register Port C Data Register Port C Data Direction Register Port D Data Register Port D Data Direction Register I/O Address %002A %002B %002C %002D %002E %002F %0030 %0031 %0032 %00D3 %0036 %0037 %0038 %0039 %003A %003B %00EE %00ED %00E5 %00E4 %00DE %00DD %00E8 %00E7 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
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DMA REGISTERS
Register Name DMA Control Register DMA Vector Register DMA0 List Address Register Low* DMA0 List Address Register Middle* DMA0 List Address Register High* DMA0 Control/Status Register DMA1 List Address Register Low* DMA1 List Address Register Middle* DMA1 List Address Register High* DMA1 Control/Status Register DMA2 List Address Register Low* DMA2 List Address Register Middle* DMA2 List Address Register High* DMA2 Control/Status Register DMA3 List Address Register Low* DMA3 List Address Register Middle* DMA3 List Address Register High* DMA3 Control/Status Register DMA4 List Address Register Low* DMA4 List Address Register Middle* DMA4 List Address Register High* DMA4 Control/Status Register DMA5 List Address Register Low* DMA5 List Address Register Middle* DMA5 List Address Register High* DMA5 Control/Status Register DMA6 List Address Register Low* DMA6 List Address Register Middle* DMA6 List Address Register High* DMA6 Control/Status Register DMA7 List Address Register Low* DMA7 List Address Register Middle* DMA7 List Address Register High* DMA7 Control/Status Register I/O Address %003E %003F %0040 %0041 %0042 %0043 %0044 %0045 %0046 %0047 %0048 %0049 %004A %004B %004C %004D %004E %004F %0050 %0051 %0052 %0053 %0054 %0055 %0056 %0057 %0058 %0059 %005A %005B %005C %005D %005E %005F Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
1
Note: * These addresses can be selected to access the Buffer Address and Buffer Length register for testing.
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HDLC REGISTERS
Register Name HDLC Vector Register HDLC0 Transmit Mode Register HDLC0 Transmit Interrupt Register HDLC0 Transmit Control/Status HDLC0 Transmit Fill Register HDLC0 Receive Mode Register HDLC0 Receive Interrupt Register HDLC0 Counter Access Port HDLC0 DMA Select Register HDLC1 Transmit Mode Register HDLC1 Transmit Interrupt Register HDLC1 Transmit Control/Status Register HDLC1 Transmit Fill Register HDLC1 Receive Mode Register HDLC1 Receive Interrupt Register HDLC1 Counter Access Port HDLC1 DMA Select Register HDLC2 Transmit Mode Register HDLC2 Transmit Interrupt Register HDLC2 Transmit Control/Status Register HDLC2 Transmit Fill Register HDLC2 Receive Mode Register HDLC2 Receive Interrupt Register HDLC2 Counter Access Port HDLC2 DMA Select Register I/O Address %003D %0060 %0061 %0062 %0063 %0064 %0065 %0066 %0067 &0068 %0069 %006A %006B %006C %006D %006E %006F %0070 %0071 %0072 %0073 %0074 %0075 %0076 %0077 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
GCI/SCIT REGISTERS
Register Name GCI Control Register GCI Status Register 1 GCI Status Register 2 GCI Interrupt Enable Register MON0 Transmit Data Register MON0 Receive Data Register MON1 Transmit Data Register MON1 Receive Data Register C/I0 Transmit Data Register C/I0 Receive Data Register C/I1 Transmit Data Register C/I1 Receive Data Register I/O Address %00C0 %00C1 %00C2 %00C3 %00C4 %00C4 %00C5 %00C5 %00C6 %00C6 %00C7 %00C7 Access R/W RO R/W R/W WO RO WO RO WO RO WO RO
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Z80382 MIMIC REGISTERS
Register Name MMC Mimic Master Control Register IUS/IP Interrupt Pending IE Interrupt Enable IVEC Interrupt Vector RTCR Receive Time Constant TTCR Transmit Time Constant DLM Divisor Latch (MSByte) DLL Divisor Latch (LSByte) SCR Scratch Register MSR Modem Status Register LSR Line Status Register MCR Modem Control Register LCR Line Control Register IER Interrupt Enable Register RBR Receiver Buffer Register THR Transmitter Holding Register Mimic DMA Control Register FSCR FIFO Status and Control Register TTTC Transmitter Timeout Time Constant Register RTTC Receiver Timeout Time Constant Register IIR Interrupt Identication Register FCR FIFO Control Register Mimic Modication Register Host DMA Control Register Mimic BRG High Constant Register Mimic BRG Low Constant Register IOBRG Register Host I/O Status Register Host DMA Mailbox Control Register Host DMA Transmit Register 1 Host DMA Receive Register 1 Host DMA Transmit Register 0 Host DMA Receive Register 0 I/O Address %00FF %00FE %00FD %00FC %00FB %00FA %00F9 %00F8 %00F7 %00F6 %00F5 %00F4 %00F3 %00F1 %00F0 %00F0 %00EF %00EC %00EB %00EA None %00E9 %00E9 %00e6 %00E1 %00E0 %00D6 %00D5 %00D2 %00D1 %00D1 %00D0 %00D0 Access R/W R/Wb7 R/W R/W R/W R/W RO RO RO R/Wb7-4 R/Wb6432 RO RO RO WO RO R/W R/W7-4 R/W R/W None RO WO R/W R/W R/W R/W W bit1/R R/W RO WO RO WO Host None None None None None None %01, DLAB=1, R/W %00, DLAB=1, R/W %07, R/W %06, RO %05, RO %04, R/W %03, R/W %01, DLAB=0, R/W %00, DLAB=0, RO %00, DLAB=0, WO None None None None %02, RO %02, RO None None
1
Base + 10b R None /HDAK1, /HWR lo (Note) /HDAK1, /HRD lo /HDAK0, /HWR lo /HDAK0, /HRD lo
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PCMCIA MEMORY AND REGISTERS
Register Name Low Attribute Memory Base Address Registers 0-6 Z80 Control Register Conguration Option Register Conguration Status Register Pin Replacement Register Socket Copy Register Extended Status Register Image Base Address Registers Version Number Register High Attribute Memory I/O Address %0100-177 %0178-17E %017F %0180 %0181 %0182 %0183 %0184 %0185,6 %0187 %0188-1FF Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Host Attr 00-EE even Attr F0-FC even None Attr 100 Attr 102 Attr 104 Attr 106 Attr 108 Attr 10A, C Attr 10E Attr 110-1FE even
PLUG AND PLAY ISA REGISTERS
Register Name PnP Address Register PnP Write Data Register PnP Read Data Register Read Address Register Isolation Register Conguration Control Register Wake Register PnP Master Register Resource Data Register PnP Status Register Card Select Number (CSN) Register Logical Device Number Register Activate Register I/O Range Check Register I/O Mailbox Base Address Registers Mimic Base Address Registers Interrupt Request Level Register DMA Channel 0,1 Registers I/O Address None None None None None None None %0102 %0104 %0105 %0106 None %0130 None %0160,1 %0162,3 %0170 %0174,5 Access Host I/O %0279, WO I/O %0A79, WO I/O %0203-3FF, RO Pnp %00, WO PnP %01, RO PnP %02, WO PnP %03, WO None PnP %04, RO PnP %05, RO PnP %06, R/W PnP %07, RO PnP %30, R/W PnP %31, R/W PnP %60,1, R/W PnP %62,3, R/W PnP %70, R/W PnP %74,5, R/W
R/W WO RO RO R/W R/W R/W R/W R/W
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PACKAGE INFORMATION
1
Figure 38. 144-Lead QFP Package Diagram
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PACKAGE INFORMATION (Continued)
Figure 39. 144-Lead VQFP Package Diagram
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ORDERING INFORMATION
Part Number Z8038220ASC Z8038220FSC Z8L38210ASC Z8L38210FSC VDD 5V 10% 5V 10% 3.3V 10% 3.3V 10% Clock Speed(1) 20 MHz 20 MHz 10 MHz 10 MHz Package Type VQFP QFP VQFP QFP Package Code MKT71C1173-00 MKT71C1163-00 MKT71C1173-00 MKT71C1163-00 Oper. Temp. 0 to +70C 0 to +70C 0 to +70C 0 to +70C
1
Note: 1. Refers to maximum internal bus clock frequency. See AC specifications for maximum external clock speed.
Package
F = QFP (Plastic Quad Flatpack) A = VQFP (Very Small QFP)
Speeds
10 = 10 MHz 20 = 20 MHz
Temperature
S = 0 to +70C
Environmental
C = Plastic Standard
Example:
Z 80382 20 F S C is a Z80382, 20 MHz, QFP, 0 to +70C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prex
(c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
ZilogOs products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com
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