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| IRLR/U014NPbF l l l l l l l PD - 95551A HEXFET(R) Power MOSFET Logic-Level Gate Drive Surface Mount (IRLR024N) Straight Lead (IRLU024N) Advanced Process Technology Fast Switching Fully Avalanche Rated Lead-Free D VDSS = 55V RDS(on) = 0.14 G S ID = 10A Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The D-PAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications. D-Pak TO-252AA I-Pak TO-251AA Absolute Maximum Ratings Parameter ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Max. 10 7.1 40 28 0.2 16 35 6.0 2.8 5.0 -55 to + 175 300 (1.6mm from case ) Units A W W/C V mJ A mJ V/ns C Thermal Resistance Parameter RJC RJA RJA Junction-to-Case Case-to-Ambient (PCB mount)** Junction-to-Ambient Typ. --- --- --- Max. 5.3 50 110 Units C/W www.irf.com ** When mounted on 1" square PCB (FR-4 or G-10 Material ) . For recommended footprint and soldering techniques refer to application note #AN-994 1 12/06/04 IRLR/U014NPbF Electrical Characteristics @ TJ = 25C (unless otherwise specified) V(BR)DSS V(BR)DSS/TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Min. Typ. Max. Units Conditions 55 --- --- V VGS = 0V, ID = 250A --- 0.056 --- V/C Reference to 25C, ID = 1mA --- --- 0.14 VGS = 10V, ID = 6A --- --- 0.21 VGS = 4.5V, ID = 5A 1.0 --- --- V VDS = VGS, ID = 250A 3.1 --- --- S VDS = 25V, ID = 6A --- --- 25 VDS = 55V, VGS = 0V A --- --- 250 VDS = 55V, VGS = 0V, TJ = 150C --- --- 100 VGS = 16V nA --- --- -100 VGS = -16V --- --- 7.9 ID = 6A --- --- 1.4 nC VDS = 44V --- --- 4.4 VGS = 5.0V, See Fig. 6 and 13 --- 6.5 --- VDD = 28V --- 47 --- ID = 6A ns --- 12 --- RG = 6.2, VGS = 5.0V --- 23 --- RD = 4.5, See Fig. 10 Between lead, --- 4.5 --- nH 6mm (0.25in.) G from package --- 7.5 --- and center of die contact --- 265 --- VGS = 0V --- 80 --- pF VDS = 25V --- 38 --- = 1.0MHz, See Fig. 5 D S Source-Drain Ratings and Characteristics IS ISM VSD trr Q rr ton Notes: Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol --- --- 10 showing the A G integral reverse --- --- 40 S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 6A, VGS = 0V --- 37 56 nS TJ = 25C, IF = 6A --- 48 71 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Repetitive rating; pulse width limited by Starting TJ = 25C, L = 1.96mH max. junction temperature. ( See fig. 11 ) Pulse width 300s; duty cycle 2%. This is applied for I-PAK, LS of D-PAK is measured between lead and center of die contact RG = 25, IAS = 6A. (See Figure 12) ISD 6.0A, di/dt 210A/s, VDD V(BR)DSS, TJ 175C 2 www.irf.com IRLR/U014NPbF 100 VGS VGS 15V 15V 10V 12V 5.0V 10V 4.5V 7.0V 3.5V 5.0V 3.0V 4.5V 2.7V 2.7V BOTTOM 2.0V BOTTOM 2.5V TOP TOP 100 I D , Drain-to-Source Current (A) I D , Drain-to-Source Current (A) 10 10 VGS VGS 15V 15V 12V 10V 10V 5.0V 7.0V 4.5V 5.0V 3.5V 4.5V 3.0V 2.7V 2.7V BOTTOM 2.5V BOTTOM 2.0V TOP TOP 1 1 2.5V 2.5V 20s PULSE WIDTH TJ = 25 C 1 10 100 0.1 0.1 0.1 0.1 20s PULSE WIDTH TJ = 175 C 1 10 100 VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100 2.5 I D , Drain-to-Source Current (A) TJ = 25 C TJ = 175 C 10 RDS(on) , Drain-to-Source On Resistance (Normalized) ID = 10A 2.0 1.5 1.0 1 0.5 0.1 2.0 V DS = 50V 20s PULSE WIDTH 4.0 6.0 8.0 10.0 0.0 -60 -40 -20 0 VGS = 10V 20 40 60 80 100 120 140 160 180 VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3 IRLR/U014NPbF 500 400 Ciss VGS , Gate-to-Source Voltage (V) VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd 15 ID = 6 A VDS = 44V VDS = 27V C, Capacitance (pF) 10 300 Coss 200 5 100 Crss 0 1 10 100 0 FOR TEST CIRCUIT SEE FIGURE 13 0 2 4 6 8 10 VDS , Drain-to-Source Voltage (V) QG , Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 100 1000 ISD , Reverse Drain Current (A) OPERATION IN THIS AREA LIMITED BY RDS(on) 10 ID , Drain Current (A) 100 10us 10 TJ = 175 C 100us 1 1ms 1 10ms TJ = 25 C 0.1 0.2 0.6 1.0 V GS = 0 V 1.4 1.8 0.1 TC = 25 C TJ = 175 C Single Pulse 1 10 100 VSD ,Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRLR/U014NPbF 10.0 VDS V GS RG 10V Pulse Width 1 s Duty Factor 0.1 % RD 8.0 D.U.T. + ID , Drain Current (A) -V DD 6.0 4.0 Fig 10a. Switching Time Test Circuit 2.0 VDS 90% 0.0 25 50 75 100 125 150 175 TC , Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature 10% VGS td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms 10 Thermal Response (Z thJC ) D = 0.50 0.20 1 0.10 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1 PDM t1 t2 0.1 0.00001 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRLR/U014NPbF EAS , Single Pulse Avalanche Energy (mJ) 60 TOP 50 15V BOTTOM ID 2.4A 5.0A 6.0A VDS L DRIVER 40 RG D.U.T IAS tp 30 + V - DD 10V 20V A 0.01 20 Fig 12a. Unclamped Inductive Test Circuit 10 0 25 50 75 100 125 150 175 V(BR)DSS tp Starting TJ , Junction Temperature ( C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50K QG 12V .2F .3F 10 V QGS QGD VGS 3mA D.U.T. + V - DS VG Charge IG ID Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit 6 www.irf.com IRLR/U014NPbF Peak Diode Recovery dv/dt Test Circuit D.U.T + + Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer - + RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test + VDD Driver Gate Drive P.W. Period D= P.W. Period VGS=10V * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt VDD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% ISD * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS www.irf.com 7 IRLR/U014NPbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: T HIS IS AN IRFR120 WITH AS S EMBLY LOT CODE 1234 AS S EMBLED ON WW 16, 1999 IN THE AS S EMBLY LINE "A" Note: "P" in as sembly line pos ition indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRFU120 12 916A 34 DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A OR INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRFU120 12 34 DATE CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 16 A = AS S EMBLY S ITE CODE 8 www.irf.com IRLR/U014NPbF I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-251AA) Part Marking Information EXAMPLE: T HIS IS AN IRFU120 WIT H AS S EMBLY LOT CODE 5678 AS S EMBLED ON WW 19, 1999 IN T HE AS S EMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRF U120 919A 56 78 DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A OR INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRFU120 56 78 DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 19 A = AS S EMBLY S IT E CODE www.irf.com 9 IRLR/U014NPbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 ( .641 ) 15.7 ( .619 ) 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive[Q101] market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information12/04 10 www.irf.com Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/ |
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