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NLSF302 Quad 2-Input NOR Gate
The NLSF302 is an advanced high speed CMOS 2-input NOR gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.
Features
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FUNCTION TABLE
Inputs A L L H H B L H L H Output Y H L L L
NLSF302 = Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
Device NLSF302MNR2 NLSF302MNR2G Package QFN-16 QFN-16 (Pb-Free) Shipping 3000/Tape & Reel 3000/Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
May, 2006 - Rev. 4
CCC CCC CCC
* * * * * * * * * * *
High Speed: tPD = 3.6 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 2.0 mA (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Function Compatible with Other Standard Logic Families QFN-16 Package Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model; > 2000 V, Machine Model > 200 V Chip Complexity: 40 FETs or 10 Equivalent Gates Pb-Free Package is Available*
1 QFN-16 MN SUFFIX CASE 485G
MARKING DIAGRAM
16
1
NLSF 302 ALYW G G
Publication Order Number: NLSF302/D
NLSF302
VCC Y4 A1 16 Y1 15
14
13
B1 16 1 4 3 5 7 9 8 10 13 12 Y4 Y3 Y2 Y=A+B A2 15 Y1 Y2
1
NLSF302 MN Package
12
B4
A1 B1 A2 B2 A3 B3 A4 B4
NC
2
11
NC
3
(Top View)
10
A4
4
9
Y3
5 B2
6 GND
7 A3
8 B3
Figure 1. LOGIC DIAGRAM
Figure 2. PIN ASSIGNMENT (QFN-16)
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MAXIMUM RATINGS
Parameter Symbol VCC Vin Value Unit V V V DC Supply Voltage DC Input Voltage - 0.5 to + 7.0 - 0.5 to + 7.0 DC Output Voltage Vout IIK - 0.5 to VCC + 0.5 - 20 20 25 50 450 Input Diode Current mA mA mA mA Output Diode Current IOK Iout DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature ICC PD mW C Tstg - 65 to + 150 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
Parameter DC Supply Voltage DC Input Voltage Symbol VCC Vin Min 2.0 0 0 Max 5.5 5.5 Unit V V V
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DC Output Voltage Vout TA VCC +85 100 20 Operating Temperature -40 0 0 C Input Rise and Fall Time VCC = 3.3 V 0.3 V VCC =5.0 V 0.5 V tr, tf ns/V
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NLSF302
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DC ELECTRICAL CHARACTERISTICS
Parameter Test Conditions Symbol VIH VIL VCC V TA = 25C Typ TA = - 40 to 85C Min Max Min Max Unit V V V Minimum High-Level Input Voltage 2.0 3.0 to 5.5 2.0 3.0 to 5.5 1.50 VCC x 0.7 1.50 VCC x 0.7 Maximum Low-Level Input Voltage Minimum High-Level Output Voltage 0.50 VCC x 0.3 0.50 VCC x 0.3 Vin = VIH or VIL IOH = -50 mA VOHIIII 1.9 2.0 3.0 2.9 4.5 4.4 3.0 4.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 1.9 2.9 4.4 Vin = VIH or VIL IOH = -4 mA IOH = -8 mA Vin = VIH or VIL IOL = 50 mA Vin = VIH or VIL IOL = 4 mA IOL = 8 mA 2.58 3.94 2.48 3.80 Maximum Low-Level Output Voltage VOL 0.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 V 0.36 0.36 0.44 0.44 Maximum Input Leakage Current Maximum Quiescent Supply Current Vin = 5.5 V or GND Vin = VCC or GND Iin 0 to 5.5 5.5 0.1 2.0 1.0 20.0 mA mA ICC
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Parameter Test Conditions
TA = 25C Typ 5.6 8.1 3.6 5.1 4
TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 Max 9.5 13.0 6.5 8.5 10
Symbol tPLH, tPHL
Min
Max 7.9 11.4 5.5 7.5 10
Unit ns
Maximum Propagation Delay, Input A or B to Output Y
VCC = 3.3 0.3 V CL = 15 pF CL = 50 pF VCC = 5.0 0.5 V CL = 15 pF CL = 50 pF
Maximum Input Capacitance
Cin
pF
Typical @ 25C, VCC = 5.0 V 15
Power Dissipation Capacitance (Note 1)
CPD
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0V)
Characteristic Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage
TA = 25C Symbol VOLP VOLV VIHD VILD TEST POINT A or B 50% tPLH Y 50% VCC *Includes all probe and jig capacitance tPHL VCC GND DEVICE UNDER TEST OUTPUT CL* Typ 0.3 - 0.3 Max 0.8 - 0.8 3.5 1.5 Unit V V V V
INPUT
Figure 3. Switching Waveforms
Figure 4. Test Circuit http://onsemi.com
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Figure 5. Input Equivalent Circuit
NLSF302
PACKAGE DIMENSIONS
16 PIN QFN CASE 485G-01 ISSUE C
D
A B
PIN 1 LOCATION
E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50
0.15 C 0.15 C 0.10 C TOP VIEW
16 X
0.08 C SIDE VIEW A1 C
16X
L
5
NOTE 5 4
16X
K
1 12
16X
b BOTTOM VIEW
0.10 C A B 0.05 C
NOTE 3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CC CC CC
(A3) D2 e
8 9 16 13
A
SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
EXPOSED PAD
E2 e
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NLSF302/D

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