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| (R) EL5001 Data Sheet January 31, 2005 FN7376.2 6-Channel Clock Driver The EL5001 is a 6-channel level shifting driver designed primarily for use as a clock driver in LTPS LCD displays. The EL5001 buffers and level shifts six logic level input signals. The six channels are grouped in to two sets, one of two channels and one of four channels. Each set can be configured in the inverting or non-inverting modes. Operating from 3.3V input logic, the output swing is set using two reference input pins. These pins can be up to 18V differential and are not buffered, so should therefore be bypassed effectively. The EL5001 is designed to drive capacitive loads of 500pF with rise and fall times of just 20ns. A three-state pin is provided to set all outputs in to a high impedance mode. The ENABLE pin can be used to put the device in to a power save mode where the power consumption drops to just 3A. The EL5001 is available in 20-pin QFN (4mm x 4mm) and HTSSOP packages. Both are specified for operation over the -40C to +85C temperature range. Features * SIx inverting/non-inverting channels * 3.3V input logic * 18V output * 250A typical supply current * Drives up to 500pF * TR/TF = 35ns max * Disable function * 20-pin QFN (4mm x 4mm) and HTSSOP packages * Pb-free available (RoHS compliant) Applications * LTPS LCD clock drivers * CCD driving * Level shifters Ordering Information PART NUMBER EL5001IL EL5001IL-T7 EL5001IL-T13 EL5001ILZ (See Note) EL5001ILZ-T7 (See Note) EL5001ILZ-T13 (See Note) PACKAGE 20-Pin QFN (4mm x 4mm) 20-Pin QFN (4mm x 4mm) 20-Pin QFN (4mm x 4mm) 20-Pin QFN (4mm x 4mm) (Pb-Free) 20-Pin QFN (4mm x 4mm) (Pb-Free) 20-Pin QFN (4mm x 4mm) (Pb-Free) TAPE & REEL 7" 13" PKG. DWG. # MDP0046 MDP0046 MDP0046 MDP0046 PART NUMBER EL5001IRE EL5001IRE-T7 EL5001IRE-T13 EL5001IREZ (See Note) EL5001IREZ-T7 (See Note) EL5001IREZ-T13 (See Note) PACKAGE 20-Pin HTSSOP 20-Pin HTSSOP 20-Pin HTSSOP 20-Pin HTSSOP (Pb-Free) 20-Pin HTSSOP (Pb-Free) 20-Pin HTSSOP (Pb-Free) TAPE & REEL 7" 13" PKG. DWG. # MDP0048 MDP0048 MDP0048 MDP0048 7" MDP0046 7" MDP0048 13" MDP0046 13" MDP0048 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004, 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL5001 Pinouts EL5001 [20-PIN QFN (4mm x 4mm)] TOP VIEW 18 GND 19 TRI EL5001 (20-PIN HSSOP) TOP VIEW TRI 1 EN 2 20 GND 19 VH 18 OUT1 17 OUT2 THERMAL PAD 16 OUT3 15 OUT4 14 OUT5 13 OUT6 12 VL 11 NC IN1 1 IN2 2 IN3 3 IN4 4 IN5 5 OUT6 10 IN6 6 INV1 7 INV2 8 VL 9 THERMAL PAD 16 NC 15 OUT1 14 OUT2 13 OUT3 12 OUT4 11 OUT5 20 EN 17 VH IN1 3 IN2 4 IN3 5 IN4 6 IN5 7 IN6 8 INV1 9 INV2 10 2 FN7376.2 January 31, 2005 EL5001 Absolute Maximum Ratings (TA = 25C) Supply Voltage between VSD and GND . . . . . . . . . . . . . . . . . . .18V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 50mA Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER POWER SUPPLY IS Supply Current VH = 10V, VL = -5V, EN = 3V, unless otherwise specified. CONDITION MIN TYP MAX UNIT DESCRIPTION EN = 3V, INX = 0V EN = 3V, INX = 3V 750 250 3 -13 5 0 1200 500 A A A IS_DIS VLR VHR VH-VL INPUT VIH IIH VIL IIL CIN RIN OUTPUT VOH VOL ROH ROL IPEAK IL Supply Current - Disabled VL Range VH Range Maximum VH - VL Range EN = 0V, INX = 0V 0 18 18 V V V Logic `1' Input Voltage Logic `1' Input Current Logic `0' Input Voltage Logic `0' Input Current Input Capacitance Input Resistance 2.0 0.1 10 0.8 0.1 3.5 50 10 V A V A pF M VOUTL High VOUTL Low On Resistance VH to OUT On Resistance VL to OUT Peak Output Current Out Leakage Current INX = 10V, IL = 10mA INX = 0V, IL = -10mA IL = 50mA IL = 50mA 9.80 9.88 -4.90 11 11 500 0.1 0.5 -4.88 15 15 V V mA A SWITCHING CHARACTERISTICS tR tF tRFD tD+ tDtDD tEN tDIS Rise Time Fall Time TR, TF Matching Turn On Delay Turn Off Delay tD+, tD-, Matching Enable Time Disable Time CL = 500pF CL = 500pF CL = 500pF CL = 500pF CL = 500pF CL = 500pF 9.8 2.2 20 20 5 55 55 5 35 35 ns ns ns ns ns ns s s 3 FN7376.2 January 31, 2005 EL5001 Typical Performance Curves VOLTAGE (1V/DIV) TIME (40ns/DIV) VOLTAGE (1V/DIV) RL=0 CL=500pF VS=V-=0V VS=V+=18V RISE TIME T=37.55ns FALL TIME T=29ns RL=0 CL=500pF VS=V-=0V VS=V+=18V TIME (40ns/DIV) FIGURE 1. RISE TIME OUTPUT 6VP-P FIGURE 2. FALL TIME OUTPUT 6VP-P VOLTAGE (2V/DIV) TIME (20ns/DIV) VOLTAGE (2V/DIV) RL=0 CL=500pF VS=V-=0V VS=V+=18V RISE TIME T=23.63ns FALL TIME T=22.93ns RL=0 CL=500pF VS=V-=0V VS=V+=18V TIME (20ns/DIV) FIGURE 3. RISE TIME OUTPUT 12VP-P FIGURE 4. FALL TIME OUTPUT 12VP-P VOLTAGE (2V/DIV) RISE TIME T=40.08ns VOLTAGE (2V/DIV) RL=0 CL=500pF VS=V-=0V VS=V+=18V RL=0 CL=500pF VS=V-=0V VS=V+=18V FALL TIME T=30.57ns TIME (20ns/DIV) TIME (20ns/DIV) FIGURE 5. RISE TIME OUTPUT 5VP-P FIGURE 6. FALL TIME OUTPUT 5VP-P 4 FN7376.2 January 31, 2005 EL5001 Typical Performance Curves (Continued) CH2 VOLTAGE (1V/DIV) VOLTAGE (1V/DIV) CH2 ENABLE T=9.8s DISABLE T=2.2s RL=0 CL=500pF VS=V-=0V VS=V+=18V TIME (10s/DIV) CH3 CH3 RL=0 CL=500pF VS=V-=0V VS=V+=18V TIME (10s/DIV) FIGURE 7. DISABLE RESPONSE FIGURE 8. ENABLE RESPONSE VOLTAGE (CH1-1V/DIV)(CH2-5V/DIV) CH2 TURN-OFF T=90ns CH3 RL=0 CL=500pF VS=V-=0V VS=V+=18V TIME (100ns/DIV) VOLTAGE (CH1-1V/DIV)(CH2-5V/DIV) TURN-ON T=90ns CH2 CH3 RL=0 CL=500pF VS=V-=0V VS=V+=18V TIME (100ns/DIV) FIGURE 9. TURN-OFF (TRI) FIGURE 10. TURN-ON (TRI) VOLTAGE (CH2-5V/DIV)(CH3-1V/DIV) CH3 GROUND CH2 VOLTAGE (2V/DIV) RL=0 CL=500pF VS=V-=0V VS=V+=18V 1.78V 1.32V RL=0 CL=500pF VS=V-=0V VS=V+=18V PROPAGATION DELAY T=52ns TIME (2s/DIV) TIME (40ns/DIV) FIGURE 11. ENABLE/DISABLE THRESHOLD FIGURE 12. PROPAGATION DELAY 5 FN7376.2 January 31, 2005 EL5001 Typical Performance Curves (Continued) 150 RL=0 CL=500pF VS=V-=0V VS=V+=18V IIN (mA) RL=0 100 CL=500pF 50 0 -50 -100 -150 -200 -250 -300 -2 TIME (10ns/DIV) -1 0 1 2 3 VIN (V) 4 5 6 7 8 VOLTAGE (200mV/DIV) MAXIMUM SKEW=5.0ns FIGURE 13. SKEW JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - HTSSOP EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 FIGURE 14. INPUT CURRENT vs VOLTAGE 3.5 POWER DISSIPATION (W) 1 0.9 POWER DISSIPATION (W) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 800mW TS JA SO = 12 5 C/ H 3 2.857W 2.5 2 1.5 1 0.5 0 0 25 50 75 85 100 125 150 H TS S JA = 35 O C 0 /W P2 P2 0 W 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) AMBIENT TEMPERATURE (C) FIGURE 15. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 16. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 2.500W (4 Q mF mN 2 =4 x 4 0 0 mm C /W ) 0.8 POWER DISSIPATION (W) JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD 3 POWER DISSIPATION (W) 2.5 2 1.5 1 0.5 0 0.7 667mW 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 150 (4 Q mF mN =1 x 4 2 0 50 m C m) /W JA JA 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) AMBIENT TEMPERATURE (C) FIGURE 17. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 6 FN7376.2 January 31, 2005 EL5001 EL5001 Test Board Circuit Layout TRI R1 50 EN R2 OPEN IN1 R3 50 IN2 R4 50 IN3 R5 50 R6 50 IN4 R7 50 IN5 R8 50 IN6 R9 50 INV1 R10 OPEN INV2 C5 33nF R12 3.3 C12 500pF FERRITE BEAD C6 L 2 4.7F VSD2 MBRM120LT3 5 IN3 6 IN4 7 IN5 8 IN6 9 INV1 10 INV2 OUT3 16 OUT4 15 OUT5 14 OUT6 13 VL 12 NC 11 C9 500pF OUT3 3 IN1 4 IN2 OUT1 18 OUT2 17 C8 500pF OUT2 1 TRI 2 EN GND 20 VH 19 C2 33nF R11 3.3 FERRITE BEAD + C3 L 1 4.7F VS+ D1 MBRM120LT3 C7 500pF OUT1 C10 500pF OUT4 C11 500pF OUT5 OUT6 + GND Block Diagram OE VS+ VH INPUT GND LEVEL SHIFTER 3-STATE CONTROL OUTPUT VSVL 7 FN7376.2 January 31, 2005 EL5001 Applications Information The EL5001, a six channel high performance buffer, is directed primarily as a clock driver to LPTS LCD display applications. The six input channels are grouped into one group of four inputs and one group of two inputs each with a single pin (INV1 or INV2) to toggle the polarity from inverting to non-inverting. Each channel consists of a single Nchannel low side driver and single P-channel high side driver. These 11 devices pull the output to either the high or low voltage on VH and VL respectively, depending on the logic input signal. A common 3-state pin is available that when activated will pull all 6-channel outputs to the high impedance state. Enable and disable pins turn shutdown both inputs and outputs. Timing plots for 3-state, enable, and disable functions are included in the characterization documentation. The EL5001 is available in either a 20-pin HTSSOP or QFN (4mm x 4mm) packages to provide a choice for power dissipation considerations. Power Dissipation Calculation When switching at high speeds, or driving heavy loads, the EL5001 drive capability is limited by the rise in die temperature brought about by internal power dissipation. For reliable operation die temperature must be kept below TJMAX (125C). It is necessary to calculate the power dissipation for a given application prior to selecting package type. Power dissipation may be calculated: 4 2 2 PD = ( V S x I S ) + x ( C INT x V S x f ) + ( C L x V OUT x f ) 1 where: VS = Total power supply to the EL5001 (from VS+ to VS-) VOUT = Swing on the output (VH - VL) CL = Load capacitance CINT = Internal load capacitance (80pF max) IS = Quiescent supply current (3mA max) f = Frequency Having obtained the application's power dissipation, the maximum junction temperature can be calculated: T JMAX = T MAX + JA x PD Supply Voltage and Input Compatibility The EL5001 is designed to operate at a maximum potential range from 0V to 18V. Because the EL5001 does not contain a true analog switch, the positive supply must always be 4V higher than the negative supply. All input pins are compatible with both 3V and 5V CMOS signals. With the positive supply set to VS = 5V the EL5001 is compatible with TTL inputs. where: TJMAX = Maximum junction temperature (125C) TMAX = Maximum ambient operating temperature PD = Power dissipation calculated above JA = Thermal resistance, junction to ambient, of the application (package + PCB combination) Power Supply Bypassing Due to the high switching currents generated by the EL5001 power supply bypassing is very important on both the positive and negative supplies. A 4.7F tantalum capacitor can be used in parallel with a 0.1F low-inductance ceramic MLC capacitor. As with all bypass components, these should be placed as close as possible to the supply pins. We also recommend the VL and VH pins have some level of bypassing especially when the device is driving highly capacitive loads. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 FN7376.2 January 31, 2005 |
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