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E2B0034-27-Y2
Semiconductor MSM6555B-xx
Semiconductor SEGMENT DRIVER
This version: Nov. 1997 MSM6555B-xx Previous version: Mar. 1996
DOT MATRIX LCD CONTROLLER WITH 17-DOT COMMON DRIVER AND 80-DOT
GENERAL DESCRIPTION
The MSM6555B-xx is a dot matrix LCD controller with 17-dot common driver and 80-dot segment driver comprising a display RAM, character generation ROM, LCD bias generation circuit and control circuit. The LCD driving bias generation circuit incorporated in the MSM6555B-xx allows LCD bias voltage to be obtained merely by providing a specified capacitance externally. The MSM6555B-xx can display the arbitrator (arbitrary character) patterned on the LCD panel.
FEATURES
* Serial interface with microcontroller * Dot matrix LCD controller with 17-dot common driver and 80-dot segment driver (up to 16 digits 2 lines can be displayed) * 256 character ROM (5 7 dots) * 1/9 duty (1 line; character + cursor + arbitrator) or 1/17 duty (2 lines; character + cursor, 1 line; arbitrator) display * LCD driving bias voltage generation circuit * 80-dot arbitrator * Low standby current * Gold bump chip * Optional when TCP is adopted
1/27
Semiconductor
MSM6555B-xx
BLOCK DIAGRAM
VDD C1 to C17 VSS 17 COMMON DRIVER S1 to S80 80 SEGMENT DRIVER
VC2
VCC2 LATCH
80
VSS1 LCD BIAS GENERATOR
VSS4
1/4 BIAS VDD VSS1 VSS2,3 VSS4 VSS5
80
SHIFT REGISTER
VSS5
VSS2,3
N1 VOLTAGE REGULATOR N2 RAM (448 BITS)
CHARACTER GENERATOR ROM (256 5 7 DOTS)
BLINK CONTROLLER
VSS6
VC1
VOLTAGE DOUBLER 9
8
VCC1
XT OSC XT
TIMING GENERATOR
SERIAL/PARALLEL INTERFACE
32K/EXT CS 9D/17D RST C/D SHT SO SI
TEST
2/27
Semiconductor
MSM6555B-xx
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDD VI PD TSTG Condition Ta = 25C, VDD-VSS Ta = 25C -- -- Rating -0.3 to +3.5 0 to VDD + 0.3 *1 -55 to +150 Unit Applicable pin V V mW C VDD, VSS All inputs -- --
*1 Power dissipation depends on the radiation characteristic determined by assembling condition. Junction temperature should be set to 150C or less.
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage
IC Internal Oscillation Frequency (*1)
Symbol VDD fINT Top
Condition VDD-VSS -- --
Range 2.5 to 3.3 20 to 38.4 -10 to +70
Unit Applicable pin V kHz C VDD, VSS -- --
Operating Temperature
*1 For the IC internal oscillation frequency, see the explanation of the SF command in Command description. Note: Completely shut off light to ensure that IC chips will not be exposed to light.
3/27
Semiconductor
MSM6555B-xx
ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
Parameter "H" Input Voltage 1 "L" Input Voltage 1 "H" Input Voltage 2 "L" Input Voltage 2 "H" Input Current 1 "L" Input Current "H" Input Current 2 "H" Output Voltage "L" Output Voltage
Off Leakage Current COM Output Resistance SEG Output Resistance
(VDD = 3V 10%, Ta = -10 to +70C) Condition -- -- -- -- VI = VDD VI = 0V VI = VDD IOH = -400mA IOL = 1.5mA VI = VDD/0V IO = 50mA IO = 10mA *1 *2 *3 *4 Min. VDD-0.3 0 0.8VDD 0 -- -- 0.1 VDD-0.5 -- -- -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- 25 20 25 0.5 Max. VDD 0.6 VDD 0.2VDD 1 -1 0.4 -- 0.5 10 5 15 50 40 50 2 Unit V V V V mA mA mA V V mA kW kW mA mA mA mA Applicable pin XT XT Input pins except XT Input pins except XT Input pins except TEST and XT Input pins except XT TEST SO SO SO C1 to C17 S1 to S80 -- -- -- --
Symbol VIH1 VIL1 VIH2 VIL2 IIH1 IIL IIH2 VOH VOL IOFF RC RS IDD1 IDD2 IDD3 IDD4
Supply Current 1 Supply Current 2 Supply Current 3 Supply Current 4
*1 *2 *3 *4
f=32.768 kHz ; crystal oscillation f=32.768 kHz ; external clock f=76.8 kHz ; external clock After reset input "L" pulse input or stop command input:
Note: The above values are guaranteed when the IC chip is not exposed to light.
DC Characteristics (2)
(VDD = 0V, VSS = -3V, Ta = 25C) Parameter Bias Voltage 1 Bias Voltage 2, 3 Bias Voltage 4 Bias Voltage 5 Symbol Condition (Note) VSS1 VSS2, 3 VSS4 VSS5 VSS2, 3 = -2.0V N1 = "H", N2 = "L" contrast = "1" VSS2, 3 = -2.0V VSS2, 3 = -2.0V Min. -1.1 -2.5 -3.1 -4.2 Typ. -1.0 -2.15 -3.0 -4.0 Max. -0.9 -1.7 -2.9 -3.8 Unit V V V V Applicable pin VSS1 VSS2, 3 VSS4 VSS5
Notes:
1. Connect a 0.1 mF capacitor to the LCD bias generator and the voltage doubler. 2. The above values are guaranteed when the IC chip is not exposed to light.
4/27
Semiconductor Switching Characteristics
Parameter CS Setup Time CS Hold Time SO ON Delay Time SO OFF Delay Time SO Output Delay Time Input Setup Time Input Hold Time Waveform Rise/Fall Time Reset Pulse Input Pulse Width
VIH CS tCH SI VIH VIL VIH VIL
MSM6555B-xx
(VDD - VSS = 3V 10%, Ta = -10 to +70C) Symbol tCS tCH tON tOFF tDLY tIS tIH tr, tf tRT Condition -- -- -- -- -- CL = 45pF -- All inputs -- Min. 300 200 -- 0 0 200 200 -- 5 Max. -- -- 200 200 200 -- -- 50 --
VIH VIL
Unit ns ns ns ns ns ns ns ns ms
C/D
VIH VIL tIS VIH
VIH VIL tIH VIH VIL VIH tOFF "Z"
SHT tCS "Z" VOH VOL tON RST
VIL
SO
VOH VOL tDLY tRT
VIL
VIL VIH = 0.8 VDD, VOH = VDD -0.5V VIL = 0.2 VDD, VOL = 0.5V
5/27
Semiconductor
MSM6555B-xx
FUNCTIONAL DESCRIPTION
Pin Functional Description * SI (Serial Input) This is an input pin used to input the command and display data serially in the 8-bit unit, where "H" is defined as 1 and "L" is as 0. When the CS pin is at "H" level, command or display data is read by the rising edge of SHT. Whether the input data is command or display data is determined by the setting of the C/D at the 8th rising edge of the SHT. The input data is command when C/D = "H", and is display data when C/D = "L". * C/D (Command/Data) This is an input pin used to determine whether the data input into the SI pin is command or display data. It is read at the 8th rising edge of the SHT. The input data is command when C/D = "H", and is display data when C/D = "L". * SHT (Shift Clock) This is a read clock for SI input and C/D input, which are read at the rising edge of SHT. Reading completes in 8 clocks. Maintain this SHT pin at "H" when there is no command and data input from the SI pin. Input during the busy condition will result in operation errors. It is valid when the CS pin is at "H". * SO (Serial Out) This is a busy/non-busy and display data serial read-out pin, where "H" is defined as 1 and "L" is as 0. It is output when CS = "H" and the Serial Out Enable is set by the command, while high impedance occurs otherwise. The busy/non-busy signal is output when CS input is at the "H" level. The "H" represents the non-busy state while "L" denotes the busy state. The busy state occurs after the 8th rising edge of the SHT, and the state is automatically shifted to the non-busy state after the lapse of a specified time. Furthermore, the display data is output synchronously with the falling edge of the SHT. * CS (Chip Select) This is a chip select pin, where "H" represents the Select and "L" the Non-select. "L" input causes the SO pin to be opened, and the SHT pin corresponds to "H" inside the IC. For the SI, C/D, SHT, SO and CS, see "I/O Procedure". * RST (Reset) Input of "L" level pulse into this pin will suspend the oscillation to prevent the breakthrough current in the oscillation phase, and the Common and Segment outputs is set to the reset state where VDD level is output. This reset state can be released only by command input. (See STOP command.) Furthermore, contrast control will be the minimum in the combination of N2 and N1. Setting this pin to "L" level during the command execution will cause operation errors. When power is turned on, the RST pin must be set to "L". This pin is based on direct input reset method. Current consumption is 5 to 10 mA during the process of "L" input, so fixed "L" input must not be set. 6/27
Semiconductor
MSM6555B-xx
* 9D/17D (1/9Duty/1/17Duty) This is a duty setting pin where "H" is defined as 1/9 duty and "L" as 1/17 duty. Select the level in conformity to the panel used. In the case of 1/17 duty, the Common outputs C10 to C16 must be kept open. * 32K/EXT (32K x'tal osc/External clock) This is an input pin used to set up the type of logic source oscillation. 32K/EXT = "H" : In this setting, 32.768 kHz is used for source oscillation frequency. The oscillation feedback resistor (approx. 4 MW) is formed in the IC, and the external 32.768 kHz crystal and oscillating capacitors are connected to the XT and XT, thereby forming the oscillator circuit. When the source oscillation clock is input from outside, it is put into the XT, and XT is kept open. 32K/EXT = "L" : This is used to input the source oscillation clock of about n-th power (n=1 to 4) of 2 of 32kHz. Conforming to the command SF setting, the external source oscillation frequency is divided into 1/2 to 1/16 in the IC and is used as source oscillation frequency in the IC. The XT is kept open. AE See SF command. * TEST This is a pin used for test in our company. This pin is kept open for the user. * XT, XT These are pins for 32.768 kHz crystal-controlled oscillator circuit formation and external source oscillation input. XT is kept open, when the souce oscillation clock is input from outside. * C1 to C17, S1 to S80 (COMMON 1 to 17, SEGMENT 1 to 80) These are output pins connected to the LCD panel. Alternation is provided by reserving the frame. During the 1/9 duty operation, C1 to C9 are used with C10 to C17 kept open. AE See "Relation between Display Screen and Common and Segment Outputs". * VC1, VCC1 These are pins to connect the capacitor to double the battery voltage. They are connected with the capacitor of 0.1 mF.
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Semiconductor
MSM6555B-xx
Arbitrator
C1 C2
Character
C8 Cursor C9
C10
Character
C16 Cursor C17
Segment Output
S1
S5
S6
S10
S76
S80
Common Output
Relation between Display Screen and Common and Segment Outputs * VSS6 This is a pin to connect the capacitor to store the doubled voltage. The capacitor of 0.1 mF or more is connected between this pin and VDD. * VSS2, 3 This is power pin to be used after the doubled voltage has passed through the regulator. They provide the reference voltage used in the LCD bias voltage generator. The capacitor of 0.1 mF is connected between this pin and VDD for electric charge distribution among capacitors and voltage stabilization during generation of various types of LCD bias voltage. * VC2, VCC2 These pins are used to connect the capacitors for electric charge distribution to generate LCD bias voltage with reference to VSS2, 3. They are connected with the capacitor of 0.1 mF.
8/27
Semiconductor
MSM6555B-xx
* VSS1, VSS4, VSS5 Connect a capacitor of 0.1 mF between these pins and VDD for electric charge distribution and voltage stabilization concerning the capacitor of VSS2, 3 during generation of various types of LCD bias voltage. The logical value for LCD bias voltage is as shown below. VDD VSS1 = VSS2, 3/2 VSS2, 3 VSS4 = VSS2, 3 + VSS2, 3/2 Lowest voltage : VSS5 = VSS2, 3 + VSS2, 3/2 + VSS2, 3/2 AE This is 1/4 bias, which is common to 1/9 duty and 1/17 duty. * N1, N2 These are input pins used to determine the voltage of VSS2, 3 in combination with the Contrast Up/Down command.
N2 L L H H N1 L H L H Command contrast control range 0 to 7 1 to 8 2 to 9 3 to A
Highest voltage :
* VDD, VSS These are pins used to connect the VDD to the positive pin of the battery, and the VSS to the negative pin of the battery.
9/27
Semiconductor
MSM6555B-xx
Command List
No. Mnemonic
1 2 3 LPA LOT SF
X : Don't Care
Operation
Load Pointer Address Load Option Set Frequency
D 7 1 1 1 6 1 0 0 5 A5 1 1 4 A4 1 0 3 A3 X X 2 A2 X X 1 A1 I1 F1 0 A0 I0
Comment
* Addresses from 0 to 47
4 5
BKCG 1/0 CONT U/D
Bank Change 1/0 Contrast Up/Down
1 1
0 0
0 0
X X
0 0
0 0
0 1
6
STOP
Set Stop Mode
1
0
0
X
0
1
0
7
SOE/D
Serial Out Enable/Disable
1
0
0
X
0
1
1
* For the functions of I1 and I0, see the next page. * Setting the source oscillation frequency F0 conditions * Valid only for 1/19 duty 1/0 * Switching between display addresses 0 to 15, and 16 and 31 1/0 * VLCD adjustment, 8 stages * Released by setting DO = 1 independently of the H/L of the C/D 0 * Oscillation suspension and DISPOFF instruction * Switching output and high impedance of 1/0 SO * On when DO = 1, and off when DO = 0 * Continued OSC 1/0 * All COM and SEG are at VDD level when turned off * Pointer address is incremented by one X * The relative operation with with (I1, I0) is exceptional. * Character and arbitrator blinking is controlled. The arbitrator is based on X the 5-dot unit. * For the arbitrator, blink setting is accepted even if all 5 dots are displayed X in blinks, but blinking does not occur. X * Cursor on X * Cursor off * Cursor blinking is controlled. If the X cursor display not specified, blink setting is accepted, but blinking does not occur. X X X * WCHB + WCSB * CCHB + CCSB
8
DISP
Display On/Off
1
0
0
X
1
0
0
9
AINC
Address Increment
1
0
0
X
1
X
1
10
WCHB
Write Character Blink Clear Character Blink Write Cursor Clear Cursor Write Cursor Blink
0
X
X
X
0
0
0
11 12 13 14
CCHB WCS CCS WCSB
0 0 0 0
X X X X
X X X X
X X X X
0 0 0 1
0 1 1 0
1 0 1 0
15 16 17
CCSB WCCB CCCB
Clear Cursor Blink Write Character Cursor Blink Clear Character Cursor Blink
0 0 0
X X X
X X X
X X X
1 1 1
0 1 1
1 0 1
Note:
1. Commands number 1 to 8, do not affect pointer address. 2. When commands from 9 to 17 and display code data are input, the pointer address is automatically incremented by one (1).
10/27
Semiconductor LOT command function list
I1 0 0 1 1 I0 0 1 0 1 Function Operation is cancelled (No operation)
Hereafter, equivalent to writing blank code at each AINC execution Hereafter, cursor off and blink-cancellation are carried out at each AINC execution
MSM6555B-xx
Comment -- Used to mechanical RAM clear when power is turned on
Both of above two operations are indicated
11/27
Semiconductor Command Description [D7, D6, D5, D4, D3, D2, D1, D0] X = Don't care
MSM6555B-xx
* LPA (Load Pointer Address) [1, 1, A5, A4, A3, A2, A1, A0] This is a command to set up the address for the address pointer to specify the address subjected to command execution and address for display data input. * LOT (Load Option) [1, 0, 1, 1, X, X, I1, I0] This is a command to process the display of the current address in conformity to execution of the AINC command. The I1 and I0 of the command are used to assign the definition. I1 = 1 : Cancellation of cursor and stop of character and cursor blinking for each AINC execution 0 : Cancellation of above definition I0 = 1 : The blank code is set up for each AINC execution and the display is turned off. When the current address is an arbitrator, all five dots are turned off. 0 : Cancellation of above definition I1 and I0 can be set independently of each other. * SF (Set Frequency) [1, 0, 1, 0, X, X, F1, FO] This command sets up the number of divisions to be applied the source oscillation frequency to be input from the XT in order to get the source oscillation inside the IC. This is valid when 32 K/EXT pin = "L". The following table lists the source frequencies inside the IC.
F1 0 0 1 1 F0 0 1 0 1 Source frequency inside IC XT/2 XT/4 XT/8 XT/16
The following shows the blinking frequency: 32 K/EXT = "H" : The blinking frequency is 1 Hz when 32.768 kHz is input. When another frequency is input, the blinking frequency is proportionate to that frequency. 32 K/EXT = "L" : If (F1, F0) = (0, 0): The blinking frequency is 1 Hz when 76.8 kHz is input. When another frequency is input, the blinking frequency is proportionate to that frequency.
12/27
Semiconductor
MSM6555B-xx
If (F1, F0) = (0, 1), (1, 0), (1, 1) the blinking frequency will be as follows: 1 Hz 32.768 kHz /A A = XT input frequency/source frequency inside IC The following shows the frame frequency: When 32 K/EXT = "H", and 32.768 kHz input is assumed, we get the following: approximately 65 Hz in the case of 1/9 duty approximately 68.8 Hz in the case of 1/17 duty When another frequency is input, the blinking frequency is proportionate to that frequency. When 32 K/EXT = "L", the frame frequency is in proportion to the IC internal source oscillation set up by (F0, F1) with reference to the IC internal source oscillation of 32.768 kHz. * BKCG1/0 (Bank Change 1/0) [1, 0, 0, X, 0, 0, 0, 1/0] This command is valid only for 1/9 duty display, and provides switching (BANK switching) of the display address group. When "0" is set, display addresses are in the range from 0 to 15 and from 32 to 47. When "1" is set, display addresses are in the range from 16 to 31 and from 32 to 47. The command and display data can be set despite BANK setting. * CONT U/D (Contrast Up/Down) [1, 0, 0, X, 0, 0, 1, 1/0] This is a command to select the voltage VSS2, 3 serving as bases for LCD. The contrast is changed by changing the voltage VSS2, 3. The contrast is controlled by the value on the up/down three-bit counter and is available in 8 stages. The up/down counter counts up the number when "1" is input by this command, while it counts down the number when "0" is input by this command. Counting is carried out in a loop from "0" to "7". The counter execution values change from 1 to 8, from 2 to 9 and from 3 to A by setting the N2 and N1. Example : ...67012345670... * STOP (Set Stop Mode) [1, 0, 0, X, 0, 1, 0, 0] The oscillation stage is stopped to prevent breakthrough current in the oscillation stage. At the same time, VDD level is output to all pins of LCD output to start the standby mode. The standby mode is released when D0 = 1 is set by serial input, independently of C/D input setting. When D0 = 1 command or data is input, this command or data is executed and input, and the standby mode is also released. * SOE/D (Serial Out Enable/Disable) [1, 0, 0, X, 0, 1, 1, 1/0] This is a command to control the impedance of SO output pin. When "1" is set, the display data is output from the SO pin. When "0" is set, the SO pin becomes a high impedance. 13/27
Semiconductor
MSM6555B-xx
* DISP (Display On/Off) [1, 0, 0, X, 1, 0, 0, 1/0] This is a control command to turn on and off the LCD panel display. The display turns on when "1" is set, and turns off when "0" is set. When it turns off, the VDD level is output to both Common and Segment pins. It should be noted, however, that oscillation is not stopped even when the display is set to the off position. * AINC (Address Increment) [1, 0, 0, X, 1, X, 1, X] This is a command to increment the address pointer value by one. The value is incremented by one every time this command is input. Furthermore, processing specified by the LOT command is applied to the address denoted by the address pointer value before it is incremented by one every time this command is input. * WCHB (Write Character Blink) [1, X, X, X, 0, 0, 0, X] This is a command to specify the character and arbitrator blinking. This is done to the address denoted by the address pointer. In the case of characters, blinking alternates between alldisplay-off state (35 dots) and character display state. In the case of arbitrator, only the Onbit alternates between the display on/off states. Arbitrator blinking control is made in the 5dot unit. * CCHB (Clear Character Blink) [0, X, X, X, 0, 0, 1, X] This is a command to cancel the blinking of characters and arbitrators, and is done to the address indicated by the address pointer. * WCS (Write Cursor) [0, X, X, X, 0, 1, 0, X] This is a command to turn on the cursor, and is done to the address indicated by the address pointer. * CCS (Clear Cursor) [0, X, X, X, 0, 1, 1, X] This is a command to turn off the cursor, and is done to the address indicated by the address pointer. * WCSB (Write Cursor Blink) [0, X, X, X, 1, 0, 0, X] This is a command to blink the cursor, and is done to the address indicated by the address pointer. It should be noted, however, that blinking does not occur to the address where cursor display is not specified. Blinking starts when the cursor display is specified.
14/27
Semiconductor
MSM6555B-xx
* CCSB (Clear Cursor Blink) [0, X, X, X, 1, 0, 1, X] This is a command to cancel cursor blinking, and is done to the address indicated by the address pointer. It can be set to the address where cursor display is not specified. * WCCB (Write Character Cursor Blink) [0, X, X, X, 1, 1, 0, X] This is a command to execute both the WCHB and WCSB commands. * CCCB (Clear Character Cursor Blink) [0, X, X, X, 1, 1, 1, X] This is a command to execute both the CCHB and CCSB commands. * Address Pointer Increment (+1) When display data are input and the following command is executed, the address pointer is incremented by one: AINC, WCHB, CCHB, WCS, CCS, WCSB, CCSB, WCCB and CCCB * Character Blink Method The character on-state alternates with the character dot all-display-off state, as illustrated below: Example of blinking (Character "A")
"A"
All-display-off state
15/27
Semiconductor I/O Procedure * Input timing (command input, display code and data input)
MSM6555B-xx
CS C/D DON'T CARE C/D
SI
MSB
LSB
SHT "Z" BUSY
SO
MSB LSB
Non-BUSY/BUSY
(1)
(1) Max 2 {COMMON 1-line display time}
Starting of the CS provides input synchronization in the 8-bit unit. Subsequent CS rising edge is not necessary if the 8-bit unit is maintained.
16/27
Semiconductor
MSM6555B-xx
* Output timing (display code and data read) If the SOE command has already been input, the code or the arbitrator data of the address currently indicated by the address pointer is output from SO pin.
CS C/D
Synchronization of 8-bit unit
DON'T CARE
C/D
SHT "Z" BUSY
SO
MSB LSB
Non-BUSY/BUSY
(1)
(1) Max 2 {COMMON 1-line display time}
Note: If CS is set to "L" and is again set to "H" without completion of read-out 8 bits, the previous uncompleted portion will be output continuously, the extra read-out data will be "0".
17/27
Semiconductor Display Screen and Memory Address Display
MSM6555B-xx
Arbitrator
Character I
Cursor I
Character II
Cursor II
RAM Map
32 33 47 Arbitrator
0
1
15
Character I
0
1
15
Cursor I
16
17
31
Character II
16
17
31
Cursor II
Note: Characters are input by codes. Arbitrators are displayed independently of the CG ROM. The following shows the relationship between the input data and display of Arbitrators:
S5n+1 S5n+5 S: Segment n: 0 to 15 Serial input data from D7 to D5 require dummy input. Either "1" or "0" may be used for input data from D7 to D5.
D4
D0
18/27
Semiconductor Code and Character Font of MSM6555B-02
00H 08H 10H 18H 20H 28H 30H
MSM6555B-xx
38H
01H
09H
11H
19H
21H
29H
31H
39H
02H
0AH
12H
1AH
22H
2AH
32H
3AH
03H
0BH
13H
1BH
23H
2BH
33H
3BH
04H
0CH
14H
1CH
24H
2CH
34H
3CH
05H
0DH
15H
1DH
25H
2DH
35H
3DH
06H
0EH
16H
1EH
26H
2EH
36H
3EH
07H
0FH
17H
1FH
27H
2FH
37H
3FH
19/27
Semiconductor
MSM6555B-xx
40H
48H
50H
58H
60H
68H
70H
78H
41H
49H
51H
59H
61H
69H
71H
79H
42H
4AH
52H
5AH
62H
6AH
72H
7AH
43H
4BH
53H
5BH
63H
6BH
73H
7BH
44H
4CH
54H
5CH
64H
6CH
74H
7CH
45H
4DH
55H
5DH
65H
6DH
75H
7DH
46H
4EH
56H
5EH
66H
6EH
76H
7EH
47H
4FH
57H
5FH
67H
6FH
77H
7FH
20/27
Semiconductor
MSM6555B-xx
80H
88H
90H
98H
A0H
A8H
B0H
B8H
81H
89H
91H
99H
A1H
A9H
B1H
B9H
82H
8AH
92H
9AH
A2H
AAH
B2H
BAH
83H
8BH
93H
9BH
A3H
ABH
B3H
BBH
84H
8CH
94H
9CH
A4H
ACH
B4H
BCH
85H
8DH
95H
9DH
A5H
ADH
B5H
BDH
86H
8EH
96H
9EH
A6H
AEH
B6H
BEH
87H
8FH
97H
9FH
A7H
AFH
B7H
BFH
21/27
Semiconductor
MSM6555B-xx
C0H
C8H
D0H
D8H
E0H
E8H
F0H
F8H
C1H
C9H
D1H
D9H
E1H
E9H
F1H
F9H
C2H
CAH
D2H
DAH
E2H
EAH
F2H
FAH
C3H
CBH
D3H
DBH
E3H
EBH
F3H
FBH
C4H
CCH
D4H
DCH
E4H
ECH
F4H
FCH
C5H
CDH
D5H
DDH
E5H
EDH
F5H
FDH
C6H
CEH
D6H
DEH
E6H
EEH
F6H
FEH
C7H
CFH
D7H
DFH
E7H
EFH
F7H
FFH
22/27
Semiconductor Supplement
MSM6555B-xx
(1) Display when power is turned on, and command execution time (for 32K/EXT = L) * When 32K/EXT = L, source oscillation is subjected to frequency division inside the IC by the value of (F1, F0), and is utilized for logic operation as a source oscillation inside the IC. * When power is turned on, (F1, F0) is not stable, and the source oscillation inside the IC uses the range from 1/2 to 1/16 of XT frequency. * On the other hand, the LCD frame frequency is determined by the ratio of the source oscillation inside the IC to 32.768 kHz. Example 1: When XT = 65.536 kHz and (F1, F0) = (0, 0), the source oscillation inside the IC is 32.768 kHz, and frame frequency is as follows: approximately 65 Hz in the case of 1/9 duty approximately 68.8 Hz in the case of 1/17 duty Example 2: When XT = 65.536 kHz and (F1, F0) = (1, 1), the source oscillation inside the IC is 4.096 kHz, and frame frequency is as follows: approximately 8.13 Hz in the case of 1/9 duty approximately 8.6 Hz in the case of 1/17 duty
* Thus, (F1, F0) must be determined before start of display. * The command execution time depends on the source oscillation inside the IC. The maximum command execution time corresponds to the display time for two Common lines. * Thus, the command execution time will be as follows in the case of Examples: 1 and 2: Example 1: in the case of 1/17 duty Common one-line display time (Ct0) (Ct0) = 1 / 68.8 (Hz) / 17 (common) = 855 ms Thus, command execution time is Ct0 2 = 1710 ms (max.) Example 2: in the case of 1/9 duty Common one-line display time (Ct0) (Ct0) = 1 / 8.13 (Hz) / 9 (common) = 13.67 ms Thus, command execution time is Ct0 2 = 27.33 ms (max.) * As described above, command execution time to completion of setting the (F1, F0) after power is turned on from 0 volt (Note: including this SF command execution time) depends on the incidental (F1, F0) value when power is turned on and external source frequency, so it is necessary to calculate the maximum value to reflect the result in software design up to completion of setting the (F1, F0).
23/27
Semiconductor
MSM6555B-xx
(2) Standby mode The standby mode can be started either by the RST pin method or Stop command method. The following shows the difference between the RST pin method and Stop command method at the time of resetting:
-- Contrast Value RST pin method Minimum value in combination of (N1, N2) Stop command method Holding of the value before standby mode
For registers except for the above (blink setting, bank switching, etc.), there is no difference between the RST pin method and Stop command method; the state before the standby mode is held. The standby mode is released when D0 = 1 is set by serial input, independently of C/D input setting. The command or data input in this case is also valid.
24/27
Semiconductor
MSM6555B-xx
APPLICATION CIRCUITS
LCD PANEL VDD (2.5 to 3.3V)
17 VDD C VDD C C C C C=0.1mF C VDD C VC1 VCC1 VC2 VCC2 VSS6 VSS N1 N2 CS C/D SHT MSM6555B-xx VSS1 VSS2, 3 VSS4 VSS5 C1 to C17
80 S1 to S80 XT XT 22pF or
32K/EXT 9D/17D
VDD or VSS VDD or VSS
RST SO SI TEST
VDD or VSS VDD or VSS
OPEN
PORT
25/27
Semiconductor
MSM6555B-xx
PAD CONFIGURATION
Pad Layout Chip size : 7.16 4.96mm
Y 95 96 59 58
X
121 1 32
33
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pad Name S77 S78 S79 S80 VDD SO XT XT TEST 32K/EXT RST 9D/17D SHT SI C/D CS N2 N1 VSS5 VSS4 x (mm) -3023 -2857 -2691 -2525 -2139 -1944 -1764 -1591 -1418 -1245 -1072 -899 -726 -553 -380 -207 -34 139 380 560 y (mm) -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 Pad No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pad Name VSS2, 3 VSS1 VCC2 VC2 VCC1 VC1 VSS6 VSS C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 x (mm) 740 920 1100 1280 1460 1640 1820 2188 2528 2694 2860 3026 3426 3426 3426 3426 3426 3426 3426 3426 y (mm) -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2325 -2083 -1917 -1751 -1585 -1419 -1253 -1087 -921
26/27
Semiconductor
MSM6555B-xx
Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
Pad Name C13 C14 C15 C16 C17 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40
x (mm) 3426 3426 3426 3426 3426 3426 3426 3426 3426 3426 3426 3426 3426 3426 3426 3426 3426 3426 3027 2861 2695 2529 2363 2197 2031 1865 1699 1533 1367 1201 1035 869 703 537 371 205 39 -127 -293 -459 -625 -791 -957 -1123 -1289
y (mm) -755 -589 -423 -257 -92 75 240 406 572 738 904 1070 1236 1402 1568 1734 1900 2066 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325
Pad No. 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121
Pad Name S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76
x (mm) -1455 -1621 -1787 -1953 -2119 -2285 -2451 -2617 -2783 -2949 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426 -3426
y (mm) 2325 2325 2325 2325 2325 2325 2325 2325 2325 2325 2066 1900 1734 1568 1402 1236 1070 904 738 572 406 240 75 -92 -257 -423 -589 -755 -921 -1087 -1253 -1419 -1585 -1751 -1917 -2083
27/27

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