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LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
DESCRIPTION
The LF3338 is a lower cost version of the 12-bit LF3330 and is suited for multimedia and special effects systems, projectors, plasma display panels, scan converters, set-top boxes, and other consumer applications. This device filters digital images in the vertical dimension at real-time video rates. Input data is 8 bits and coefficient data is 12 bits and both are in two's complement format. The output is also in two's complement format and may be rounded to 16 bits. The filter is an 8-tap FIR filter with all required line buffers contained onchip. The line buffers can store video lines with lengths from 4 to 3076 pixels. Multiple LF3338s can be cascaded together to create larger vertical filters. Due to the length of the line buffers, interleaved data can be fed directly into the device and filtered without separating the data into individual data streams. The number of interleaved data sets that the device can handle is limited only by the length of the on-chip line buffers. If the interleaved video line has 3076 data values or less, the filter can handle it. The LF3338 contains enough on-board memory to store 256 coefficient sets. The LF InterfaceTM allows all 256 coefficient sets to be updated within vertical blanking. Selectable 16-bit data output with user-defined rounding and limiting minimizes the constraints put on coefficient sets for various filter implementations.
FEATURES
u u u u u 83 MHz Data Rate 8-bit Data and 12-bit Coefficients Supports Interleaved Data Streams Cascadable for More Filter Taps Seven 3K x 8-bit, Dynamic Programmable Two-Mode Line Buffers
u On-board Memory for 256 Coefficient Sets u LF InterfaceTM Allows All 256 Coefficient Sets to be Updated Within Vertical Blanking u Selectable 16-bit Data Output with User-Defined Rounding and Limiting u Separate Input Port for Odd and Even Field Filtering u u u u 8 Filter Taps 3.3 Volt Power Supply 5 Volt Tolerant I/O Purchase Description
LF3338 BLOCK DIAGRAM
8 DIN7-0
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
8-TAP VERTICAL FILTER 256 COEFFICIENT SET STORAGE
32
8 VB7-0
3K LINE BUFFER
ROUND SELECT LIMIT CIRCUITRY OED
16 DOUT15-0
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER 8
COUT7-0
OEC
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FIGURE 1.
CEN
8 ACC Coef Bank 7 4 12 8 20 12 12 12 Coef Bank 6 Coef Bank 5 Coef Bank 4 RSL3-0 OED
DEVICES INCORPORATED
CA7-0
SHEN
8
DIN7-0
8 3K Line Buffer 22 8 3K Line Buffer "0" 8 3K Line Buffer 20 20
20
LF3338 FUNCTIONAL BLOCK DIAGRAM
32
16
LIMIT
16 DOUT15-0
ROUND
8 20
3K Line Buffer 8
VB7-0
8 3K Line Buffer
20 22
8 3K Line Buffer
20
8 3K Line Buffer 12 12 12 12
20
OEC
8
COUT7-0
12 LF INTERFACE Coef Bank 0 Coef Bank 1 Coef Bank 2 Coef Bank 3
CF11-0
LD
PAUSE
CLK
8-Bit Vertical Digital Image Filter
Video Imaging Products
CONFIGURATION AND CONTROL REGISTERS
SELECT
2
LF3338
04/06/1999-LDS.3338-B
LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
FIGURE 2. INPUT FORMATS
Input Data 765 -27 26 25
(Sign)
SIGNAL DEFINITIONS Power VCC and GND +3.3 V power supply. All pins must be connected. Clock CLK -- Master Clock The rising edge of CLK strobes all enabled registers. Inputs DIN7-0 -- Data Input DIN7-0 is the 8-bit registered data input port. Data is latched on the rising edge of CLK. VB7-0 -- Field Filtering Data Input VB7-0 is the 8-bit registered data input port used only when implementing Odd and Even Field Filtering (see Functional Description section for a full discussion). Data is latched on the rising edge of CLK. CF11-0 -- Coefficient Input CF11-0 is used to load data into the coefficient banks and configuration/ control registers. Data present on CF11-0 is latched into the LF InterfaceTM on the rising edge of CLK when LD is LOW (see the LF InterfaceTM section for a full discussion). CA7-0 -- Coefficient Address CA7-0 determines which row of data in the coefficient banks is fed to the multipliers. CA7-0 is latched into the Coefficient Address Register on the rising edge of CLK when CEN is LOW. Outputs DOUT15-0 -- Data Output DOUT15-0 is the 16-bit registered data output port.
Coefficient Data 11 10 9 -20 2-1 2-2
(Sign)
210 22 21 20
210 2-9 2-10 2-11
TABLE 1. OUTPUT FORMATS
SLCT4-0 00000 00001 00010 S15 S14 S13 F15 F14 F13 F16 F15 F14 F17 F16 F15
*** *** *** ***
S8 F8 F9 F10
S7 F7 F8 F9
*** *** *** ***
S2 F2 F3 F4
S1 F1 F2 F3
S0 F0 F1 F2
* * *
01110 01111 10000
* * *
* * *
* * * *** *** ***
* * *
* * * *** *** ***
* * *
* * *
* * *
F29 F28 F27 F30 F29 F28 F31 F30 F29
F22 F21 F23 F22 F24 F23
F16 F15 F14 F17 F16 F15 F18 F17 F16
COUT7-0 -- Cascade Data Output COUT7-0 is a 8-bit cascade output port. COUT7-0 on one device should be connected to DIN7-0 of another LF3338. Controls LD -- Coefficient Load When LD is LOW, data on CF11-0 is latched into the LF Interface TM on the rising edge of CLK. When LD is HIGH, data can not be latched into the LF Interface TM. When enabling the LF Interface TM for data input, a HIGH to LOW transition of LD is required in order for the input circuitry to function properly. Therefore, LD must be set HIGH immediately after power up to ensure proper operation of the input circuitry (see the LF Interface TM section for a full discussion).
FIGURE 3. ACCUMULATOR FORMAT
Accumulator Output 31 30 29 -216 215 214
(Sign)
210 2-13 2-14 2-15
PAUSE -- LF InterfaceTM Pause When PAUSE is HIGH, the LF InterfaceTM loading sequence is halted until PAUSE is returned to a LOW state. This effectively allows the user to load coefficients and control registers at a slower rate than the master clock (see the LF InterfaceTM section for a full discussion). CEN -- Coefficient Address Enable When CEN is LOW, data on CA7-0 is latched into the Coefficient Address Register on the rising edge of CLK. When CEN is HIGH, data on CA7-0 is not latched and the register's contents will not be changed.
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LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
FIGURE 4. RSL CIRCUITRY
RSL3-0 4 DATA IN 32
TABLE 2.
BITS 11-0
CONFIGURATION REGISTER 0 - ADDRESS 200H
FUNCTION Line Buffer Length DESCRIPTION See Line Buffer Description Section
TABLE 3.
BITS 0 1 2
CONFIGURATION REGISTER 1 - ADDRESS 201H
Line Buffer Mode Line Buffer Load Odd and Even Field Filtering Port Enable 0 : Delay Mode 1 : Recirculate Mode 0 : Normal Load 1 : Parallel Load 0 : VB Port Disabled 1 : VB Port Enabled 0 : VB Line Buffer Disabled 1 : VB Line Buffer Enabled
S15 S0
5 SELECT 32
R0
FUNCTION
DESCRIPTION
32 RND
3
Odd and Even Field Filtering Line Buffer Enable
11-4
Reserved
Must be set to "0"
TABLE 4.
BITS 0 11-1
CONFIGURATION REGISTER 2 - ADDRESS 202H
FUNCTION Limit Enable Reserved DESCRIPTION 0 : Limiting Disabled 1 : Limiting Enabled Must be set to "0"
L15 L0
32 LIMIT 16
TABLE 5.
BITS 0 11-1
CONFIGURATION REGISTER 3 - ADDRESS 203H
FUNCTION Cascade Mode Reserved DESCRIPTION
RSL CIRCUITRY
R15
0 : First Device 1 : Cascaded Device Must be set to "0"
16 DATA OUT
ACC -- Accumulator Control When ACC is HIGH, the accumulator is enabled for accumulation and the accumulator output register is disabled for loading. When ACC is LOW, no accumulation is performed and the accumulator output register is enabled for loading. ACC is latched on the rising edge of CLK. SHEN -- Shift Enable SHEN enables or disables the loading of data into the input/ cascade registers and the line buffers. When SHEN is LOW, data is loaded into the input/cascade
registers and shifted through the line buffers on the rising edge of CLK. When SHEN is HIGH, data can not be loaded into the input/ cascade registers or shifted through the line buffers and their contents will not be changed. RSL3-0 -- Round/Select/Limit Control RSL3-0 determines which of the sixteen user-programmable round/ select/limit registers are used in the round/select/limit circuitry. A value of 0 on RSL3-0 selects round/ select/limit register 0. A value of 1 selects round/select/limit register 1 and so on. RSL3-0 is latched on the
rising edge of CLK (see the round, select, and limit sections for a complete discussion). OED -- DOUT Output Enable When OED is LOW, DOUT15-0 is enabled for output. When OED is HIGH, DOUT15-0 is placed in a high-impedance state. OEC -- COUT Output Enable When OEC is LOW, COUT7-0 is enabled for output. When OEC is HIGH, COUT7-0 is placed in a highimpedance state.
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LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
parallel. This allows all the line buffers to be preloaded with data in the amount of time it normally takes to load a single line buffer. Odd and Even Field Filtering The LF3338 is capable of odd and even field filtering. Bit 2 of Configuration Register 1 enables the VB Data Input port required for odd and even field filtering. Bit 3 of the same configuration register enables the line buffer in the VB Data path. Line buffer length is set to the length written to Configuration Register 0. If line buffer parallel load is enabled and odd and even field filtering is enabled, the data for the VB line buffer comes from the VB Data Input port. Interleaved Data The LF3338 is capable of handling interleaved data. The number of data sets it can handle is determined by the number of data values contained in a video line. If the interleaved video line has 3076 data values or less, the LF3338 can handle it no matter how many data sets are interleaved together. Cascading A cascade port is provided to allow cascading of multiple devices for more filter taps (see Figure 5). COUT7-0 of one device should be connected to DIN7-0 of another device. As many LF3338s as desired may be cascaded together. However, the outputs of the LF3338s must be added together with external adders. The first line buffer on a cascaded device must have its length shortened by two delays. This is to account for the added delays of the input register on the device and the cascade output register from the previous LF3338. If Bit 0 of Configuration Register 3 is set to "1", the length of the first line buffer will be reduced by two. This will make its effective length the same as the other line buffers on the device. If Bit 0 of Configuration Register 3 is set to "0", the length of the first line buffer will be the same as the other line buffers. When cascading devices, the first LF3338 should have Bit 0 of Configuration Register
FUNCTIONAL DESCRIPTION Line Buffers The maximum delay length of each line buffer is 3076 cycles and the minimum is 4 cycles. Configuration Register 0 (CR0) determines the delay length of the line buffers. The line buffer length is equal to the value of CR0 plus 4. A value of 0 for CR0 sets the line buffer length to 4. A value of 3072 for CR0 sets the line buffer length to 3076. Any values for CR0 greater than 3072 are not valid. The line buffers have two modes of operation: delay mode and recirculate mode. Bit 0 of Configuration Register 1 determines which mode the line buffers are in. In delay mode, the data input to the line buffer is delayed by an amount determined by CR0. In recirculate mode, the output of the line buffer is routed back to the input of the line buffer allowing the line buffer contents to be read multiple times. Bit 1 of Configuration Register 1 allows the line buffers to be loaded in parallel. When Bit 1 is "1", the input register (DIN7-0) loads all seven line buffers in
FIGURE 5.
8 DIN
MULTIPLE LF3338S CASCADED TOGETHER
LF3338
LINE BUFFERS COUT DIN
LF3338
LINE BUFFERS COUT DIN
LF3338
LINE BUFFERS COUT DIN
LF3338
LINE BUFFERS
VERTICAL FILTER
VERTICAL FILTER
VERTICAL FILTER
VERTICAL FILTER
RSL CIRCUIT
RSL CIRCUIT
RSL CIRCUIT
RSL CIRCUIT
LF3347
25
25
RSL CIRCUIT
16 DATA OUT 29 TAP RESULT
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LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
programmable. This allows the filter's output to be rounded to any precision required. Since any 32-bit value may be programmed into the round registers, the device can support complex rounding algorithms as well as standard half-LSB rounding. RSL3-0 determines which of the sixteen round registers are used in the rounding operation. A value of 0 on RSL3-0 selects round register 0. A value of 1 selects round register 1 and so on. RSL3-0 may be changed every clock cycle if desired. This allows the rounding algorithm to be changed every clock cycle. This is useful when filtering interleaved data. If rounding is not desired, a round register should be loaded with 0 and selected as the register used for rounding. Round register loading is discussed in the LF Interface TM section. Output Select The word width of the filter output is 32 bits. However, only 16 bits may be sent to DOUT15-0. The select circuitry determines which 16 bits are passed (see Table 1). There are sixteen select registers which control the select circuitry. Each select register is 5 bits wide and userprogrammable. RSL3-0 determines which of the sixteen select registers are used in the select circuitry. Select register 0 is chosen by loading a 0 on RSL3-0. Select register 1 is chosen by loading a 1 on RSL3-0 and so on. RSL3-0 may be changed every clock cycle if desired. This allows the 16-bit window to be changed every clock cycle. This is useful when filtering interleaved data. Select register loading is discussed in the LF Interface TM section.
3 set to "0". Any LF3338s cascaded after the first LF3338 should have Bit 0 of Configuration Register 3 set to "1". When not cascading, Bit 0 of Configuration Register 3 should be set to "0". It is important to note that the first multiplier on all cascaded devices should not be used. This is because the first multiplier does not have a line buffer in front of it. The coefficient value sent to the first multiplier on a cascaded device should be "0". Rounding The filter output may be rounded by adding the contents of one of the sixteen round registers to the filter output (see Figure 4). Each round register is 32 bits wide and user-
FIGURE 6. COEFFICIENT BANK LOADING SEQUENCE
COEFFICIENT SET 1 COEFFICIENT SET 2 COEFFICIENT SET 3
CLK W1 LD W2 W3
CF11-0
ADDR1
COEF0
COEF7
ADDR2
COEF0
COEF7
ADDR3
COEF0
COEF7
W1: Coefficient Set 1 written to coefficient banks during this clock cycle. W2: Coefficient Set 2 written to coefficient banks during this clock cycle. W3: Coefficient Set 3 written to coefficient banks during this clock cycle.
FIGURE 7. CONFIGURATION/CONTROL REGISTER LOADING SEQUENCE
CONFIG REG SELECT REG ROUND REGISTER LIMIT REGISTER
CLK W1 LD W2 W3 W4
CF11-0
ADDR1
DATA1
ADDR2
DATA1
ADDR3
DATA1
DATA2
DATA3
DATA4
ADDR4
DATA1
DATA2
DATA3
DATA4
W1: Configuration Register loaded with new data on this rising clock edge. W2: Select Register loaded with new data on this rising clock edge. W3: Round Register loaded with new data on this rising clock edge. W4: Limit Register loaded with new data on this rising clock edge.
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LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
passed as the filter output. RSL3-0 may be changed every clock cycle if desired. This allows the limit range to be changed every clock cycle. This is useful when filtering interleaved data. When loading limit values into the device, the upper limit must be greater than the lower limit. Limit register loading is discussed in the LF Interface TM section. Coefficient Banks The coefficient banks store the coefficients which feed into the multipliers in the filter. There is a separate bank for each multiplier. Each bank can hold 256 12-bit coefficients. The banks are loaded using the LF InterfaceTM. Coefficient bank loading is discussed in the LF Interface TM section. Configuration and Control Registers The configuration registers determine how the LF3338 operates. Tables 2 through 5 show the formats of the four configuration registers. There are three types of control registers: round, select, and limit. There are sixteen round registers. Each round register is 32 bits wide. RSL3-0 determines which round register is used for rounding. There are sixteen select registers. Each select register is 5 bits wide. RSL3-0 determines which select register is used for the select circuitry. There are sixteen limit registers. Each limit register is 32 bits wide and stores both an upper and lower limit value. The lower limit is stored in bits 15-0 and the upper
Limiting An output limiting function is provided for the output of the filter. The limit registers determine the valid range of output values when limiting is enabled (Bit 0 in Configuration Register 2). There are sixteen 32-bit limit registers. RSL3-0 determines which limit register is used during the limit operation. A value of 0 on RSL3-0 selects limit register 0. A value of 1 selects limit register 1 and so on. Each limit register contains both an upper and lower limit value. If the value fed to the limiting circuitry is less than the lower limit, the lower limit value is passed as the filter output. If the value fed to the limiting circuitry is greater than the upper limit, the upper limit value is
FIGURE 8. COEFFICIENT BANK LOADING SEQUENCE WITH PAUSE IMPLEMENTATION
COEFFICIENT SET 1
CLK W1 PAUSE LD
CF11-0
ADDR1
COEF0
COEF1
COEF7
W1: Configuration Register loaded with new data on this rising clock edge.
FIGURE 9. CONFIGURATION AND SELECT REGISTER LOADING SEQUENCE WITH PAUSE IMPLEMENTATION
CONFIGURATION REGISTER SELECT REGISTER
CLK W1 PAUSE LD W2
CF11-0
ADDR1
DATA1
ADDR2
DATA1
W1: Configuration Register loaded with new data on this rising clock edge. W2: Select Register loaded with new data on this rising clock edge.
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DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
LF InterfaceTM The LF InterfaceTM is used to load data into the coefficient banks and configuration/control registers. LD is used to enable and disable the LF InterfaceTM. When LD goes LOW, the LF InterfaceTM is enabled for data input. The first value fed into the interface on CF11-0 is an address which determines what the interface is going to load. The three most
limit is stored in bits 31-16. RSL3-0 determines which limit register is used for limiting when limiting is enabled. Configuration and control register loading is discussed in the LF Interface TM section.
FIGURE 10. ROUND REGISTER LOADING SEQUENCE WITH PAUSE IMPLEMENTATION
ROUND REGISTER
CLK W1 PAUSE LD
CF11-0
ADDR1
DATA1
DATA2
DATA3
DATA4
W1: Round Register loaded with new data on this rising clock edge.
FIGURE 11. LIMIT REGISTER LOADING SEQUENCE WITH PAUSE IMPLEMENTATION
LIMIT REGISTER
CLK W1 PAUSE LD
CF11-0
ADDR1
DATA1
DATA2
DATA3
DATA4
W1: Limit Register loaded with new data on this rising clock edge.
TABLE 10.
COEFFICIENT BANK LOADING FORMAT
CF11 CF10 0 0 1 1 0 1 0 1 0 CF9 0 1 0 0 0 1 0 1 0 CF8 0 0 1 0 1 1 0 1 1 CF7 0 0 0 0 1 0 0 0 0 CF6 0 0 1 1 1 0 0 0 1 CF5 0 0 0 1 1 0 1 1 0 CF4 0 1 0 1 0 0 1 0 0 CF3 1 0 0 0 0 0 0 0 0 CF2 0 0 0 1 0 0 0 0 0 CF1 1 0 1 1 1 0 1 0 1 CF0 0 0 1 0 1 1 0 0 1 0 0 0 1 1 0 1 1 0
1st Word - Address 2nd Word - Bank 0 3rd Word - Bank 1 4th Word - Bank 2 5th Word - Bank 3 6th Word - Bank 4 7th Word - Bank 5 8th Word - Bank 6 9th Word - Bank 7
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DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
TABLE 6. CF11-9 DECODE
11 10 9 DESCRIPTION 0 0 0 1 1 0 0 1 0 1 0 1 1 1 1 Coefficient Banks Configuration Registers Select Registers Round Registers Limit Registers
significant bits (CF11-9) determine if the LF InterfaceTM will load coefficient banks or configuration/control registers (see Table 6). The nine least significant bits (CF8-0) are the address for whatever is to be loaded (see Tables 7 through 9). For example, to load address 15 of the coefficient banks, the first data value into the LF InterfaceTM should be 00FH. To load limit register 10, the first data value should be E0AH. The first address value should be loaded into the interface on the same clock cycle that latches the HIGH to LOW transition of LD (see Figures 6 and 7). The next value(s) loaded into the interface are the data value(s) which will be stored in the bank or register defined by the address value. When loading coefficient banks, the interface will expect eight values to be loaded into the device after the address value. The eight values are coefficients 0 through 7. When loading configuration or select registers, the interface will expect one value after the address value. When loading round or limit registers, the interface will expect four
TABLE 7. ROUND REGISTERS
REGISTER 0 1 ADDRESS (HEX) A00 A01
values after the address value. Figures 6 and 7 show the data loading sequences for the coefficient banks and configuration/control registers. PAUSE allows the user to effectively slow the rate of data loading through the LF InterfaceTM. When PAUSE is HIGH, the LF InterfaceTM is held until PAUSE is returned to a LOW. Figures 8 through 11 display the effects of PAUSE while leading coefficient and control data. Table 10 shows an example of loading data into the coefficient banks. The following data values are written into address 10 of coefficient banks 0 through 7: 210H, 543H, C76H, 9E3H, 701H, 832H, F20H, 143H. Table 11 shows an example of loading data into a
14 15
A0E A0F
TABLE 8. SELECT REGISTERS
REGISTER 0 1 ADDRESS (HEX) 600 601
14 15
60E 60F
TABLE 9. LIMIT REGISTERS
REGISTER 0 1 ADDRESS (HEX) E00 E01
14 15
E0E E0F
TABLE 11.
CONFIGURATION REGISTER LOADING FORMAT
CF11 CF10 0 0 CF9 1 0 CF8 0 0 CF7 0 0 CF6 0 0 CF5 0 0 CF4 0 0 CF3 0 0 CF2 0 0 CF1 1 1 CF0 0 1 0 0
1st Word - Address 2nd Word - Data
TABLE 12.
ROUND REGISTER LOADING FORMAT
CF11 CF10 0 R R R R CF9 1 R R R R CF8 0 R R R R CF7 0 1 1 1 0** CF6 0 0 1 0 1 CF5 0 1 1 0 1 CF4 0 0 1 0 1 CF3 1 0 0 0 0 CF2 1 0 1 0 1 CF1 0 1 0 1 1 CF0 0 0* 0 1 0 1 R R R R
1st Word - Address 2nd Word - Data 3rd Word - Data 4th Word - Data 5th Word - Data
R = Reserved. Must be set to "0". * This bit represents the LSB of the Round Register. ** This bit represents the MSB of the Round Register.
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DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
83 MHz clock rate, all 256 coefficient sets can be updated in less than 27.7 s, which is well within vertical blanking time. It takes 5S clock cycles to load S round or limit registers. Therefore, it takes 160 clock cycles to update all round and limit registers. Assuming an 83 MHz clock rate, all round/limit registers can be updated in 1.92 s. The coefficient banks and configuration/control registers are not loaded with data until all data values for the specified address are loaded into the LF InterfaceTM. In other words, the coefficient banks are not written to until all eight coefficients have been loaded into the LF InterfaceTM. A round register is not written to until all four data values are loaded. After the last data value is loaded, the interface will expect a new address value on the next clock cycle. After the next address value is loaded, data loading will begin again as previously discussed. As long as data is loaded into the interface, LD must remain LOW. After all desired coefficient banks and configuration/control registers are loaded with data, the LF InterfaceTM must be disabled. This is done by setting LD HIGH on the clock cycle after the clock cycle which latches the last data value. It is important that the LF InterfaceTM remain disabled when not loading data into it.
configuration register. Data value 003H is written into Configuration Register 2. Table 12 shows an example of loading data into a round register. Data value 7683F4A2H is written into round register 12. Table 13 shows an example of loading data into a select register. Data value 00FH is loaded into select register 2. Table 14 shows an example of loading data into limit register 7. Data value 3B60H is loaded as the lower limit and 72A4H is loaded as the upper limit. It takes 9S clock cycles to load S coefficient sets into the device. Therefore, it takes 2304 clock cycles to load all 256 coefficient sets. Assuming an
TABLE 13. SELECT REGISTER LOADING FORMAT
CF11 1st Word - Address 2nd Word - Data 0 0 CF10 1 0 CF9 1 0 CF8 0 0 CF7 0 0 CF6 0 0 CF5 0 0 CF4 0 0 CF3 0 1 CF2 0 1 CF1 1 1 CF0 0 1
TABLE 14. LIMIT REGISTER LOADING FORMAT
CF11 1st Word - Address 2nd Word - Data 3rd Word - Data 4th Word - Data 5th Word - Data 1 R R R R CF10 1 R R R R CF9 1 R R R R CF8 0 R R R R CF7 0 0 0* 1 0** CF6 0 1 0 0 1 CF5 0 1 1 1 1 CF4 0 0 1 0 1 CF3 0 0 1 0 0 CF2 1 0 0 1 0 CF1 1 0 1 0 1 CF0 1 0 1 0 0
R = Reserved. Must be set to "0". * This bit represents the MSB of the Lower Limit. ** This bit represents the MSB of the Upper Limit.
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DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... -65C to +150C Operating ambient temperature ........................................................................................... -55C to +125C VCC supply voltage with respect to ground ............................................................................ -0.5 V to +4.5 V Input signal with respect to ground .......................................................................................... -0.5 V to 5.5 V Signal applied to high impedance output ................................................................................. -0.5 V to 5.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA ESD Classification (MIL-STD-883E METHOD 3015.7) ...................................................................... Class 3
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0C to +70C -55C to +125C Supply Voltage 3.00 V VCC 3.60 V 3.00 V VCC 3.60 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 CIN COUT Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent Input Capacitance Output Capacitance
(Note 3)
Test Condition VCC = Min., IOH = -4 mA VCC = Min., IOL = 8.0 mA
Min 2.4
Typ
Max
Unit V
0.4 2.0 0.0 5.5 0.8 10 10 120 1 10 10
V V V A A mA mA pF pF
Ground VIN VCC (Note 12) Ground VOUT VCC (Note 12)
(Notes 5, 6) (Note 7)
TA = 25C, f = 1 MHz TA = 25C, f = 1 MHz
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DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0C to +70C) Notes 9, 10 (ns)
LF3338- 12
Symbol Parameter Min Max
tCYC tPW tS tH tDD tDC tDIS tENA
Clock Cycle Time Clock Pulse Width Input Setup Time Input Hold Time Data Output Delay Cascade Data Output Delay Three-State Output Disable Delay (Note 11) Three-State Output Enable Delay (Note 11)
12 5 4 0.5 8 9 10 10
SWITCHING WAVEFORMS:
1 CLK tS DIN7-0
DINN
DATA I/O
2 3 tPW
DINN+1
4
5
6
7
tH
tPW tCYC
CA7-0
CAN
CAN+1
VB7-0 CONTROLS (Except OE) OE
VBN
VBN+1
tDIS DOUT15-0
tENA
HIGH IMPEDANCE DOUTN-1
tDD
DOUTN
tDC COUT7-0
HIGH IMPEDANCE COUTN-1 COUTN
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DEVICES INCORPORATED
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LF3338- 12
COMMERCIAL OPERATING RANGE (0C to +70C) Notes 9, 10 (ns) VALUES NOT VALID
Symbol
Parameter
Min
Max
tCFS tCFH tLS tLH tPS tPH
Coefficient Input Setup Time Coefficient Input Hold Time Load Setup Time Load Hold Time PAUSE Setup Time PAUSE Hold Time
5 0 4 0 4 0.5
SWITCHING WAVEFORMS:
1 CLK tLS LD tPW
LF INTERFACETM
2 tPW tCYC tPS tPH 3 4 tLH 5 6
PAUSE tCFS CF11-0 tCFH
CF0 CF1 CF2
ADDRESS
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DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
NOTES
9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of IOH and IOL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Never- used. Parasitic capacitance is 30 pF theless, conventional precautions minimum, and may be distributed. should be observed during storage, handling, and use of these circuits in This device has high-speed outputs caorder to avoid exposure to excessive pable of large instantaneous current electrical stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping testing of this device. The following of transient undershoot. Input levels measures are recommended: below ground will be clamped beginning at -0.6 V. The device can with- a. A 0.1 F ceramic capacitor should be stand indefinite operation with inputs installed between VCC and Ground or outputs in the range of -0.5 V to leads as close to the Device Under Test +5.5 V. Device operation will not be (DUT) as possible. Similar capacitors adversely affected, however, input cur- should be installed between device VCC rent levels will be well in excess of 100 and the tester common, and device mA. ground and tester common. 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT socket or contactor fingers. anteed as specified. 5. Supply current for a given application can be accurately approximated by: NCV2 F c. Input voltages on a test fixture should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT input levels relative to the DUT ground pin. 10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the 200mV level from the measured steady-state output voltage with 10mA loads. The balancing voltage, VTH, is set at 3.0 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1 IOL CL IOH VTH
DUT
FIGURE B. THRESHOLD LEVELS
tENA OE
Z 0
1.5 V 1.5 V 1.5 V
tDIS
3.0V Vth VOL*
0.2 V
0 1
Z Z
1.5 V
VOH*
0.2 V
Z
1
0V Vth VOL* Measured VOL with IOH = -10mA and IOL = 10mA VOH* Measured VOH with IOH = -10mA and IOL = 10mA
4
where N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with outputs changing every cycle and no load, at a 40 MHz clock rate. 7. Tested with all inputs within 0.1 V of VCC or Ground, no load. 8. These parameters are guaranteed but not 100% tested.
Video Imaging Products
14
04/06/1999-LDS.3338-B
LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
ORDERING INFORMATION
GND VCC DOUT15 DOUT14 DOUT13 DOUT12 DOUT11 DOUT10 DOUT9 DOUT8 DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 VCC GND 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100-pin
GND ACC RSL0 RSL1 RSL2 RSL3 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CEN VCC GND SHEN GND GND GND GND DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Top View
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
OED VCC CF0 CF1 CF2 CF3 CF4 CF5 CF6 CF7 CF8 CF9 CF10 CF11 LD PAUSE VCC GND NC NC NC NC COUT0 COUT1 COUT2 COUT3 COUT4 COUT5 COUT6 COUT7
Speed
0C to +70C -- COMMERCIAL SCREENING
12 ns LF3338QC12
25 18 15 12
ns ns ns ns
-55C to +125C -- COMMERCIAL SCREENING
25 18 15 12
ns ns ns ns
-55C to +125C -- MIL-STD-883 COMPLIANT
GND VCC GND GND GND GND VB0 VB1 VCC CLK GND VB2 VB3 VB4 VB5 VB6 VB7 OEC VCC GND
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Plastic Quad Flatpack (Q2)
Video Imaging Products
15
04/06/1999-LDS.3338-B

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