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www.fairchildsemi.com FAN8040 4-Channel Motor Driver Features * 4-channel Balanced Transformerless (BTL) Driver * 3-channels PWM input direct-coupled type include internal filters. * Separated power supply voltages (PVCC1: CH1 and CH2, PVCC2: CH3 and CH4) * Built-in input pin selection function of channel 4 * Built-in OP-amplifier * Built-in Power Save function * Built-in Thermal Shutdown Circuit (TSD) * Operating ranges: 4.5~ 13.2V Description The FAN8040G3 is a monolithic integrated circuit, suitable for 4-channel motor driver which drives tracking actuator, focus actuator, sled motor and spindle motor of compack disk player system. 28-SSOPH-375-SG2 Typical Applications * Compact Disk Player (CDP) * Video Compact Disk Player (VCD) * Other Compact Disk Media Ordering Information Device FAN8040G3 FAN8040G3X Package 28-SSOPH-375SG2 28-SSOPH-375SG2 Operating Temp. -40C ~ +85C -40C ~ +85C Rev. 1.0.0 (c)2004 Fairchild Semiconductor Corporation 2 1 27 2 3 4 5 6 7 25 24 23 22 26 OPOUT OUTVREF CH4CAPA CH4IN CH3FIN CH3RIN OPIN- FAN8040 28 VDD OPIN+ SW CH1FIN CH1RIN CH2FIN CH2RIN Pin Assignments FIN FIN 8 9 10 PVCC1 CH2OUTR CH2OUTF CH1OUTR CH1OUTF VREFIN GND 21 GND PS FAN8040G3 11 12 13 14 20 19 18 17 16 15 PVCC2 CH3OUTR CH3OUTF CH4OUTF CH4OUTR FAN8040 Pin Definitions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name OPINOPIN+ SW CH1FIN CH1RIN CH2FIN CH2RIN GND VREFIN PVCC1 CH2OUTR CH2OUTF CH1OUTR CH1OUTF CH4OUTR CH4OUTF CH3OUTF CH3OUTR PVCC2 PS GND CH3RIN CH3FIN CH4IN CH4CAPA OUTVREF OPOUT VDD I/O I I I I I I I I O O O O O O O O I I I I I I O Pin Function Description OP-amplifier negative input OP-amplifier positive input channel 4 input change switch input Channel 1 PWM forward input Channel 1 PWM reverse input Channel 2 PWM forward input Channel 2 PWM reverse input Ground 1 Internal reference voltage input terminal Power supply voltage for channel 1 and channel 2 Channel 2 reverse output Channel 2 forward output Channel 1 reverse output Channel 1 forward output Channel 4 reverse output Channel 4 forward output Channel 3 forward output Channel 3 reverse output Power supply voltage for channel 3 and channel 4 Power save signal input Ground 2 Channel 3 PWM reverse input Channel3 PWM forward input Channel 4 input Channel 4 external capacitor connection terminal Channel 4 external reference voltage input terminal Op-amplifier output Predriver power supply voltage 3 FAN8040 Internal Block Diagram CH3OUTR CH4CAPA CH3FIN 28 27 26 50K 25 10K 24 100K 23 F 22 R F VDD FIN 21 Bias Circuit 25pF 20 50K 19 18 D 17 D CH4OUTF OPOUT CH3RIN VDD PS 16 D 15 D PS CNTL VDD INTERFACE 100K PVCC2 (CH3,4) R 50K 100K 19K 10K TSD VDD F INTERFACE R VDD 100K 25pF PVCC1 5.3K PVCC2 50K 50K 50K PS CNTL 50K F R INTERFACE F R 100K 25pF PVCC1 (CH1,2) F R D D D 1 OPIN- 2 OPIN+ 3 SW 4 CH1FIN 5 CH1RIN 6 CH2FIN 7 CH2RIN CH2OUTR VREFIN PVCC1 CH1OUTR D : Drive Buffer SW : H--> ON, L --> OFF 4 CH2OUTF CH1OUTF FIN 8 GND 9 10 11 12 13 14 CH4OUTR D OUTVREF CH3OUTF PVCC2 CH4IN GND FAN8040 Equivalent Circuits Driver Forward Input Driver Reverse Input CH1, CH2 and CH3 CH1, CH2 and CH3 4 6 23 17K 5 7 22 17K Driver Output Internal Reference Voltage 30K 50K 11 12 13 30K 15 16 9 50K 17 18 14 PS Input CH4 SW Input 20 50K 50K 3 2K 50K 5 FAN8040 Equivalent Circuits (Continued) OP- Amplifier Input OP- Amplifier Output 2K 2K 27 1 2K 2K 2 External Reference Voltage Input 100K 100K 24 100K 50K 26 50K 10K 25 100K 6 FAN8040 Absolute Maximum Ratings (Ta = 25C) Parameter Supply Voltage Predriver Supply Voltage Power Dissipation Operating Temperature Storage Temperature Symbol PVCC1, 2 VDD PD TOPR TSTG Value 15 15 2.5note -40 ~ +85 -55 ~ +150 Unit V V W C C Note: 1. When mounted on a 76.2mm x 114mm x 1.57mm PCB (Phenolic resin material). 2. Power dissipation reduces 16.6mW/C for using above Ta = 25C 3. Do not exceed PD and SOA (Safe operating area) Power Dissipation Curve PD [mW] 3000 2500 2000 1500 1000 500 0 0 25 50 75 100 125 150 175 200 SOA Ambient temperature, Ta[C] Recommended Operating Condition (Ta = 25C) Parameter Operating Supply Voltage Predriver Supply Voltage Symbol PVCC1, 2 VDD Value 4.5 ~ 13.2 4.5 ~ 13.2 Unit V V 7 FAN8040 Electrical Characteristics (Ta = 25C) (Ta=25C, VDD=PVCC1=PVCC2=8V, RL=8, f=1kHz, unless otherwise specified) Parameter Quiescent Circuit Current1 Internal Reference Input Voltage Quiescent Circuit Current2 Power Save Off Voltage Power Save On Voltage Input High Level Voltage Input Low Level Voltage Input High Level Current Input Low Level Current (Forward) Input Low Level Current (Reverse) Output Offset Voltage Maximum Output Voltage Ripple Rejection Ratio Input Bias Current Output Offset Voltage Maximum Output Voltage Closed-loop Voltage Gain Ripple Rejection Ratio (Note2) (Note2) (Note1) Symbol IQ VREF IPS VPSOFF VPSON VIH VIL IIH IILF IILR VOO VOM RR IB VOO4 VOM GVC RR VIHSW VILSW IIHSW IILSW VOFOP IBOP VOHOP VOLOP ISINK ISOURCE GVO SR Conditions Under no-load At Power Save On Min. 3.40 2.0 2.4 -0.3 Typ. 17.0 3.70 10 310 5.0 70 10 5.4 11.3 70 60 0 10 13.0 9.0 65 0.5 Max. 25.0 4.0 100 0.5 VCC 0.5 450 0 0 30 5.6 300 50 13.3 VCC 0.5 90 10 +5 300 0.2 - Unit mA V uA V V V V uA uA uA mV V dB nA mV V dB dB V V uA uA mA nA V V mA mA dB V/us BTL DRIVER PART (CH1, CH2 and CH3) VF=VR=5V VF=0V VR=0V VF=5V,VR=0V VRR=100mVrms, 100Hz 170 -10 -50 -30 4.4 - SPINDLE MOTOR DRIVER (CH4) CH4IN=OUTVREF CH4IN=4V VRR=100mVrms, 100Hz -50 4.8 9.3 2.0 -0.3 VSW=3.5V VSW=0V -10 -5 7.0 7.0 2.0 VIN=60dBV, 1KHz f=50KHz,2VPP(Squre) - ANALOG SWITCH INPUT Input High Level Voltage Input Low Level Voltage Input High Level Current Input Low Level Current OP-AMPLIFIER Offset Voltage Input Bias Current Output High Level Volatage Output Low Level Volatage Output Sink Current Output Source Current Open-loop Voltage Slew Rate (Note2) Gain(Note2) Note : 1. when the PS(pin20) is low level (under 0.5V) the bias circuit is disabled, so that the whole circuits are disabled. 2. Guranteed Design Value 8 FAN8040 Application Information 1. Power Save Function * Power save function is also performed at PS (pin20). The truth table is as follows: VDD SW (pin3) Input L H Function CAPA(pin25) OFF CAPA(pin25) ON Input L H PS (pin20) Function Power Save ON Power Save OFF 20 PS CNTL Bias Circuit Figure 1. Truth table of Gain selection and Mute Function * When the PS (pin 20) is hige level (above 2V), the bias circuit is enable. On the other hand, when the PS(pin20) is low level (under 0.5V), the bias circuit is disabled. * When the CAPA(pin3) is low level, the CAPA (pin25) is opened in Figure. 4. 2. TSD (Thermal Shutdown) Function * When the chip temperature rises above 175C, then the 4-channels BTL driver output circuit will be muted. The TSD circuit has the hysteresis temperature of 25C. 4. Balanced Transformerless(BTL) Driver (CH1, CH2 and CH3) * CH1, CH2 and CH3 drive parts are composed of internal filter, V-I converter and output power amplifiers. PVCC I1 Buffer1 R1=100K Buffer2 C1=25 I2 FWD INTERFACE F R S1 OUT1 REV S2 A VREF OUT2 Figure 2. Schematic of BTL Driver (CH1, CH2 and CH3) F L L H H R L H L H S1 OFF OFF ON ON S2 OFF ON OFF ON H : above 2.4 [V] L : under 0.5 [V] Table 1. Truth table of internal switches operation 9 FAN8040 * Internal primary filter is composed of sourcing/sinking current source of 25uA and forward/reverse controlled switches. * It converts "FWD/REV" digital signals to analog signal as shown Figure. 2. 1V/usec FWD Input REV 5V 0V VREF OUTF OUTR Output 0V 0V 5V FWD Input REV 0V 0V 0V OUTF Output VREF OUTR Figure 3. Operartion waveforms of BTL Driver (CH1, CH2 and CH3) * If the forward input signal is high level (avobe 2.4V) and reverse input signal is low level (under 0.5V), then the forward current source switch S1and reverse current source switch S2 become turn-on and turn-off, respectively. * This causes the internal capacitor, C1, to be charged with sourcing current source of 25uA and consequently the voltage of the filter output, VA, increases with the internal time constant of 2.5usec. * VA = I1 x R1 2.5[V ], * The time constant is (Or reverse input : -2.5[V ] ) R x C = 2.5[u sec] Where, R is 100 [] and C is 25[pF]. * The output voltages of power amplifers, VOUTF and VOUTR, are given as: * VOUTF = VREF + VA VOUTR = VREF - VA [V ] [V ] 10 FAN8040 5. Channel 4 Driver (Spindle Motor Driver) * The channel 4 driver is composed of input amplifer with input selection switch, V-I converter and output power amplifiers. * The voltage, VREF, is the external reference voltage given by the bias voltage of the pin 26 in Figure. 4. * The input signal, VIN, through the CH4IN (pin24) is amplified by 100K/100K times and then fed to the next amplifier. And the amplified voltage is amplified by R2/R1 times and then the fed to the level shift circuit. * Level shifit produces the current due to the difference between the input signal and the internal power reference (PVCC/2). The current produced as + I and - I is fed into the driver buffer. * If it is desired to change the gain, then the CH4CAPA (pin25) can be used. It is controlld by the SW (pin3) input signal. * When the SW (pin3) is high level, then the input voltage,VIN, applied to the CH4CAPA (pin25). 100K 100K R2 R1 + I D 24 R1 Servo Output C1 C2 16 25 10K Level Shift PVCC - I 26 VREF VREF 50K D 15 50K 50K VREF 3 Figure 4. Channel 4 Spindle Driver 11 FAN8040 Typical Performance Characteristics VDD vs IQ1 12 11.5 11 PVCC1 vs IPVCC1 0. 6 0. 55 0. 5 IPVCC1[mA] 0. 45 0. 4 0. 35 0. 3 0. 25 0. 2 IQ1[mA] 10.5 10 9.5 9 8.5 8 5 6 7 8 9 10 11 12 13 14 VDD[V] 5 6 7 8 9 10 11 12 13 14 PVCC1[V] PVCC2 vs IPVCC2 0. 6 0. 55 0. 5 IPVCC1[mA] GCV[dB] 0. 45 0. 4 0. 35 0. 3 0. 25 0. 2 5 6 7 8 9 10 11 12 13 14 PVCC2[V] 13 12. 5 12 11. 5 11 10. 5 10 9. 5 5 6 7 VDD vs GCV 8 9 10 11 12 13 14 V DD[V ] Temperature vs IQ1 15 14 13 11 10 9 8 7 6 5 -40 -20 0 20 40 60 80 100 Temperature vs IPVCC1 1 0. 9 0. 8 0. 7 0. 6 0. 5 0. 4 0. 3 0. 2 0. 1 0 -40 IPVCC1[mA] 12 IQ1[mA] -20 0 20 40 60 80 100 Temp [C] Temp [C] 12 FAN8040 Temperatur vs IPVCC2 1 0. 9 0. 8 0. 7 0. 6 0. 5 0. 4 0. 3 0. 2 0. 1 0 -40 6 5. 8 5. 6 5. 4 5. 2 5 4. 8 4. 6 4. 4 4. 2 4 -40 Temperature vs VOM1AB -20 0 20 40 60 80 100 VOM1AB[V] IPVC2[mA] -20 0 20 40 60 80 100 Tem [C] p Tem [C] p Temperature vs VOM 2AB 6 5. 8 5. 6 5. 4 5. 2 5 4. 8 4. 6 4. 4 4. 2 4 -40 6 5. 8 5. 6 5. 4 5. 2 5 4. 8 4. 6 4. 4 4. 2 4 -40 Temperature vs VOM3AB VOM3AB[V] VOM2AB[V -20 0 20 40 60 80 100 -20 0 20 40 60 80 100 Tem p[C] Temp[C] Temperature vs VOM4AB 6 5. 8 5. 6 5. 4 5. 2 5 4. 8 4. 6 4. 4 4. 2 4 -40 Temperature vs GCV1 13 12. 5 12 GCV1[dB] 11. 5 11 10. 5 10 9. 5 9 -40 VOM4AB[V] -20 0 20 40 60 80 100 -20 0 20 40 60 80 100 Temp[C] Temp[C] 13 FAN8040 Temperature vs ISOURCE 10 9 8 7 6 5 4 3 2 1 0 -40 40 38 36 34 32 30 28 26 24 22 20 -40 Temperature vs ISINK ISOURCE[mA] -20 0 20 40 60 80 100 ISINK[mA] -20 0 20 40 60 80 100 Temp[C] Temp[C] 14 SLED MOTOR SPINDLE MOTOR PVCC 0.1uF M M 0.47uF VDD 0.1uF 28 20 D 50K PVCC2 (CH3,4) D 50K VDD F INTERFACE 100K 100K 25pF R 50K 10K 100K 27 26 25 24 F PVCC 23 22 21 Bias Circuit FIN 19 18 17 16 D 15 D Typical Application Circuits Power Save R SLED TSD PVCC F 100K 25pF INTERFACE R PVCC VREF FORWARD 19K 10K REVERSE PVCC 5.3K 50K 50K 50K 50K BIAS SPINDLE 1.75V F F INTERFACE R PVCC FOCUS H = ON L = OFF 82 15 FORWARD REVERSE TRACKING F R FORWARD REVERSE Digital Servo R 100K 25pF PVCC1 (CH1,2) D D D D 1 2 3 4 300pF 5 6 7 FIN 8 9 10 11 12 13 14 FOCUS COIL TRACKING COIL 0.1uF 0.1uF PVCC FAN8040 15 FAN8040 Mechanical Dimensions(Unit : mm) Package Dimensions 28-SSOPH-375SG2 16 FAN8040 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 7/27/04 0.0m 001 Stock#DSxxxxxxxx 2004 Fairchild Semiconductor Corporation 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. |
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