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| K4J55323QG 256M GDDR3 SDRAM 256Mbit GDDR3 SDRAM Revision 1.1 November 2005 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1 of 53 Rev. 1.1 November 2005 K4J55323QG Revision History Revision 0.0 0.1 Month February March Year 2005 2005 - Target Spec History 256M GDDR3 SDRAM - Changed EMRS table for Driver Impedance control. - Typo corrected. - Added clock frequency change sequence on page 18 and IBIS spec on page 19~21 - Reduced Cin min. value on page 54. - Added note for RFM pin on page 4. - Modified input functional description for CK/CK and Vref on page 5. - Removed -BC10/11 from the spec. Accordingly, CL12~15 become "reserved" in MRS table. - Modified note description for RMF on page 4. - Modified input functional description for Mirror function on page 5. - Modified note description for the Write Latency on page 55. - Clarify RMF description on page 4,5 to avoid confusion in case of using same board for both 512Mb and 256Mb GDDR3. - Added note description for Boundary scan function on page 22,23. (one RFM ball in the scan oder will be read as a logic "0") - Typo corrected. - Finalized DC characteristics and IBIS specification - Changed tRFC of -BC16 from 33tCK to 31tCK effective date code with WW0543 0.2 March 2005 0.3 April 2005 0.4 May 2005 1.0 1.1 June November 2005 2005 2 of 53 Rev. 1.1 November 2005 K4J55323QG 256M GDDR3 SDRAM 2M x 32Bit x 4 Banks Graphic Double Data Rate 3 Synchronous DRAM with Uni-directional Data Strobe 1.0 FEATURES * * * * * * * * * * * * * * 1.8V + 0.1V power supply for device operation 1.8V + 0.1V power supply for I/O interface On-Die Termination (ODT) Output Driver Strength adjustment by EMRS Calibrated output drive 1.8V Pseudo Open drain compatible inputs/outputs 4 internal banks for concurrent operation Differential clock inputs (CK and CK) Commands entered on each positive CK edge CAS latency : 4, 5, 6, 7, 8, 9, 10, 11 (clock) Additive latency (AL): 0 and 1 (clock) Programmable Burst length : 4 and 8 Programmable Write latency : 1, 2, 3, 4, 5, 6 and 7 (clock) Single ended READ strobe (RDQS) per byte * * * * * * * * * * * * * Single ended WRITE strobe (WDQS) per byte RDQS edge-aligned with data for READs WDQS center-aligned with data for WRITEs Data Mask(DM) for masking WRITE data Auto & Self refresh modes Auto Precharge option 32ms, auto refresh (4K cycle) 136 Ball FBGA Maximum clock frequency up to 800MHz Maximum data rate up to 1.6Gbps/pin DLL for outputs Boundary scan function with SEN pin Mirror function with MF pin 2.0 ORDERING INFORMATION Part Number K4J55323QG-BC12 K4J55323QG-BC14 K4J55323QG-BC16 K4J55323QG-BC20 Max Freq. 800MHz 700MHz 600MHz 500MHz Max Data Rate 1.6Gbps/pin 1.4Gbps/pin 1.2Gbps/pin 1.0Gbps/pin Pseudo Open Drain_18 136 Ball FBGA Interface Package K4J55323QC-AC** is leaded package part number 3.0 GENERAL DESCRIPTION FOR 2M x 32Bit x 4 Bank GDDR3 SDRAM The K4J55323QG is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 6.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, and programmable latencies allow the device to be useful for a variety of high performance memory system applications. 3 of 53 Rev. 1.1 November 2005 K4J55323QG 4.0 PIN CONFIGURATION Normal Package (Top View) 1 A B C D E F G H J K L M N P R T V VDDQ VSSQ VDDQ VSSQ VDDQ VDD VSS VREF VSSA VDDA VSS VDD VDDQ VSSQ VDDQ VSSQ VDDQ 2 VDD DQ0 DQ2 WDQS0 DQ4 DQ6 VSSQ A1 RFU1 A10 VSSQ DQ24 DQ26 WDQS3 DQ28 DQ30 VDD 3 VSS DQ1 DQ3 RDQS0 DM0 DQ5 DQ7 RAS RFU2 A2 DQ25 DQ27 DM3 RDQS3 DQ29 DQ31 VSS 4 ZQ VSSQ VDDQ VSSQ VDDQ CAS BA0 CKE VDDQ A0 A11 A3 VDDQ VSSQ VDDQ VSSQ SEN 5 6 7 8 9 MF VSSQ VDDQ VSSQ VDDQ CS BA1 WE VDDQ A4 A7 A9 VDDQ VSSQ VDDQ VSSQ RESET 256M GDDR3 SDRAM 10 VSS DQ9 DQ11 RDQS1 DM1 DQ13 DQ15 RFM CK A6 DQ17 DQ19 DM2 RDQS2 DQ21 DQ23 VSS 11 VDD DQ8 DQ10 WDQS1 DQ12 DQ14 VSSQ A5 CK A8/AP VSSQ DQ16 DQ18 WDQS2 DQ20 DQ22 VDD 12 VDDQ VSSQ VDDQ VSSQ VDDQ VDD VSS VREF VSSA VDDA VSS VDD VDDQ VSSQ VDDQ VSSQ VDDQ Note : 1. RFU1 is reserved for future use 2. RFU2 is reserved for future use 3. RFM : When the MF ball is tied LOW, RFM(H10) receiver is disabled and it recommended to be driven to a static LOW state, however, either static HIGH or floating state on this pin will not cause any problem for the DRAM. When the MF ball is tied HIGH, RAS(H3) becomes RFM due to mirror function and the receiver is disabled. It recommended to be driven to a static LOW state, however, either static HIGH or floating state on this pin will not cause any problem for the DRAM Please refer to Mirror Function Signal Mapping table at page 6. 4 of 53 Rev. 1.1 November 2005 K4J55323QG 5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol CK, CK Type Input Function 256M GDDR3 SDRAM Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). CK, CK should be maintained stable, except self-refresh mode Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of clock. Although DM pins are input only, the DM loading matches the DQ and WDQS loading. Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A8 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A8 LOW) or all banks (A8 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1,BA2. The address inputs also provide the op-code during Mode Register Set commands. Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7, CA9 . Column address CA8 is used for auto precharge. Data Input/ Output: Bi-directional data bus. READ Data Strobe: Output with read data. RDQS is edge-aligned with read data. WRITE Data Strobe: Input with write data. WDQS is center-aligned to the inout data. No Connect: No internal electrical connection is present. CKE Input CS RAS, CAS, WE DM0 ~DM3 BA0,BA1 Input Input Input Input A0 ~ A11 Input DQ0 ~ DQ31 RDQS0 ~ RDQS3 WDQS0 ~ WDQS3 NC/RFU VDDQ VSSQ VDD VSS VDDA VSSA VREF MF ZQ RES SEN RFM Input/ Output Output Input Supply Supply Supply Supply Supply Supply Supply Input Input Input Input DQ Power Supply DQ Ground Power Supply Ground DLL Power Supply DLL Ground Reference voltage: 0.7*VDDQ , 2 Pins : (H12) for Data input , (H1) for CMD and ADDRESS Mirror Function for clamshell mounting of DRAMs. VDDQ CMOS input. Reset pin: RESET pin is a VDDQ CMOS input Scan enable : Must tie to the ground in case not in use. VDDQ CMOS input. Reserved for Mirror Function : When the MF ball is tied low, RFM(H10) is recommended to be driven to logic low state. When the MF ball is tied high, RAS(H3) switch to RFM and is recommended to be driven to logic low state Reference Resistor connection pin for On-die termination. 5 of 53 Rev. 1.1 November 2005 K4J55323QG 6.0 BLOCK DIAGRAM (2Mbit x 32I/O x 4 Bank) WDQS 256M GDDR3 SDRAM Input Buffer 32 Input Buffer I/O Control LWE LDMi Bank Select Data Input Register Serial to parallel 128 2M x 32 Output Buffer 4-bit prefetch Sense AMP Refresh Counter Row Buffer Row Decoder 2M x 32 2M x 32 2M x 32 128 32 x32 DQi Address Register iCK ADDR Column Decoder LCBR LRAS Col. Buffer Latency & Burst Length Strobe Gen. RDQS LCKE Programming Register LRAS LCBR LWE LCAS LWCBR Output DLL CK,CK LDMi Timing Register iCK CKE CS RAS CAS WE DMi * iCK : internal clock 6 of 53 Rev. 1.1 November 2005 K4J55323QG 7.0 FUNCTIONAL DESCRIPTION 7.1 Simplified State Diagram Power Applied 256M GDDR3 SDRAM Power On Precharge PREALL Self Refresh REFS REFSX MRS EMRS MRS Idle REFA Auto Refresh CKEH CKEL Active Power Down CKEH CKEL ACT Precharge Power Down Row Active Write Write A Write Write Read A Read Read Read Write A Read A PRE Read A Write A PRE PRE Read A PRE Precharge PREALL Automatic Sequence Command Sequence PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh CKEL = Enter Power Down CKEH = Exit Power Down ACT = Active Write A = Write with Autoprecharge Read A = Read with Autoprecharge PRE = Precharge 7 of 53 Rev. 1.1 November 2005 K4J55323QG 7.2 INITIALIZATION 256M GDDR3 SDRAM GDDR3 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. 1. Apply power and keep CKE/RESET at low state ( All other inputs may be undefined) - Apply VDD and VDDQ simultaneously - Apply VDDQ before Vref. ( Inputs are not recognized as valid until after VREF is applied ) 2. Required minimum 100us for the stable power before RESET pin transition to HIGH - Upon power-up the address/command active termination value will automatically be set based off the state of RESET and CKE. - On the rising edge of RESET the CKE pin is latched to determine the address and command bus termination value. If CKE is sampled at a zero the address termination is set to 1/2 of ZQ. If CKE is sampled at a one the address termination is set to ZQ. - RESET must be maintained at a logic LOW level and CS at a logic high value during power-up to ensure that the DQ outputs will be in a High-Z state, all active terminators off, and all DLLs off. 3. Minimum 200us delay required prior to applying any executable command after stable power and clock. 4. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, then RESET and CKE should be brought to HIGH, 5. Issue a PRECHARGE ALL command following after NOP command. 6. Issue a EMRS command (BA1BA0="01") to enable the DLL. 7. Issue MRS command (BA0BA1 = "00") to reset the DLL and to program the operating parameters. 20K clock cycles are required between the DLL to lock. 8. Issue a PRECHARGE ALL command 9 . Issue at least two AUTO refresh command to update the driver impedance and calibrate the output drivers. Following these requirements, the GDDR3 SDRAM is ready for normal operation. VDDQ VDD VREF T0 CK CK RES t T1 Ta0 Tb0 Tc0 Td0 Te0 Tf0 t CH tCL ATS t ATH t IS t IH CKE CKE COMMAND t IS t IH NOP PRE LMR LMR PRE AR AR ACT DM t IS tIH CODE A0-A7, A9-A11 A8 t CODE RA ALL BANKS t IS t IH ALL BANKS CODE t CODE IS t RA IS t IH t IS t IH IH BA0, BA1 RDQS WDQS DQ T = 200us T=10ns Power-up: VDD and CK stable Precharge All Banks tRP High High High BAO=H, BA1 =L BAO=L, BA1 =L BA tMRD Load Mode Register DLL Reset tMRD Precharge All Banks tRP 20K 1st Auto Refresh tRFC 2nd Auto Refresh tRFC Load Extended Mode Register 8 of 53 Rev. 1.1 November 2005 K4J55323QG 7.3 MODE REGISTER SET(MRS) 256M GDDR3 SDRAM The mode register stores the data for controlling the various operating modes of GDDR3 SDRAM. It programs CAS latency, addressing mode, test mode and various vendor specific options to make GDDR3 SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for the proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE (The GDDR3 SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum clock cycles specified as tMRD are required to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The Burst length uses A0 ~ A1. CAS latency (read latency from column address) uses A2, A6 ~ A4. A7 is used for test mode. A8 is used for DLL reset. A9 ~ A11 are used for Write latency. Refer to the table for specific codes for various addressing modes and CAS latencies. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 WL DLL TM CAS Latency BT CL Burst Length Test Mode BA1 0 0 BA0 0 1 An ~ A0 MRS EMRS A7 0 1 mode Normal Test Burst Type A3 0 1 Burst Type Sequential Reserved DLL A8 DLL Reset No Yes 0 Write Latency Reserved 1 2 3 4 5 6 7 1 Write Latency A11 0 0 0 0 1 1 1 1 A10 0 0 1 1 0 0 1 1 A9 0 1 0 1 0 1 0 1 Note : DLL reset is self-clearing Burst Length CAS Latency A2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CAS Latency 8 9 10 11 4 5 6 7 Reserved(12) Reserved(13) Reserved(14) Reserved(15) Reserved Reserved Reserved Reserved A1 0 0 1 1 A0 0 1 0 1 Burst Length Reserved Reserved 4 8 RFU(Reserved for future use) should stay "0" during MRS cycle 9 of 53 Rev. 1.1 November 2005 K4J55323QG 256M GDDR3 SDRAM PROGRAMMABLE IMPEDANCE OUTPUT BUFFER AND ACTIVE TERMINATOR The GDDR3 SDRAM is equipped with programmable impedance output buffers and Active Terminators. This allows a user to match the driver impedance to the system. To adjust the impedance, an external precision resistor(RQ) is connected between the ZQ pin and Vss. The value of the resistor must be six times of the desired output impedance. For example, a 240 resistor is required for an output impedance of 40 . To ensure that output impedance is one sixth the value of RQ (within 10 %), the range of RQ is 120 to 360 (20 to 60) output impedance. MF,SEN, RES, CK and /CK are not internally terminated. CK and /CK will be terminated on the system module using external 1% resisters. The output impedance is updated during all AUTO REFRESH commands and NOP commands when a READ is not in progress to compensate for variations in voltage supply and temperature. The output impedance updates are transparent to the system. Impedance updates do not affect device operation, and all data sheet timing and current specifications are met during update. To guarantee optimum output driver impedance after power-up, the GDDR3(x32) needs at least 20us after the clock is applied and stable to calibrate the impedance upon power-up. The user may operate the part with less than 20us, but the optimal output impedance is not guaranteed. The value of ZQ is also used to calibrated the internal address/command termination resisters. The two termination values that are selectable during power up are 1/2 of ZQ and ZQ. The value of ZQ is used to calibrate the internal DQ termination resisters. The two termination values that are selectable are 1/4 of ZQ and 1/2 of ZQ. BURST LENGTH Read and write accesses to the GDDR3 SDRAM are burst oriented, with the burst length being programmable, as shown in MRS table. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2-Ai when the burst length is set to four (Where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmable burst length applies to both READ and WRITE bursts. BURST TYPE Accesses within a given burst must be programmed to be sequential; this is referred to as the burst type and is selected via bit M3. This device does not support the interleaved burst mode found in GDDR SDRAM devices. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in below table: Burst Definition Burst Definition Burst Length 4 A2 0 A2 8 0 1 Starting Column Address A1 0 A1 0 0 A0 0 A0 0 0 Order of Accesses Within a Burst Type= Sequential 0-1-2-3 0-1-2-3-4-5-6-7 4-5-6-7-0-1-2-3 Note : 1. For a burst length of four, A2-A7 select the block of four burst; A0-A1 select the starting column within the block and must be set to zero 2. For a burst length of eight, A3-A7 select the block of eight burst; A0-A2 select the starting column within the block. 10 of 53 Rev. 1.1 November 2005 K4J55323QG CAS LATENCY (READ LATENCY) 256M GDDR3 SDRAM The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 4~15 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n+m. Below table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. CAS Latency SPEED -10 -11 -12 -14 Allowable operating frequency (MHz) CL=15 CL=14 TBD TBD 800 700 600 CL=13 CL=12 CL=11 CL=10 CL=9 CL=8 CL=7 -16 -20 - - - 500 T0 T5 T6 T7 T7n /CK CK COMMAND READ NOP CL = 7 NOP NOP RDQS DQ T0 T6 T7 T8 T8n /CK CK COMMAND READ NOP CL = 8 NOP NOP RDQS DQ Burst Length = 4 in the cases shown Shown with nominal tAC and nominal tDSDQ DON'T CARE TRANSITIONING DATA 11 of 53 Rev. 1.1 November 2005 K4J55323QG WRITE LATENCY 256M GDDR3 SDRAM The Write latency (WL) is the delay, in clock cycles, between the registration of a WRITE command and the availability of the first bit of input data. The latency can be set from 1 to 7 clocks depending in the operating frequency and desired current draw. When the write latencies are set to 1 or 2 or 3 clocks, the input receivers never turn off when the WRITE command is registered. If a WRITE command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n+m. Reserved states should not be used as unknown operation or incompatibility with future versions may result. T0 /CK CK COMMAND T1 T2 T3 T3n WRITE NOP WL = 3 NOP NOP WDQS DQ T0 T2 T3 T4 T4n /CK CK COMMAND WRITE NOP WL = 4 NOP NOP WDQS DQ Burst Length = 4 in the cases shown DON'T CARE TRANSITIONING DATA 12 of 53 Rev. 1.1 November 2005 K4J55323QG TEST MODE 256M GDDR3 SDRAM The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7 set to zero, and bits A0-A6 and A8A11 set to the desired values. Test mode is entered by issuing a MODE REGISTER SET command with bit A7 set to one, and bits A0A6 and A8-A11 set to the desired values. Test mode functions are specific to each Dram Manufacturer and its exact functions are hidden from the user. DLL RESET The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A7 set to zero, and bits A0-A6 and A8A11 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bit A8 set to one, and bits A0A7 and A9-A11 set to the desired values. When a DLL Reset is complete the GDDR3 SDRAM reset bit 8 of the mode register to a zero. After DLL Reset MRS, Power down can not be issued within 10 clock. In case the clock frequency need to be changed after the power-up, 256Mb GDDR3 doesn't require DLL reset. Instead, DLL should be disabled first before the frequency changed and then change the clock frequency as needed. After the clock frequency changed, there needed some time till clock become stable and then enable the DLL and then 20K cycle required to lock the DLL Clock frequency change sequence after the power-up(example) 700Mbps 1000Mbps ~ CK,CK ~ ~ Command ~ EMRS DLL Disable EMRS DLL Enable Any Command Wait until clock stable 20K cycle for DLL locking time 13 of 53 Rev. 1.1 November 2005 K4J55323QG 7.4 EXTENDED MODE REGISTER SET(EMRS) 256M GDDR3 SDRAM The extended mode register stores the data output driver strength and on-die termination options. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR3 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA0,BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. The minimum clock cycles specified as tMRD are required to complete the write operation in the extended mode register. 4 kinds of the output driver strength are supported by EMRS (A1, A0) code. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. "High" on BA0 is used for EMRS. Refer to the table for specific codes. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 1 Term ID RON AL tWR DLL tWR Termination Drive Strength Vendor ID BA1 0 0 BA0 0 1 An ~ A0 MRS EMRS A10 0 1 Vendor ID Off On DLL A6 0 1 DLL Enable Disable Drive Strength A1 0 0 1 Additive Latency 1 A8 0 1 AL 0 1 A0 0 1 0 1 Drive Strength Autocal 30 40 50 ADDR/CMD Termination A11 0 1 Termination Default Half of default Data Termination A3 tWR A7 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 tWR 11 13 5 6 7 8 9 10 0 0 1 1 A2 0 1 0 1 Termination ODT Disabled*1 Reserved ZQ/4 ZQ/2 Default value is determined by CKE status at the rising edge of RESET during power-up Ron of Pull-up A9 0 1 RON 40 60 RFU(Reserved for future use) should stay "0" during EMRS cycle * ZQ : Resistor connection pin for On-die termination * 1 : ALL ODT will be disabled 14 of 53 Rev. 1.1 November 2005 K4J55323QG DLL ENABLE/DISABLE 256M GDDR3 SDRAM The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after disabling the DLL for debugging or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 20K clock cycles must occur before an any command can be issued. DATA TERMINATION The Data Termination, DT, is used to determine the value of the internal data termination resisters. The GDDR3 SDRAM supports 60 and 120 termination. The termination may also be disabled for testing and other purposes. DATA DRIVER IMPEDANCE The Data Driver impedance (DZ) is used to determine the value of the data drivers impedance. When auto calibration is used the data driver impedance is set to RQ/6 and it's tolerance is determined by the calibration accuracy of the device. When any other value is selected the target impedance is set nominally to the desired impedance. However, the accuracy is now determined by the device's specific process corner, applied voltage and operating temperature. ADDITIVE LATENCY The Additive Latency function (AL) is used to optimize the command bus efficiency. The AL value is used to determine the number of clock cycles that is to be added to CL after CAS is captured by the rising edge of CK. Thus the total CAS latency is determined by adding CL and AL. 15 of 53 Rev. 1.1 November 2005 K4J55323QG 256M GDDR3 SDRAM 7.5 MANUFACTURERS VENDOR CODE AND REVISION IDENTIFICATION The Manufacturers Vendor Code, V, is selected by issuing a EXTENDED MODE REGISTER SET command with bits A10 set to one, and bits A0-A9 and A11 set to the desired values. When the V function is enabled the GDDR3 SDRAM will provide its manufacturers vendor code on DQ[3:0] and revision identification on DQ[7:4] Manufacturer Reserved Samsung Infineon Elpida Etron Nanya DQ[3:0] 0 1 2 3 4 5 Manufacturer Hynix Mosel Winbond ESMT Reserved Reserved DQ[3:0] 6 7 8 9 A B Manufacturer Reserved Reserved Reserved Micron DQ[3:0] C D E F Vendor ID Read T0 CK CK RES tCH tIS tIH tCL T1 Ta2 Tb3 Tc4 Td5 Te6 Tf7 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ CKE tIS tIH ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 200 cycle High DQ[3:0] >20ns >20ns Vendor Code ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ tRP Precharge All Banks tMRD EMRS Vendor_ID On tMRD EMRS Vendor_ID Off tMRD MRS tMRD Precharge All Banks Dummy_MRS w/ specified value DON'T CARE TRANSITIONING DATA 16 of 53 Rev. 1.1 November 2005 ~ ~ tRP 1st Auto Refresh ~ ~ COMMAND ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ K4J55323QG 256M GDDR3 SDRAM 7.6 Clock frequency change sequence during the device operation Both existing tCK and desired tCK are in DLL-On mode - Change frequency from existing frequency to desired frequency - Issue Precharge All Banks command - Issue MRS command to reset the DLL while other fields are valid and required 20K tCK to lock the DLL - Issue Precharge All Banks command. Issue at least Auto-Refresh command CK CK CMD NOP NOP NOP NOP Existing tCK is in DLL-on mode while desired tCK is in DLL-off mode - Issue Precharge All Banks command - Issue EMRS command to disable the DLL - Issue Precharge All Banks command - Change the frequency from existing to desired. - Issue Auto-Refresh command at least two. Issue MRS command CK CK CMD PRE EMRS PRE NOP NOP NOP PRE MRS PRE NOP AR NOP Frequency Change tFCHG All Banks Precharge tRP DLL Reset All Banks Precharge tMRD 20tCK (DLL locking time) NOP NOP AR MRS NOP NOP NOP NOP All Banks Precharge tRP DLL OFF All Banks Precharge tMRD Frequency Change tFCHG Clock frequency change in case existing tCK is in DLL-off mode while desired tCK is in DLL-on mode - Issue Precharge All Banks command and issue EMRS command to disable the DLL. - Issue Precharge All Banks command. - Change the clock frequency from existing to desired - Issue Precharge All Banks command. - Issue EMRS command to enable the DLL - Issue MRS command to reset the DLL and required 20K tCK to lock the DLL. - Issue Precharge All Banks command. - Issue Auto-Refresh command at least two CK CK CMD PRE EMRS PRE NOP NOP NOP PRE EMRS MRS PRE NOP AR All Banks Precharge tRP DLL OFF All Banks Precharge tMRD Frequency Change tFCHG All Banks Precharge tRP DLL On tMRD DLL Reset All Banks Precharge tMRD 20tCK (DLL locking time) 17 of 53 Rev. 1.1 November 2005 K4J55323QG 7.7 BOUNDARY SCAN FUNCTION GENERAL INFORMATION 256M GDDR3 SDRAM The 256Mb GDDR3 incorporates a modified boundary scan test mode as an optional feature. This mode doesn't operate in accordance with IEEE Standard 1149.1 - 1990. To save the current GDDR3 ball-out, this mode will scan parallel data input and output and the scanned data through WDQS0 pin controlled by an add-on pin, SEN which is located at V4 of 136 ball package. For the normal device operation other than boundary scan, there required device re-initialization by device power-off and then power-on. DISABLING THE SCAN FEATURE It is possible to operate the 256Mb GDDR3 without using the boundary scan feature. SEN(at V-4 of 136 ball package) should be tied LOW(VSS) to prevent the device from entering the boundary scan mode. The other pins which are used for scan mode, RES, MF, WDQS0 and CS# will be operating at normal GDDR3 function when SEN is de-asserted. Figure 1. Internal Block Diagram (Reference Only) Dedicated Scan Flops (1per signal under test) Tie to Iogic 0 DM0 D DQ CK Pins under test DQS D DQ CK DQ4 D DQ CK The following lists the rest of the signals on the scan chain: DQ[3:0], DQ[31:6], RDQS[3:1], WDQS[3:1], DM[3:1], RFU, CAS#, WE#, CKE, BA[1:0], A[11:0], CK, CK# and ZQ Two RFU's(J-2 and J-3 on 136-ball package) and one RFM(H-10 on 136-ball package) will be on the scan chain and will be read as a logic "0" RDQS0 D DQ CK The following lists signals not on the scan chain: NC, VDD, VSS, VDDQ, VSSQ, VREF In case ZQ pin is connected to the external resistor, it will be read as logic "0". However, if the ZQ pin is open, it will be read as floating. Accordingly, ZQ pin should be driven by any signal. RES (SSH,Scan Shift) CS# (SCK, Scan Clock) WDQS0 (SOUT,Scan Out) RFU at V-4 (SEN, Scan Enable) Puts device into scan mode and re-maps pins to scan functionality MF (SOE#, Output Enable) 18 of 53 Rev. 1.1 November 2005 K4J55323QG BOUNDARY SCAN EXIT ORDER BIT# 1 2 3 4 5 6 7 8 9 10 11 12 BALL D-3 C-2 C-3 B-2 B-3 A-4 B-10 B-11 C-10 C-11 D-10 D-11 BIT# 13 14 15 16 17 18 19 20 21 22 23 24 BALL E-10 F-10 E-11 G-10 F-11 G-9 H-9 H-10 H-11 J-11 J-10 L-9 BIT# 25 26 27 28 29 30 31 32 33 34 35 36 BALL K-11 K-10 K-9 M-9 M-11 L-10 N-11 M-10 N-10 P-11 P-10 R-11 BIT# 37 38 39 40 41 42 43 44 45 46 47 48 BALL R-10 T-11 T-10 T-3 T-2 R-3 R-2 P-3 P-2 N-3 M-3 N-2 256M GDDR3 SDRAM BIT# 49 50 51 52 53 54 55 56 57 58 59 60 BALL L-3 M-2 M-4 K-4 K-3 K-2 L-4 J-3 J-2 H-2 H-3 H-4 BIT# 61 62 63 64 65 66 67 BALL G-4 F-4 F-2 G-3 E-2 F-3 E-3 *Note : 1. When the device is in scan mode, the mirror function will be disabled and none of the pins are remapped. 2. Since the other input of the MUX for DM0 tied to GND, the device will output the continuous zeros after scanning a bit #67, if the chip stays in scan shift mode. 3. Two RFU balls(#56and #57) and one RFM ball(#20) in the scan order will be read as a logic"0". SCAN PIN DESCRIPTION Package Ball V-9 F-9 D-2 V-4 Symbol SSH SCK SOUT SEN Normal Function RES CS WDQS0 RFU Type Input Input Output Input Description Scan shift. Capture the data input from the pad at logic LOW and shift the data on the chain at logic HIGH. Scan Clock. Not a true clock, could be a single pulse or series of pulses. All scan inputs will be referenced to rising edge of the scan clock. Scan Output. Scan Enable. Logic HIGH would enable the device into scan mode and will be disabled at logic LOW. Must be tied to GND when not in use. Scan Output Enable. Enables (registered LOW) and disables (registered HIGH) SOUT data. This pin will be tied to VDD or GND through a resistor (typically 1K ) for normal operation. Tester needs to overdrive this pin guarantee the required input logic level in scan mode. A-9 SOE MF Input *Note : 1. When SEN is asserted, no commands are to be executed by the GDDR3 SDRAM. This applies to both user commands and manufacturing commands which may exist while RES is de-asserted. 2. All scan functionalities are valid only after the appropriate power-up and initialization sequence. (RES and CKE, to set the ODT of the C/A) 3. In scan mode, the ODT for the address and control lines set to a nominal termination value of ZQ. The ODT for DQ's will be disabled. It is not necessary for the termination to be calibrated. 4. In a double-load clam-shell configuration, SEN will be asserted to both devices. Separate two SOE's should be provided to top and bottom devices to access the scanned output. When either of the devices is in scan mode, SOE for the other device which not in a scan will be disabled. 19 of 53 Rev. 1.1 November 2005 K4J55323QG SCAN DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS PARAMETER/CONDITON Input High (Logic 1) Voltage Input Low (Logic 0) Voltage *Note : 1. The parameter applies only when SEN is asserted. 2. All voltages referenced to GND. 256M GDDR3 SDRAM SYMBOL VIH(DC) VIL(DC) MIN VREF+0.15 - MAX VREF-0.15 UNITS V V NOTES 1,2 1,2 Figure 2. Scan Capture Timing Not a true clock, but a single pulse or series of pulses SCK tSES SEN SSH SOE tSDS tSDS LOW tSCS Pins under Test VALID DON'T CARE Figure 3.Scan Shift Timing SCK tSES SEN tSCS SSH tSCS SOE Scan Out bit 0 Scan Out bit 1 Scan Out bit 2 Scan Out bit 3 SOUT tSAC tSOH TRANSITIONING DATA 20 of 53 Rev. 1.1 November 2005 K4J55323QG SCAN AC ELECTRICAL CHARACTERISTICS PARAMETER/CONDITON Clock Clock cycle time Scan Command Time Scan enable setup time Scan enable hold time Scan command setup time for SSH, SOE# and SOUT Scan command hold time for SSH, SOE# and SOUT Scan Capture Time Scan capture setup Time Scan capture hold Time Scan Shift Time Scan clock to valid scan output Scan clock to scan output hold *Note : 1. The parameter applies only when SEN is asserted. 2. Scan Enable should be issued earlier than other Scan Commands by 3ns. 256M GDDR3 SDRAM SYMBOL tSCK tSES tSEH tSCS tSCH tSDS tSCH tSAC tSOH MIN 40 20 20 14 14 10 10 1.5 MAX 6 UNITS ns ns ns ns ns ns ns ns ns NOTES 1 1,2 1 1 1 1 1 1 1 Figure 4. Scan Initialization Sequence tATS tATS VDD VDDQ VREF RES (SSH in Scan Mode) CKE (Dual-load C/A) CKE (Quad-load C/A) SEN tSCS tSCH tSDS tSDH VALID tSDS tSDH VALID tSCS tSCH tSES SCK SOE# tSCS tSCS SOUT tSDS tSDH Scan Out Bit0 Pins Under Test VALID T = 200us RESET at power - up Boundary Scan Mode Note : To set the pre-defined ODT for C/A, a boundary scan mode should be issued after an appropriate ODT initialization sequence with RES and CKE signals 21 of 53 Rev. 1.1 November 2005 K4J55323QG 7.8 Mirror Function 256M GDDR3 SDRAM The GDDR3 SDRAM provides a mirror function (MF) ball to change the physical location of the control lines and all address lines which helps to route devices back to back. The MF ball will affect RAS, CAS, WE, CS and CKE on balls H3, F4, H9, F9 and H4 respectively and A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, BA0 and BA1 on balls K4, H2, K3, M4, K9, H11, K10, L9, K11, M9, K2, L4, G4 and G9 respectively and only detects a DC input. The MF ball should be tied directly to VSS or VDD depending on the control line orientation desired. When the MF ball is tied low the ball orientation is as follows, RAS - H3, CAS - F4, WE - H9, CS - F9, CKE H4, A0 - K4, A1 - H2, A2 - K3, A3 - M4, A4 - K9, A5 - H11, A6 - K10, A7 - L9, A8 - K11, A9 - M9, A10 - K2, A11 - L4, BA0 - G4 and BA1 - G9. The high condition on the MF ball will change the location of the control balls as follows; CS - F4, CAS - F9, RAS - H10, WE - H4, CKE - H9, A0 - K9, A1 - H11, A2 - K10, A3 - M9, A4 - K4, A5 - H2, A6 - K3, A7 - L4, A8 - K2, A9 - M4, A10 - K11, A11 - L9, BA0 - G9 and BA1 - G4. Mirror Function Signal Mapping PIN RAS CAS WE CS CKE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 MF LOGIC STATE HIGH H10 F9 H4 F4 H9 K9 H11 K10 M9 K4 H2 K3 L4 K2 M4 K11 L9 G9 G4 LOW H3 F4 H9 F9 H4 K4 H2 K3 M4 K9 H11 K10 L9 K11 M9 K2 L4 G4 G9 22 of 53 Rev. 1.1 November 2005 K4J55323QG 7.9 OPERATIONS 7.9.1 BANK/ROW ACTIVATION 256M GDDR3 SDRAM /CK CK CKE /CS HIGH Before any READ or WRITE commands can be issued to a banks within the GDDR3 SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD(min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command in which a READ or WRITE command can be entered. For example, a tRCD specification of 16ns with a 800MHz clock (1.25ns period) results in 12.8 clocks rounded to 13. This is reflected in below figure, which covers any case where 12 /CAS /WE A0-A11 RA BA0,BA1 BA RA = Row Address BA = Bank Address Activating a Specific Row in a Specific Bank Example : Meeting tRCD T0 /CK CK T1 T2 T3 T4 T12 T13 T14 COMMAND ACT NOP NOP ACT NOP NOP RD/WR NOP A0-A11 Row Row Col BA0,BA1 Bank x tRRD Bank y Bank y tRCD DON'T CARE 23 of 53 Rev. 1.1 November 2005 K4J55323QG 256M GDDR3 SDRAM 7.9.2 READs READ bursts are initiated with a READ command, as below figure. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst after tRAS(min) has been met. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS Latency after the READ command. Each subsequent data-out element will be valid nominally at the next positive or negative strobe edge. READ burst figure shows general timing for 2 of the possible CAS latency settings. The GDDR3(x32) drives the output data edge aligned to the crossing of CK and /CK and to RDQS. The initial HIGH transition LOW of RDQS is known as the read preamble ; the half cycle coincident with the last data-out element is known as the read postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A detailed explanation of tDQSQ (valid data-out skew), tDV (data-out window hold), the valid data window are depicted in Data Output Timing (1) figure. A detailed explanation of tAC (DQS and DQ transition skew to CK) is shown in Data Output Timing (2) figure. Data from any READ burst may be concatenated with data from a subsequent READ command. A continuous flow of data can be maintained. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued x cycles after the first READ command, where x equals the number of data element nibbles (nibbles are required by the 4n-prefetch architecture) depending on the burst length. This is shown in consecutive READ bursts figure. Nonconsecutive read data is shown for illustration in nonconsecutive READ bursts figure. Full-speed random read accesses within a page (or pages) can be performed as shown in Random READ accesses figure. Data from a READ burst cannot be terminated or truncated. During READ commands the GDDR3 Dram disables its data terminators. /CK CK CKE /CS HIGH /RAS /CAS /WE A0-A7, A9 CA A10, A11 EN AP A8 DIS AP BA0, BA1 BA CA = Column Address BA = Bank Address EN AP = Enable Auto Precharge DIS AP = Disable Auto Precharge DON'T CARE READ Command 24 of 53 Rev. 1.1 November 2005 K4J55323QG Data Output Timing (1) - tDQSQ, tQH and Data Valid Window T0 CK# CK tCH tCL tDQSQ2 (MAX) RDQS 1.6 256M GDDR3 SDRAM T1 T2 T2n T3 T3n T4 tDQSQ2 (MAX) tDQSQ2 (MIN) tDQSQ2 (MIN) DQ(Last data valid) tDQSH4 T2 tDQSL4 T2n T3 T3n DQ(First data no longer valid) All DQs and RDQS, collectively5 T2 T2n T3 T3n T2 T2n T3 T3n tDV4 tDV4 tDV4 tDV4 Data Output Timing (2) - tDQSQ, tQH and Data Valid Window T0 CK# CK tCH tAC(MAX) tCL T1 T2 T2n T3 T3n T4 RDQS 1.6 All DQs and RDQS, collectively5 tDQSH4 T2 T2n tDQSL4 T3 T3n RDQS 1.6 All DQs and RDQS, collectively5 tAC(MIN) tDQSH4 T2 T2n tDQSL4 T3 T3n Note : 1. tDQSQ represents the skew between the 8 DQ lines and the respective RDQS pin. 2. tDQSQ is derived at each RDQS clock edge and is not cumulative over time and begins with first DQ transition and ends with the last valid transition of DQs. 3. tAC is show in the nominal case 4. tDQHP is the lesser of tDQSL or tDQSH strobe transition collectively when a bank is active. 5. The data valid window is derived for each RDQS transitions and is defined by tDV. 6. There are 4 RDQS pins for this device with RDQS0 in relation to DQ0-DQ7, RDQS1 in relation DQ8-DQ15, RDQS2 in relation to DQ16-24 and RDQS3 in relation to DQ25-DQ31. 7. This diagram only represents one of the four byte lanes. 8. tAC represents the relationship between DQ, RDQS to the crossing of CK and /CK. 25 of 53 Rev. 1.1 November 2005 K4J55323QG READ Burst T0 256M GDDR3 SDRAM T7 T8 T8n T9 T9n T10 T11 /CK CK COMMAND READ NOP NOP NOP NOP NOP ADDRESS Bank a, Col n CL = 8 RDQS DQ DO n T0 T7 T8 T9 T9n T10 T11 /CK CK COMMAND READ NOP NOP NOP NOP NOP ADDRESS Bank a, Col n CL = 9 RDQS DQ DO n DON'T CARE NOTE : TRANSITIONING DATA 1. DO n=data-out from column n. 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following DQ n. 4. Shown with nominal tAC and tDQSQ. 5. RDQS will start driving high 1/2 clock cycle prior to the first falling edge. 26 of 53 Rev. 1.1 November 2005 K4J55323QG Consecutive READ Bursts T0 256M GDDR3 SDRAM T2 T7 T8 T8n T9 T9n T10 T10n /CK CK COMMAND READ READ NOP NOP NOP NOP ADDRESS Bank a, Col n Bank a, Col b CL = 8 RDQS DQ DO n DO b DON'T CARE TRANSITIONING DATA NOTE :1. DO n (or b) = data-out from column n (or column b). 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following DQ n. 4. Three subsequent elements of data-out appear in the programmed order following DQ b. 5. Shown with nominal tAC and tDQSQ. 6. Example applies when READ commands are issued to different devices or nonconsecutive READs. 7. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS. 27 of 53 Rev. 1.1 November 2005 K4J55323QG Nonconsecutive READ Bursts T0 256M GDDR3 SDRAM T7 T8 T8n T9 T9n T10 T17 T17n T18 /CK CK COMMAND READ NOP NOP READ NOP NOP NOP ADDRESS Bank a, Col n CL = 8 Bank a, Col b RDQS DQ DO n DO b T0 /CK CK T1 T7 T8 T8n T9 T10 T10n T11 COMMAND READ NOP NOP READ NOP NOP NOP ADDRESS Bank a, Col n CL = 8 Bank a, Col b RDQS DQ DO n DO b DON'T CARE TRANSITIONING DATA NOTE : 1. DO n (or b) = data-out from column n (or column b). 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following DQ n. 4. Three subsequent elements of data-out appear in the programmed order following DQ b. 5. Shown with nominal tAC and tDQSQ. 6. Example applies when READ commands are issued to different devices or nonconsecutive READs. 7. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS. 28 of 53 Rev. 1.1 November 2005 K4J55323QG Random READ Accesses T0 /CK CK T1 T2 256M GDDR3 SDRAM T8 T8n T9 T9n T10 T10n COMMAND READ NOP READ NOP NOP NOP ADDRESS Bank a, Col n CL = 8 Bank a, Col b RDQS DQ DO n DO n DO n DO n DO b T0 /CK CK T1 T7 T8 T8n T9 T9n T15 T15n COMMAND READ NOP READ NOP NOP NOP ADDRESS Bank a, Col n CL = 8 Bank a, Col b RDQS DQ DO n DO n DO n DO n DO b DON'T CARE NOTE : TRANSITIONING DATA 1. DO n (or x or b or g) = data-out from column n (or column x or column x or column b or column g). 2. Burst length = 4 3. n' or x or b' or g' indicates the next data-out following DO n or DO x or DO b OR DO g, respectively 4. READs are to an active row in any bank. 5. Shown with nominal tAC and tDQSQ. 6. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS. 29 of 53 Rev. 1.1 November 2005 K4J55323QG READ to WRITE 256M GDDR3 SDRAM T0 T7 T8 T8n T9 T9n T10 T11 T12 T12n /CK CK COMMAND READ NOP WRITE NOP NOP NOP NOP ADDRESS Bank Col n Bank a, Col b CL = 8 RDQS tWL = 4 WDQS DQ DO n DI b DM DQ Termination DQ Termination Disabled DQ Termination Enbaled 1tCK < DON'T CARE NOTE : TRANSITIONING DATA 1. DO n = data-out from column n. 2. DI b = data-in from column b. 3. Burst length = 4 4. One subsequent element of data-out appears in the programmed order following DO n. 5. Data-in elements are applied following DI b in the programmed order. 6. Shown with nominal tAC and tDQSQ. 7. tDQSS in nominal case. 8. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS. 9. The gap between data termination enable to the first data-in should be greater than 1tCK 30 of 53 Rev. 1.1 November 2005 K4J55323QG READ to PRECHARGE T0 /CK CK T1 T2 256M GDDR3 SDRAM T8 T8n T9 T9n T10 COMMAND READ NOP PRE NOP NOP ACT ADDRESS Bank a, Col n CL = 8 Bank a, (a or all) Bank a, Row tRP RDQS DQ DO n T0 /CK CK T1 T7 T8 T8n T9 T13 COMMAND READ NOP PRE NOP NOP ACT ADDRESS Bank a, Col n Bank a, (a or all) tRP Bank a, Row CL = 8 RDQS DQ DO n DON'T CARE TRANSITIONING DATA NOTE : 1. DO n (or b) = data-out from column n (or column b). 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following DQ n. 4. Three subsequent elements of data-out appear in the programmed order following DQ b. 5. Shown with nominal tAC and tDQSQ. 6. Example applies when READ commands are issued to different devices or nonconsecutive READs. 7. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS. 31 of 53 Rev. 1.1 November 2005 K4J55323QG 256M GDDR3 SDRAM 7.9.3 WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered in a rising edge of WDQS following the WRITE latency set in the mode register and subsequent data elements will be registered on successive edges of WDQS. Prior to the first valid WDQS edge a half cycle is needed and specified as the WRITE Preamble; the half cycle in WDQS following the last data-in element is known as the write postamble. The time between the WRITE command and the first valid falling edge of WDQS (tDQSS) is specified with a relative to the write latency. All of the WRITE diagrams show the nominal case, and where the two extreme cases (i.e., tDQSS(min) and tDQSS(max)) might not be intuitive, they have also been included. Write Burst figure shows the nominal case and the extremes of tDQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored. Data for any WRITE burst may not be truncated with a subsequent WRITE command. The new WRITE command can be issued on any positive edge of clock following the previous WRITE command after the burst has completed. The new WRITE command should be issued x cycles after the first WRITE command should be equals the number of desired nibbles (nibbles are required by 4n-prefetch architecture). An example of nonconsecutive WRITEs is shown in Nonconsecutive WRITE to READ figure. Full-speed random write accesses within a page or pages can be performed as shown in Random WRITE cycles figure. Data for any WRITE burst may be followed by a subsequent READ command. Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE the WRITE burst, tWR should be met as shown in WRITE to PRECHARGE figure. Data for any WRITE burst can not be truncated by a subsequent PRECHARGE command. /CK CK CKE HIGH /CS /RAS /CAS /WE A0-A7, A9 CA A10, A11 EN AP A8 DIS AP BA0, BA1 BA CA = Column Address BA = Bank Address EN AP = Enable Auto Precharge DIS AP = Disable Auto Precharge DON'T CARE WRITE Command 32 of 53 Rev. 1.1 November 2005 K4J55323QG WRITE Burst T0 T1 T2 T3 T3n T4 256M GDDR3 SDRAM /CK CK COMMAND ADDRESS T4n T5 T5n T6 WRITE Bank a, Col b NOP NOP NOP NOP NOP NOP tDQSS(NOM) WDQS DQ DM tDQSS DI b tDQSS(MIN) WDQS DQ DM tDQSS DI b tDQSS(MAX) WDQS DQ DM tDQSS DI b DON'T CARE NOTE : TRANSITIONING DATA 1. DI b = data-in for column b. 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. A burst of 4 is shown. 4. A8 is LOW with the WRITE command (auto precharge is disabled). 5. Write latency is set to 4 33 of 53 Rev. 1.1 November 2005 K4J55323QG Consecutive WRITE to WRITE T0 CK# CK T1 T2 T3 T3n T4 T4n 256M GDDR3 SDRAM T5 T5n T6 T6n T7 COMMAND WRITE NOP WRITE NOP NOP NOP NOP NOP ADDRESS Bank Col b tDQSS (NOM) Bank Col n WDQS DQ DI b DI n DM DON'T CARE TRANSITIONING DATA NOTE : 1. DI b, etc. = data-in for column b, etc. 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. Three subsequent elements of data-in are applied in the programmed order following DI n. 4. Burst of 4 is shown. 5. Each WRITE command may be to any bank of the same device. 6. Write latency is set to 3 34 of 53 Rev. 1.1 November 2005 K4J55323QG Nonconsecutive WRITE to WRITE T0 /CK CK T1 T2 T3 T3n T4 T4n 256M GDDR3 SDRAM T5 T5n T6 T6n T7 COMMAND WRITE NOP NOP WRITE NOP NOP NOP NOP ADDRESS Bank, Col b tDQSS (NOM) Bank, Col n WDQS DQ DI b DON'T CARE DI n DM DON'T CARE TRANSITIONING DATA NOTE : 1. DI b, etc. = data-in for column b, etc. 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. Three subsequent elements of data-in are applied in the programmed order following DI n. 4. burst of 4 is shown. 5. Each WRITE command may be to any bank. 6. Write latency is set to 3 35 of 53 Rev. 1.1 November 2005 K4J55323QG Random WRITE Cycles T0 /CK CK T1 T2 T3 T3n T4 T4n 256M GDDR3 SDRAM T5 T5n T6 T6n T7 COMMAND WRITE NOP WRITE NOP WRITE NOP NOP NOP ADDRESS Bank Col b tDQSS (NOM) Bank Col x Bank Col g WDQS DQ DI b DI b DI b DI b DI x DI x DI x DI x DI g DI g DM DON'T CARE TRANSITIONING DATA NOTE : 1. DI b, etc. = data-in for column b, etc. 2. b: etc. = the next data - in following DI b. etc., according to the programmed burst order. 3. Programmed burst length = 4 cases shown. 4. Each WRITE command may be to any bank. 5. Last write command will have the rest of the nibble on T8 and T8n 6. Write latency is set to 3 36 of 53 Rev. 1.1 November 2005 K4J55323QG WRITE to READ 256M GDDR3 SDRAM T0 /CK CK T1 T2 T3 T3n T4 T4n T5 T6 T10 T17 T18 T18n COMMAND WRITE NOP NOP NOP NOP NOP NOP READ NOP NOP ADDRESS Bank Col b tCDLR = 5 Bank a. Col n tDQSS (NOM) WDQS tDQSS CL = 8 DQ DI b DI n DM RDQS tDQSS (MIN) WDQS tDQSS CL = 8 DQ DI b DI n DM RDQS tDQSS (MAX) WDQS tDQSS CL = 8 DQ DI b DI n DM RDQS NOTE : DON'T CARE TRANSITIONING DATA 1. DI b = data-in for column b. 2. Three subsequent elements of data-in the programmed order following DI b. 3. A burst of 4 is shown. 4. tCDLR is referenced from the first positive CK edge after the last data-in pair. 5. The READ and WRITE commands are to the same device. However, the READ and WRITE commands may be to different devices, in which case tCDLR is not required and the READ command could be applied earlier. 6. A8 is LOW with the WRITE command (auto precharge is disabled). 7. WRITE latency is set to 3 37 of 53 Rev. 1.1 November 2005 K4J55323QG WRITE to PRECHARGE 256M GDDR3 SDRAM T0 /CK CK T1 T2 T3 T3n T4 T4n T5 T8 T9 T10 T11 COMMAND WRITE NOP NOP NOP NOP NOP NOP tWR PRE NOP tRP NOP ADDRESS Bank Col b Bank (a or all) tDQSS (NOM) WDQS tDQSS DQ DI b DM tDQSS (MIN) WDQS tDQSS DQ DI b DM tDQSS (MAX) WDQS tDQSS DQ DI b DM DON'T CARE NOTE : 1. DI b = data-in for column b. 2. Three subsequent elements of data-in the programmed order following DI b. 3. A burst of 4 is shown. 4. A8 is LOW with the WRITE command (auto precharge is disabled). 5. WRITE latency is set to 3 TRANSITIONING DATA 38 of 53 Rev. 1.1 November 2005 K4J55323QG 256M GDDR3 SDRAM 7.9.4 PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A8 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to the bank. /CK CK CKE HIGH /CS /RAS 7.9.5 POWER-DOWN (CKE NOT ACTIVE) Unlike SDR SDRAMs,GDDR3(x32) SDRAM requires CKE to be active at all times an access is in progress; from the issuing of a READ or WRITE command until completion of the burst. For READs, a burst completion is defined when the Read Postamble is satisfied; For WRITEs, a burst completion is defined BL/2 cycles after the Write Postamble is satisfied. /CAS /WE A0-A7, A9-A11 ALL BANKS A8 ONE BANK BA0, BA1 BA DON'T CARE BA=Bank Address (if A8 is LOW; otherwise "Don't Care") Power-down is entered when CKE is registered LOW. If power-down occurs when there is a row active in any bank, this mode is referred to as active powerdown. Entering power-down deactivates the input and output buffers, excluding CK,/CK and CKE. For maximum power savings, the user has the option of disabling the DLL prior to entering power-down. However, power-down duration is limited by the refresh requirements of the device, so in most applications,the selfrefresh mode is preferred over the DLL-disabled power-down mode. When in power-down, CKE LOW and a stable clock signal must be maintained at the inputs of the GDDR3 SDRAM, while all other input signals are "Don't Care" except data terminator disable command. The power-down state is synchronously exited when CKE is registered HIGH (in conjunction with a NOP or DESELECT command). A valid executable command may be applied tPDEX later. PRECHARGE Command Power-Down /CK CK CKE T0 T1 tIS T2 Ta0 Ta1 tIS Ta2 tPDEX Ta7 COMMAND VALID No PEAD/WRITE access in progress NOP NOP NOP VALID * Enter power - down mode Exit power - down mode * Once the device enters the power down mode, it should be in NOP state at least for 10ns 39 of 53 Rev. 1.1 November 2005 K4J55323QG 256M GDDR3 SDRAM 8.0 IBIS : I/V Characteristics for Input and Output Buffers (2) OCD (40 ) Pulldown Current (mA) Pullup Current (mA) Minimum -2.4 -4.7 -7.0 -9.2 -11.4 -13.4 -15.4 -17.1 -18.8 -20.3 -21.7 -22.9 -23.9 -24.8 -25.4 Maximum -3.1 -6.2 -9.2 -12.1 -14.9 -17.7 -20.3 -22.8 -25.2 -27.5 -29.6 -31.6 -33.3 -34.9 -36.3 Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 Minimum 2.4 4.7 7.0 9.3 11.5 13.6 15.7 17.7 19.6 21.4 23.2 24.8 26.3 27.7 29.0 Maximum 2.8 5.5 8.3 11.0 13.7 16.4 19.0 21.6 24.2 26.7 29.1 31.6 34.0 36.3 38.5 Pull-Up 0 1 -5 -10 3 5 7 9 11 13 15 IOH (mA) -15 -20 -25 -30 -35 -40 Min Max Voltage (V) 40 of 53 Rev. 1.1 November 2005 K4J55323QG 256M GDDR3 SDRAM Pull-Down 45 40 35 30 IOL (mA) 25 20 15 10 5 0 1 3 5 7 9 11 13 15 Min Max Voltage (V) 41 of 53 Rev. 1.1 November 2005 K4J55323QG TRUTH TABLE - Clock Enable (CKE) CKEn-1 L L CKEn L H CURRENT STATE Power-Down Self Refresh Power-Down Self Refresh All Banks Idle H L Bank(s) Active All Banks Idle COMMANDn X X DESELECT or NOP DESELECT or NOP DESELECT or NOP DESELECT or NOP AUTO REFRESH 256M GDDR3 SDRAM ACTIONn Maintain Power-Down Maintain Self Refresh Exit Power-Down Exit Self Refresh Precharge Power-Down Entry Active Power-Down Entry Self Refresh Entry 5 NOTES Note : 1. CKEn is the logic state of CKE at clock edge n; CKEn-1was the state of CKE at the previous clock edge. 2. Current state is the state of the GDDR3(x32) immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn 4. All state and sequence not shown are illegal or reserved. TRUTH TABLE - CURRENT STATE BANK n - COMMAND TO BANK n CURRENT STATE Any /CS H L X Idle L L L Row Active L L L Read (Auto-Precharge Disable) Write (Auto-Precharge Disabled) L L L L L L /RAS /CAS X H H L L L H H L H H L H H L X H L H L L L L H L L H L L H /WE X H H H H L H L L H L L H L L COMMAND/ ACTION DESELECT (NOP/ continue previous operation) NO OPERATION (NOP/continue previous operation) DATA TERMINATOR DISABLE ACTIVE (Select and activate row) AUTO REFRESH LOAD MODE REGISTER READ (Select column and start READ burst) WRITE (Select Column and start WRITE burst) PRECHARGE (Deactivate row in bank or banks) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Only after the READ burst is complete) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE (Only after the WRITE burst is complete) 7 7 10 10 8 10 10, 12 8 10, 11 10 8, 11 NOTES Note : 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see CKE Truth Table) and after tXSNR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below. 3. Current state definitions : Idle : The bank has been precharged, and tRP has been met. Row Active : A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read : A READ burst has been initiated, with auto precharge disabled. Write : A WRITE burst has been initiated, with auto precharge disabled. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and truth table- current state bank n -command to bank n. and according to truth table - current state bank n -command to bank m. Precharging : Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating : Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the :row active" state. 42 of 53 Rev. 1.1 November 2005 K4J55323QG 256M GDDR3 SDRAM Read w/ Auto- : Starts with registration of an READ command with auto precharge enabled and ends Precharge Enabled when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/ Auto- : Starts with registration of a WRITE command with auto precharge enabled and ends Precharge Enabled when tRP has been met. Once tRP is met, the bank will be in the idle state. 5. The following states must not be interrupted by any executable command ; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing : Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the GDDR3(x32) will be in the all banks idle state. Accessing Mode : Starts with registration of a LOAD MODE REGISTER command and ends when tMRD Register has been met. Once tMRD is met, the GDDR3(x32) SDRAM will be in the all banks idle state. Precharge All : Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. READ or WRITE : Starts with registration of the ACTIVE command and ends the last valid data nibble. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle, and bursts are not in progress. 8. May or may not be bank-specific ; If multiple banks are to be precharged, each must be in a valid state for precharging. 9. Left blank 10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 11. Requires appropriate DM masking. 12. A WRITE command may be applied after the completion of the READ burst. TRUTH TABLE - CURRENT STATE BANK n - COMMAND TO BANK m CURRENT STATE Any Idle Row Activating, Active, or Prechrging /CS H L X X L L L L L Read (Auto-Precharge Disable) L L L L Write (Auto-Precharge Disabled) L L L L Read (With Auto-Precharge) L L L L Write (With Auto-Precharge) L L L /RAS /CAS X H H X L H H L L H H L L H H L L H H L L H H L X H L X H L L H H L L H H L L H H L L H H L L H /WE X H H X H H L L H H L L H H L L H H L L H H L L COMMAND/ ACTION DESELECT (NOP/ continue previous operation) NO OPERATION (NOP/continue previous operation) DATA TERMINATOR DISABLE Any Command Otherwise Allowed to Bank m ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select Column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE 6 6 6 6 6, 7 6 6 6 6 6 NOTES Note : 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see TRUTH TABLE- CKE ) and after tXSNR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 43 of 53 Rev. 1.1 November 2005 K4J55323QG 3. Current state definitions : Idle : The bank has been precharged, and tRP has been met. Row Active : A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read : A READ burst has been initiated, with auto precharge disabled. Write : A WRITE burst has been initiated, with auto precharge disabled. Read w/ Auto- : See following text Precharge Enabled Write w/ Auto- : See following text Precharge Enabled 256M GDDR3 SDRAM 3a. The read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts : the access period and the precharge period. For read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For write with auto precharge, the precharge period begins when tWR ends, with tWR command and ends where the precharge period (or tRP) begins. During the precharge period of the read with auto precharge enabled or write with auto precharge enabled states, ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied. In either case, all other related Limitations apply (e.g., contention between read data write data must be avoided). 3b. The minimum delay from a READ or WRITE command with auto precharge enabled, to a command to a different bank is summarized below. From Command To Command READ or READ w/AP Minimum delay (with concurrent auto precharge) [WL + (BL/2)] tCK + tWR (BL/2) * tCK 1 tCK 1 tCK (BL/2) * tCK [CLRU + (BL/2)] + 1 - WL * tCK 1 tCK 1 tCK WRITE w/AP WRITE or WRITE w/AP PRECHARGE ACTIVE READ or READ w/AP WRITE or WRITE w/AP PRECHARGE ACTIVE READ w/AP 4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. All states and sequences not shown are illegal or reserved. 6. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 7. Requires appropriate DM masking. 44 of 53 Rev. 1.1 November 2005 K4J55323QG 9.0 COMMANDS 256M GDDR3 SDRAM Below Truth table-COMMANDs provides a quick reference of available commands. This is followed by a verbal description of each command. Two additional Truth Tables appear following the operation section : these tables provide current state/next state information. TRUTH TABLE - COMMANDs Name (Function) DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER DATA TERMINATOR DISABLE CS H L L L L L L L X RAS X H L H H L L L H CAS X H H L L H L L L WE X H H H L L H L H ADDR X X Bank/Row Bank/Col Bank/Col Code X Op-Code X NOTES 8, 11 8 3 4 4 5 6, 7 2 TRUTH TABLE - DM Operation Name (Function) Write Enable Write Inhibit DM L H DQS Valid X 10 NOTES Note : 1. CKE is HIGH for all commands except SELF REFRESH. 2. BA0 and BA1 select either the mode register or the extended mode register (BA0=0, BA1=0 select the mode register; BA0=1, BA1=0 select extended mode register; other combinations of BA0~BA1 are reserved). A0~A11 provide the op-code to be written to the selected mode register. 3. BA0 and BA1 provide bank address and A0~A11 provide row address. 4. BA0 and BA1 provide bank address; A0~A7 and A9 provide column address; A8 HIGH enables the auto precharge feature (nonpersistent) , and A8 LOW disables the auto precharge feature. 5. A8 LOW : BA0 and BA1 determine which banks are precharged. A8 HIGH : All banks are precharged. 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; ll inputs and I/Os are "Don't Care" except for CKE. 8. DESELECT and NOP are functionally interchangeable. 9. Cannot be in powerdown or self-refresh state. 10. Used to mask write data ; provided coincident with the corresponding data. 11. Except DATA Termination disable. DESELECT The DESELECT function (/CS high) prevents new commands from being executed by the GDDR3(x32). The GDDR3(x32) SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct selected GDDR3(x32) to perform a NOP (/CS LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The mode registers are loaded via inputs A0-A11. See mode register descriptions in the Register Definition section. The Load Mode Register command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0 and BA1 inputs selects the bank, and the address provided on inputsA0-A11 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. 45 of 53 Rev. 1.1 November 2005 K4J55323QG READ 256M GDDR3 SDRAM The READ command is used to initiate a burst read access to an active row. The value on the BA0 and BA1 inputs select the bank, and the address provided on inputs A0-A7, A9 selects the starting column location. The value on input A8 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0 and BA1 inputs select the bank, and the address provided on inputs A0-A7, A9 selects the starting column location. The value on inputs A8 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW. the corresponding data will be written to memory; If the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A8 determines whether one or all banks are to be precharged, and in the case where only one banks are to be precharged, inputs BA0,BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE command will be treated as a NOP if there is no open row is already in the process of precharging. AUTO PRECHARGE Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A8 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto precharge is non persistent in that it is either enable or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid state within a burst. This "earliest valid stage" is determined as if an explicit PRECHARGE command was issued at the earliest possible time, without violating tRAS(min), as described for each burst type in the Operation section of this data sheet. The user must not issue another command to the same bank until the precharge time(tRP) is completed. AUTO REFRESH Auto Refresh is used during normal operation of the GDDR3 SDRAM and is analogous to /CAS-BEFORE-/RAS (CBR) REFRESH in FPM/EDO DRAMs. This command is non persistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "Don't Care" during an Auto Refresh command. The 256Mb(x32) GDDR3 requires Auto Refresh cycles at an average interval of 3.9us (maximum). A maximum Auto Refresh commands can be posted to any given GDDR3(x32) SDRAM, meaning that the maximum absolute interval between any Auto Refresh command and the next Auto Refresh command is 9 x 3.9us(35.1us). This maximum absolute interval is to allow GDDR3(x32) SDRAM output drivers and internal terminators to automatically re calibrate compensating for voltage and temperature changes. SELF REFRESH The SELF REFRESH command can be used to retain data in the GDDR3(x32) SDRAM ,even if the rest of the system is powered down. When in the self refresh mode,the GDDR3(x32) SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled and reset upon exiting SELF REFRESH. The active termination is also disabled upon entering Self Refresh and enabled upon exiting Self Refresh. (20K clock cycles must then occur before a READ command can be issued). Input signals except CKE are "Don't Care" during SELF REFRESH. The procedure for exiting self refresh requires a sequence of commands. First, CK and /CK must be stable prior to CKE going back HIGH. Once CKE is HIGH,the GDDR3(x32) must have NOP commands issued for tXSNR because tine is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh, DLL requirements and out-put calibration is to apply NOPs for 20K clock cycles before applying any other command to allow the DLL to lock and the output drivers to recalibrate. 46 of 53 Rev. 1.1 November 2005 K4J55323QG DATA TERMINATION DISABLE (BUS SNOOPING FOR READ COMMAND) 256M GDDR3 SDRAM The DATA TERMINATOR DISABLE COMMAND is detected by the device by snooping the bus for READ commands excluding /CS. The GDDR3 DRAM will disable its Data terminators when a READ command is detected. The terminators are disable CL-1 Clocks after the READ command is detected. In a two rank system both dram devices will snoop the bus for READ commands to either device and both will disable their terminators if a READ command is detected. The command and address terminators and always enabled. ON-DIE TERMINATION Bus snooping for READ commands other than /CS is used to control the on-die termination in the dual load configuration. The GDDR3 SDRAM will disable the on-die termination when a READ command is detected, regardless of the state of /CS, when the ODT for the DQ pins are set for dual loads (120). The on-die termination is disabled x clocks after the READ command where x equals CL-1 and stay off for a duration of BL/2 + 2, as below figure, Data Termination Disable Timing. In a two-rank system, both DRAM devices snoop the bus for READ commands to either device and both will disable the on-die termination if a READ command is detected. The on-die termination for all other pins on the device are always on for both a single-rank system and a dual-rank system. The on-die termination value on address and control pins is determined during power-up in relation to the state of CKE on the first transition of RESET. On the rising edge of RESET, if CKE is sampled LOW, then the configuration is determined to be a single-rank system. The on-die termination is then set to one-half ZQ for the address pins. On the rising edge of RESET, if CKE is sampled HIGH, then the configuration is determined to be a dual-rank system. The on-die termination for the DQs, WDQS, and DM pins is set in the EMRS. Data Termination Disable Timing T0 CK# CK T7 T8 T8n T9 T9n T10 T11 COMMAND READ NOP NOP NOP NOP NOP ADDRESS Bank a, Col n CL = 8 RDQS DO n DQ DQ TERMINATION GDDR3 Data Termination is Disabled DON'T CARE TRANSITIONING DATA Note : 1. DO n = data-out from column n. 2. Burst length = 4. 3. Three subsequent elements of data-out appear in the specified order following DO n. 4. Shown with nominal tAC and tDQSQ. 5. RDQS will start driving high one-half cycle prior to the first falling edge. 6. The Data Terminators are disabled starting at CL-1 and the duration is BL/2 + 2 7. READS to either rank disable both ranks' termination regardless of the logic level of /CS. 47 of 53 Rev. 1.1 November 2005 K4J55323QG 10.0 AC & DC OPERATING CONDITIONS 10.1 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDDQ supply relative to Vss MAX Junction Temperature Storage temperature Power dissipation Short Circuit Output Current Symbol VIN, VOUT VDD VDDQ TJ TSTG PD IOS 256M GDDR3 SDRAM Value -0.5 ~ VDDQ + 0.5V -0.5 ~ 2.5 -0.5 ~ 2.5 +125 -55 ~ +150 TBD 50 Unit V V V C C W mA Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure periods may affect reliability. 10.2 POWER & DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to 0C Tc 85C ; VDD=1.8V + 0.1V, VDDQ=1.8V + 0.1V) Parameter Device Supply voltage Output Supply voltage Reference voltage DC Input logic high voltage DC Input logic low voltage Output logic low voltage AC Input logic high voltage AC Input logic low voltage Input leakage current Any input 0V- 48 of 53 Rev. 1.1 November 2005 K4J55323QG 10.3 CLOCK INPUT OPERATING CONDITIONS 256M GDDR3 SDRAM Recommended operating conditions (0C Tc 85C ; VDD=1.8V + 0.1V, VDDQ=1.8V + 0.1V) Parameter/ Condition Clock Input Mid-Point Voltage ; CK and /CK Clock Input Voltage Level; CK and /CK Clock Input Differential Voltage ; CK and /CK Clock Input Differential Voltage ; CK and /CK Clock Input Crossing Point Voltage ; CK and /CK Symbol VMP(DC) VIN(DC) VID(DC) VID(AC) VIX(AC) Min 1.16 0.42 0.22 0.22 VREF - 0.15 Max 1.36 VDDQ + 0.3 VDDQ + 0.5 VDDQ + 0.3 VREF + 0.15 Unit V V V V V Note 1,2,3 2 2,4 4 3 Note : 1. This provides a minimum of 1.16V to a maximum of 1.36V, and is always 70% of VDDQ 2. For AC operations, all DC clock requirements must be satisfied as well. 3. The value of VIX is expected to equal 70% VDDQ for the transmitting device and must track variations in the DC level of the same. 4. VID is the magnitude of the difference between the input level in CK and the input level on /CK. 5. The CK and /CK input reference level (for timing referenced to CK and /CK) is the point at which CK and /CK cross; the input reference level for signals other than CK and /CK is VREF. 6. CK and /CK input slew rate must be > 3V/ns 1.26V VREF VDDQ 60 GDDR3 Z0=60 240 10pf ZQ Output Load Circuit Note : 1 . Outputs measured into equivalent load of 10pf at a driver impedance of 40 . 49 of 53 Rev. 1.1 November 2005 K4J55323QG 10.4 DC CHARACTERISTICS Parameter Operating Current (One Bank Active) Precharge Standby Current in Power-down mode Precharge Standby Current in Non Power-down mode Active Standby Current power-down mode Active Standby Current in in Non Power-down mode Operating Current ( Burst Mode) Refresh Current Self Refresh Current Operating Current (4Bank interleaving) Symbol ICC1 ICC2P ICC2N ICC3P ICC3N ICC4 ICC5 ICC6 ICC7 Test Condition Burst Length=4 tRC tRC(min) IOL=0mA, tCC= tCC(min) CKE VIL(max), tCC= tCC(min) CKE VIH(min), CS VIH(min), tCC= tCC(min) CKE VIL(max), tCC= tCC(min) CKE VIH(min), CS VIH(min), tCC= tCC(min) IOL=0mA ,tCC= tCC(min), Page Burst, All Banks activated. tRC tRFC CKE 0.2V Burst Length=4 tRC tRC(min) 256M GDDR3 SDRAM (0C Tc 85C ; VDD=1.8V + 0.1V, VDDQ=1.8V + 0.1V) Version -12 440 100 220 120 350 900 510 10 1050 -14 420 90 200 110 320 820 480 10 935 -16 410 80 180 100 310 750 460 10 860 -20 400 70 160 90 300 650 440 10 830 Unit mA mA mA mA mA mA mA mA mA IOL=0mA, tCC= tCC(min) Note : 1. Measured with outputs open and ODT off 2. Refresh period is 32ms 10.5 CAPACITANCE Parameter Input capacitance ( CK, CK ) Input capacitance (A0~A11, BA0~BA1) Input capacitance ( CKE, CS, RAS,CAS, WE ) Data & DQS input/output capacitance(DQ0~DQ31) Input capacitance(DM0 ~ DM3) (VDD=1.8V, TA= 25C, f=1MHz) Symbol CIN1 CIN2 CIN3 COUT CIN4 Min 1.5 1.5 1.5 1.5 1.5 Max 3 3 3 2 2 Unit pF pF pF pF pF 50 of 53 Rev. 1.1 November 2005 K4J55323QG 10.6 AC CHARACTERISTICS(I-I) Parameter DQS out access time from CK CK high-level width CK low-level width CL=11 CL=10 CK cycle time CL=9 CL=8 CL=7 WRITE Latency DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS Active termination setup time Active termination hold time DQS input high pulse width DQS input low pulse widthl Data strobe edge to Dout edge DQS read preamble DQS read postamble Write command to first DQS latching transition DQS write preamble DQS write preamble setup time DQS write postamble Half strobe period tWL tDH tDS tATS tATH tDQSH tDQSL tDQSQ tRPRE tRPST tDQSS tWPRE tWPRES tWPST tHP tCK 256M GDDR3 SDRAM -12 Min -0.23 0.45 0.45 1.25 1.4 1.6 2.0 2.0 6 0.16 0.16 10 10 0.48 0.48 -0.140 0.4 0.4 0.52 0.52 0.140 0.6 0.6 3.3 1.4 1.6 2.0 2.0 5 0.18 0.18 10 10 0.48 0.48 -0.160 0.4 0.4 0.52 0.52 0.160 0.6 0.6 3.3 Symbol tDQSCK tCH tCL -14 Max Min -0.26 0.45 0.45 -16 Max Min -0.29 0.45 0.45 1.6 2.0 2.0 5 0.20 0.20 10 10 0.48 0.48 0.180 0.4 0.4 0.4 0 0.4 tCLmin or tCHmin -20 Max Min -0.35 0.45 0.45 3.3 2.0 0.52 0.52 4 0.25 0.25 10 10 0.48 0.48 0.225 0.4 0.4 WL-0.2 Max +0.35 0.55 0.55 Unit ns tCK tCK ns ns Note +0.23 0.55 0.55 +0.26 0.55 0.55 +0.29 0.55 0.55 3.3 ns ns ns 0.52 0.52 0.225 0.6 0.6 WL+0.2 tCK ns ns ns ns tCK tCK ns tCK tCK tCK tCK ns tCK tCK 1 0.180 0.6 0.6 WL+0.2 WL-0.2 WL+0.2 WL-0.2 WL+0.2 WL-0.2 0.35 0 0.4 tCLmin or tCHmin tHP0.14 -0.3 -0.3 0.3 0.3 0.9 0.6 0.4 0 0.4 tCLmin or tCHmin tHP0.16 -0.3 -0.3 0.35 0.35 1.0 0.6 0.6 - 0.6 0.6 - 0.4 0 0.4 tCLmin or tCHmin 0.6 0.6 0.03 0.03 0.2 2 3 Data output hold time from DQS Data-out high-impedance window from CK and /CK Data-out low-impedance window from CK and /CK Address and control input hold time Address and control input setup time Address and control input pulse width Jitter over 1~6 clock cycle error Cycle to cyde duty cycle error Rise and fall times of CK tQH tHZ tLZ tIH tIS tIPW tJ tDCERR tR, tF 0.03 0.03 0.2 0.03 0.03 0.2 tHP0.18 -0.3 -0.3 0.4 0.4 1.1 - 0.03 0.03 0.2 tHP0.225 -0.3 -0.3 0.5 0.5 1.3 - ns ns ns ns ns ns tCK tCK tCK 5 4 4 Note : 1. The WRITE latency can be set from 1 to 7 clocks. When the WRITE latency is set to 1 or 2 or 3 clocks(this case can be used regardless of frequency), the input buffers are turned on during the ACTIVE commands reducing the latency but added power. When the WRITE latency is set to 4 ~7 clocks , the input buffers are turned on during the WRITE commands for lower power operation. The WRITE latency which is over 4 clocks can be used only in case that Write Latency*tCK is greater than 7ns. 2. A low to high transition on the WDQS line is not allowed in the half clock prior to the write preamble. 3. The last rising edge of WDQS after the write postamble must be riven high by the controller. WDQS can not be pulled high by the on-die termination alone. 4. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 5. The cycle to cycle jitter over 1~6 cycle short term jitter 51 of 53 Rev. 1.1 November 2005 K4J55323QG AC CHARACTERISTICS (II) Parameter Row active time Row cycle time Refresh row cycle time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Row active to Row active Last data in to Row precharge (PRE or Auto-PRE) Last data in to Read command Mode register set cycle time Auto precharge write recovery time + Precharge Exit self refresh to Read command Power-down exit time Refresh interval time Symbol tRAS tRC tRFC tRCDR tRCDW tRP tRRD tWR tCDLR tMRD tDAL tXSR tPDEX tREF 256M GDDR3 SDRAM -12 -14 -16 -20 Min Max Min Max Min Max Min Max 25 100K 22 100K 19 100K 15 100K 35 31 27 21 45 39 31 27 12 10 9 7 8 6 5 4 10 9 8 6 8 8 7 5 11 10 9 7 6 5 4 3 7 6 5 4 21 19 17 13 20000 20000 20000 20000 7tCK 6tCK 6tCK 4tCK +tIS +tIS +tIS +tIS 7.8 7.8 7.8 7.8 Unit Note tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK us 52 of 53 Rev. 1.1 November 2005 K4J55323QG 11.0 PACKAGE DIMENSIONS (FBGA) A1 INDEX MARK 256M GDDR3 SDRAM 14.0 11.0 0.8x11=8.8 0.12 Max 0.8 0.8 A B C D E F G H J K L M N P R T V 1234567 0.40 8 9 10 11 12 0.8x16=12.8 0.45 0.05 0.35 0.05 1.20 Max Ball existing Depopulated ball 53 of 53 Rev. 1.1 November 2005 |
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