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PRELIMINARY
APRIL 2006
XRK69774
REV. P1.0.1
1:14 LVCMOS PLL CLOCK GENERATOR
GENERAL DESCRIPTION
The XRK69774 is a PLL based LVCMOS Clock Generator targeted for high performance and low skew clock distribution applications. The XRK69774 can select between one of two reference inputs and provides 15 LVCMOS outputs 14 outputs (2 banks of 5 and 1 bank of 4) for clock distribution and 1 for feedback. The XRK69774 has two LVCMOS inputs to support clock redundancy. Switching the internal reference clock is controlled by the control input, CLK_SEL. The XRK69774 uses PLL technology to frequency lock its outputs to the input reference clock. The divider in the feedback path will determine the frequency of the VCO. Each of the separate output banks can individually divide down the VCO output frequency. This allows the XRK69774 to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. The outputs of the XRK69774 can be immobilized, in the low state, by use of the stop clock feature. Global output disabling and reset can be achieved with the control input MR/OE. The XRK69774 has an output frequency range of 8.33MHz
to125MHz and an input frequency range of 4.16MHz to 62.5MHz.
FEATURES
* Fully Integrated PLL * 15 LVCMOS outputs

2 banks with 5 outputs and 1 with 4 outputs each 1 dedicated feedback for frequency control Output Frequency of each Bank can be individually controlled
* * * * *
VCO Range 200MHz to 500MHz Output freq. range: 8.33MHz to 125MHz Max Output Skew of 175ps Max Cycle-to-cycle jitter: 90ps LVCMOS inputs for reference clock source
APPLICATIONS
* System Clock generator * Zero Delay Buffer
FIGURE 1. BLOCK DIAGRAM OF THE XRK69774
VDD
QA0 QA1 STOP CLK QA2 QA3 QA4
CLK0
0 0 Ref VCO 1
/2
Divider Select
0 /2, /4
CLK1 CLK_SEL
1
/4
1 /2, /4
PLL VDD 200-500MHz
/4, /6 /4, /6, /8, /12
QB0 FB_IN PLL_EN VCO_SEL FSEL_A FSEL_B QB4 FSEL_C FSEL_FB[1:0] 2 QC0 QC1 QC2 __________ STOP_CLK VDD QC3 FB STOP CLK QB1 QB2 QB3
VDD
STOP CLK
POR
QFB
___ MR/OE
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRK69774
1:14 LVCMOS PLL CLOCK GENERATOR
PRELIMINARY
REV. P1.0.1
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER XRK69774CR XRK69774IR PACKAGE TYPE 52-LEAD LQFP 52-LEAD LQFP OPERATING TEMPERATURE RANGE 0C to +70C -40C to +85C
FIGURE 2. PIN OUT OF THE XRK69774
VCO_SEL
GND
GND
GND
VDD
VDD
VDD 41
QC0
QC1
QC2
QC3
52 GND ___ MR/OE _________ STOP_CLK FSEL_B FSEL_C PLL_EN FSEL_A CLK_SEL CLK0 CLK1 NC VDD VDD_PLL 1 2 3 4 5 6 7 8 9 10 11 12 13 14
51
50
49
48
47
46
45
44
43
42
QB0 40 39 38 37 36 35 34
NC
GND QB1 VDD QB2 GND QB3 VDD QB4 FB_IN GND QFB VDD NC
XRK69774
33 32 31 30 29 28
15
16
17
18
19
20
21
22
23
24
25
27 26
VDD
VDD
GND
GND
GND
FSEL_FB0
2
FSEL_FB1
VDD
QA4
QA3
QA2
QA1
QA0
PRELIMINARY
REV. P1.0.1
XRK69774
1:14 LVCMOS PLL CLOCK GENERATOR
PIN DESCRIPTIONS
PIN # 1,15, 19, 24, 30, 35, 39, 43, 47, 51 2 NAME GND TYPE POWER Power supply ground DESCRIPTION
MR/OE
INPUT
Master reset and output enable. High = output enabled, Low = device reset & outputs tri-stated NOTE: 25k Pull-Up resistor.
3
STOP_CLK
INPUT
Clock input for serial control NOTE: 25k Pull-Up resistor.
7 4 5 6
FSEL_A, FSEL_B, FSEL_C PLL_EN
Select inputs for control of feedback divide value. INPUT INPUT NOTE: Each input has a 25k Pull-Down resistor. PLL bypass High = PLL Enabled. Low = PLL bypass NOTE: 25k Pull-Up resistor.
8
CLK_SEL
INPUT
CLK0 or CLK1 Select. High = CLK1 selected, Low = CLK0 selected NOTE: 25k Pull-Down resistor.
9 10 11, 27, 42 12, 17, 22, 26, 28, 33, 37, 41, 45, 49 13 14 20 16, 18,21, 23, 25 29 31
CLK0 CLK1 NC VDD
INPUT INPUT POWER
PLL Reference Clock Inputs NOTE: CLK1 has 25k Pull-Up resistor. CLK0 has 25k Pull-Down resistor.
NO CONNECT Power supply
VDD_PLL FSEL_FB0 FSEL_FB1 QA[4:0] QFB FB_IN
POWER INPUT INPUT OUTPUT OUTPUT INPUT
Analog supply for PLL Frequency Divider Select for QFB output NOTE: Each input has a 25k Pull-Down resistor. Clock outputs (Bank A) Feedback clock output Feedback input NOTE: 25k Pull-Up resistor.
32, 34, 36, 38, 40 44, 46, 48, 50 52
QB[4:0] QC[3:0] VCO_SEL
OUTPUT OUTPUT INPUT
Clock outputs (Bank B) Clock outputs (Bank C) VCO select. high = VCO/1, low = VCO/2. NOTE: 25k Pull-Down resistor.
3
XRK69774
1:14 LVCMOS PLL CLOCK GENERATOR 1.0 ELECTRICAL SPECIFICATIONS TABLE 1: GENERAL SPECIFICATIONS
SYMBOL VTT ESDMM ESDHBM LU CIN CHARACTERISTICS Output Termination Voltage ESD Protection (Machine model) ESD Protection (Human body model) Latch-up Immunity Input capacitance
PRELIMINARY
REV. P1.0.1
CONDITION
MIN
TYP
MAX
UNIT
VDD/2 200 2000 200 Per input 4
V V V mA pf
TABLE 2: ABSOLUTE MAXIMUM RATINGS
SYMBOL VDD VIN VOUT IIN IOUT TS CHARACTERISTICS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65
CONDITION MIN TYP MAX UNIT
-0.3 -0.3 -0.3
3.9 VDD + 0.3 VDD + 0.3 +/-20 +/-50 125
V V V mA mA C
TABLE 3: DC CHARACTERISTICS (VDD = 3.3V +/- 5%)
SYMBOL VDD_PLL VIH VIL VOH VOL ZOUT IPU CHARACTERISTICS PLL Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage
CONDITION MIN TYP MAX UNIT
LVCMOS LVCMOS LVCMOS IOH=-24mA IOL = 24mA IOL = 12mA
3.0 2.0
VDD VDD + 0.3 0.8
V V V V
2.4 0.55 0.30 14 -17
V
Output Impedance Input Pull-Up/Down Current VIN = GND or VDD @ V DD_PLL Pin All VDD pins
+200
A
IDD_PLL IDDQ
PLL Supply Current
5.0
7.5
mA
Quiescent Supply Current
8
mA
4
PRELIMINARY
REV. P1.0.1
XRK69774
1:14 LVCMOS PLL CLOCK GENERATOR
TABLE 4: AC CHARACTERISTICS (VDD = 3.3V +/- 5%)
SYMBOL fREF CHARACTERISTICS Input reference frequency
CONDITION MIN TYP MAX UNIT
/8 feedback /12 feedback /16 feedback /24 feedback /32 feedback /48 feedback PLL bypass mode
25.0 16.6 12.5 8.33 6.25 4.16
62.5 41.6 31.25 20.83 15.625 10.41 250
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ns
fVCO fMAX
VCO frequency range Output frequency /4 output /8 output /12 output /16 output /24 output
200 50.0 25.0 16.6 12.5 8.33 2.0 0.8V to 2.0V CLK to FB_IN fREF = 50MHz & FB = /8 Bank A (QAx to QAy) Bank B (QBx to QBy) Bank C (QCx to QCy) all outputs (QXy to QWz) 47 0.55 to 2.4V 0.1 50
500 125 62.5 41.6 31.25 20.83
tPW ItR, ItF t()
CLKx pulse width Input CLKx Rise/Fall time Propagation Delay (static phase offset)a Output to output skew
1
ns
-250
+100 100 125 100 175 53 1.0 10 10
ps ps ps ps ps % ns ns ns ps ps ps ps ps ps ps ps
tSK(O)
DC OtR, OtF tPLZ, tPHZ tPZL, tPZH tJIT(CC) tJIT(PER) tJIT()
Output duty cycle Output Rise/Fall time Output Disable Time Output Enable Time Cycle-to-Cycle Jitter Time Period Jitter I/O Phase Jitter (rms) VCO= 400MHz All outputs @ same frequency All outputs @ same frequency /8 feedback /12 feedback /16 feedback /24 feedback /32 feedback /48 feedback
90 90 15 49 18 22 26 34
NOTE: a. t() = +50ps (1/ (120 x fREF)) for any reference frequency.
5
XRK69774
1:14 LVCMOS PLL CLOCK GENERATOR
PRELIMINARY
REV. P1.0.1
TABLE 5: AC CHARACTERISTICS (VDD = 3.3V +/- 5%)
SYMBOL BW CHARACTERISTICS PLL closed loop bandwidth
CONDITION MIN TYP MAX UNIT
/8 feedback /12 feedback /16 feedback /24 feedback /32 feedback /48 feedback
0.50-1.80 0.30-1.00 0.25-0.70 0.17-0.40 0.12-0.30 0.07-0.20 10
MHz MHz MHz MHz MHz MHz ms
tLOCK
Maximum PLL Lock Time
FIGURE 3. TEST LOAD
Transmission Line Z = 50 50
VTT
6
PRELIMINARY
REV. P1.0.1
XRK69774
1:14 LVCMOS PLL CLOCK GENERATOR
2.0 CONFIGURATION TABLES TABLE 6: FUNCTION CONTROLS
CONTROL PIN MR/OE PLL_EN DEFAULT 1 1 LOGIC 0 Resets the output divide circuitry and serial interface, tri-states all outputs LOGIC 1 Enables all outputs - normal operation
PLL bypass mode enabled. This is a test PLL enabled - normal operation mode in which the reference clock is provided to the output dividers in place of the VCO output. QA[4:0], QB[4:0] and QC[3:0] outputs disabled Outputs enabled, normal operation in Low state. CLK0 selected as PLL reference VCO / 2 CLK1 selected VCO / 4
STOP_CLK CLK_SEL VCO_SEL
1 0 0
TABLE 7: BANK OUTPUT DIVIDER CONTROLS
INPUT VC0_SEL 0 0 1 1 FSEL_A 0 1 0 1 OUTPUT QA[4:0] /4 /8 /8 /16 INPUT VCO_SEL 0 0 1 1 FSEL_B 0 1 0 1 OUTPUT QB[4:0] /4 /8 /8 /16 INPUT VC0_SEL 0 0 1 1 FSEL_C 0 1 0 1 OUTPUT QC[3:0] /8 /12 /16 /24
TABLE 8: FEEDBACK DIVIDER CONTROL
VCO_SEL 0 0 0 0 1 1 1 1 FSEL_FB1 0 0 1 1 0 0 1 1 FSEL_FB0 0 1 0 1 0 1 0 1 QFB /8 /16 /12 /24 /16 /32 /24 /48
7
XRK69774
1:14 LVCMOS PLL CLOCK GENERATOR FIGURE 4. OUTPUT-TO-OUTPUT SKEW tSK(O)
PRELIMINARY
REV. P1.0.1
VCC VCC/2 GND VCC VCC/2 GND tSK(O)
The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device.
FIGURE 5. PROPOGATION DELAY (t(O), STATIC PHASE OFFSET) TEST REFERENCE
VCC CCLKx VCC/2 GND VCC FB_IN VCC/2 GND t(O)
FIGURE 6. OUTPUT DUTY CYCLE (DC)
VCC VCC/2 tp T0 DC=tP/T0 x 100%
The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
GND
FIGURE 7. I/O JITTER
CCLKx
FB_IN TJIT(I/O) = |T0-T1mean |
The deviation in t0 for a controlled edge with respect to a t 0 mean in a random sample of cycles
8
PRELIMINARY
REV. P1.0.1
XRK69774
1:14 LVCMOS PLL CLOCK GENERATOR
FIGURE 8. CYCLE-TO-CYCLE JITTER
TN
TN+1
TJIT(CC)= |TN-TN+1 |
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
FIGURE 9. PERIOD JITTER
T0
TJIT(Per)= |TN-1/f0 |
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles
FIGURE 10. OUTPUT TRANSITION TIME TEST REFERENCE
VCC=3.3V 2.4 0.55 OtF OtR
9
XRK69774
1:14 LVCMOS PLL CLOCK GENERATOR
PRELIMINARY
REV. P1.0.1
52 LEAD LOW-PROFILE QUAD FLAT PACK (10 mm x 10 mm X 1.4 mm LQFP, 1.0 mm Form)
Rev. 1.00
Note: The control dimension is in millimeters. INCHES MIN MAX 0.055 0.063 0.002 0.006 0.053 0.057 0.010 0.014 0.004 0.009 0.465 0.480 0.390 0.398 0.0256 BSC 0.029 0.041 0 7
SYMBOL A A1 A2 B C D D1 e L
MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.25 0.35 0.11 0.23 11.80 12.20 9.90 10.10 0.65 BSC 0.73 1.03 0 7
E
10
PACKAGE DIMENSIONS
PRELIMINARY
REV. P1.0.1
XRK69774
1:14 LVCMOS PLL CLOCK GENERATOR
REVISION HISTORY
REVISION # DATE DESCRIPTION
P1.0.0 P1.0.1
April 7, 2006 April 10, 2006
Initial release General Description edit last line to: ...input frequency range of 4.16MHz to 62.5MHz.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2006 EXAR Corporation Datasheet April 2006. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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