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3010
VOLTAGE-VARIABLE DELAY LINE TR < 1ns (SERIES 3010)
FEATURES
* * * * * * * Varactor Technology Fast rise time for high frequency applications Delay continuously adjustable from 2.4ns to 3.4ns Very narrow device (SIP package) Stackable for PC board economy Epoxy encapsulated Meets or exceeds MIL-D-23859C
1 IN
data 3 delay devices, inc.
3010 3 G 6 7 9 OUT
PACKAGE
VC G
3010-P: Positive control voltage 3010-N: Negative control voltage
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3010-series devices are continuously variable, single-input, singleIN Signal Input output, passive delay lines. The signal input (IN) is reproduced at the OUT Signal Output output (OUT), shifted by a time (TD) which is adjusted via an applied VC Control Voltage control voltage (VC). This control voltage is positive for the 3010-P and G Ground negative for the 3010-N. The characteristic impedance of the line is nominally 50 ohms. The rise time (TR) of the lines is no more than 1ns, resulting in a 3dB bandwidth of at least 300MHz. The delay resolution is limited only by that of the control voltage.
SERIES SPECIFICATIONS
* * * * * * * * * * Varactor voltage range (3010-P): 1.3V (max TD) to 11.3V (min TD) Varactor voltage range (3010-N): -1.3V (max TD) to -11.3V (min TD) Range of delay variation: 1.0ns minimum Minimum delay: 2.4ns 0.25ns Impedance: 45 - 68 Output rise time: 1.0ns max Bandwidth: 300MHz min 1.5 Overshoot/preshoot: 20% max Delay Operating temperature: -10C to +80C Impedance Temperature coefficient: 1000 PPM/C max
1.0
70
60
1.08 MAX
.150 MAX
Series 3010
IN G VC G OUT
Delay Variation (ns)
0.5
Impedance ()
50
.380 MAX .100 MIN
.200
.100 .800
.200
.020 DIA
0.0 1.3 6.3 11.3
40
Varactor Voltage (V)
Package Dimensions
Doc #04001
8/10/2005
Typical Delay/Impedance Variation
2004 Data Delay Devices
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3010
TYPICAL APPLICATIONS
Rin
IN
3010-P
VC
OUT G
r
G
r: Rin: Ro: Ro
Signal source impedance Input termination resistor Output termination resistor
+
1.3V - 11.3V*
* Set Ro to the median impedance value within the delay adjustment range (50 - 60) * Set Rin = Rout - r
*Reverse polarity for 3010-N.
Analog Interface
Vcc=0V
Vcc IN Vee G
Vcc
Vcc IN
1.6Ro
3010-P
VC
OUT G Vee Vee
3010-P
VC
OUT G
G
Ro
Vcc, Vee or -2V
2.6Ro
Vcc or Vee
+
0V - 10V Vcc
-2V
+
0V - 10V Vcc
Vee=-5.2V
Vcc=0V
Vcc IN Vee G
Vcc
Vcc IN
1.6Ro
3010-N
VC
OUT G Vee Vee
3010-N
VC
OUT G
G
Ro
Vcc, Vee or -2V 2.6V - 12.6V -2V Vcc or Vee 2.6V - 12.6V
2.6Ro
Vee=-5.2V
+
Vcc
+
Vcc
ECL with -2V Termination
ECL without -2V Termination
Note: The varicap voltage is referenced to the DC level of the input signal. In the case of ECL applications, a voltage of 0V to 10V (2.6V to 12.6V for the 3010-N) should be applied at pin 6, because the signal line has -1.3V DC level. This assumes the ECL signal has approximately 50% duty cycle.
Doc #04001
8/10/2005
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
3010
PASSIVE DELAY LINE TEST SPECIFICATIONS
TEST CONDITIONS
INPUT: Ambient Temperature: Input Pulse: Source Impedance: Rise/Fall Time: Pulse Width: Period: 25 C 3 C High = 1.8V typical Low = 0.8V typical 50 Max. 3.0 ns Max. (measured at 10% and 90% levels) PWIN = 500ns PERIN = 1000ns
o o
OUTPUT: Rload: Cload: Threshold:
50 <10pf 50% (Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PERIN PW IN TRISE INPUT SIGNAL
90% 50% 10%
TFALL VIH
90% 50% 10%
VIL DFALL TFALL
DRISE TRISE OUTPUT SIGNAL
90% 50% 10%
VOH
90% 50% 10%
VOL
Timing Diagram For Testing
OUT (50) PULSE GENERATOR TRIG
IN
DEVICE UNDER TEST (DUT) + VC
OUT
IN (50) TRIG OSCILLOSCOPE
Test Setup
Doc #04001
8/10/2005
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3

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