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| Crystal Clock Oscillators 32SMO (+2.5V,+3.0V or +3.3V FIXED MODELS) 32SMO Actual Size STANDARD SMD CLOCK OSCILLATORS STANDARD SPECIFICATIONS Item Generic part number Frequency range Frequency stability (-10C to 70C) over all conditions Operating Conditions Operating temperature Input voltage (VDD) Stand-by control voltage (Pin#1) Absolute Max. Rating Supply voltage Storage temperature Input current Stand-by current Output (-10C to 70C) Symmetry Rise and fall times "0" level "1" level Load Disable delay time Enable delay time Startup time Aging Jitter Specifications 32SMO 1.000 MHz to 100.000 MHz 32SMO(A) 32SMO(B) 32SMO(C) -10C to 70C (standard) -40C to 85C (W) 0.2V, 3.0V DC 0.3V or 3.3V DC VIH : 2.2VDD min. VIL : 0.8VDD max. -0.5V to 7.0V -50C to 125C 10 mA max. (Pin #1= Open or VIH) 50 A max.(Pin #1=VIL) 40% to 60% at 50%VDD level 5 ns max. (10%VDD to 90%VDD level) VOL : 10%VDD max. VOH : 90%VDD min. 15pF max. (CMOS) 150 ns max. 10 ms max. 10 ms max. 5 ppm max.at 25C 3C for first year 5pS max. 7pS max. 7pS max. 40pS max. 150C Deterministic jitter Random jitter Norm 1-sigma Peak to peak 240C 5C for 10 seconds 10C for 1 to 2 minutes (preheating) 100 ppm 50 ppm 30 ppm 2.5V DC 0.3V 32SMO 6.50.2 #4 #3 4.00.2 #1 #2 2.0max 1.7 #1 3.0 1.7 #2 0.05 1.2 1.5 #4 #3 PIN 1 2 3 4 CONNECTION "L" OPEN or "H" GND Z OUTPUT VDD Z: high impedance 0.05 1.2 Reflow soldering condition OUTPUT WAVEFORM TR VOH ("1"Level) TF VDD 90% or 80% VDD 50% VDD VOL ("0"Level) GND 10% or 20% VDD OV DC T Symmetry=t/T 100(%) Internal crystal oscillation to be halted (Pin#1=VIL). PACKAGE DATA Item Lid Base Sealing Terminal plating Package t 32SMO Metal Ceramic Seam/EB Gold TEST CIRCUIT Test Point VDD A #4 VDD SOLDERING PATTERN 1.3 1.0 1.3 1.1 TAPE SPECIFICATIONS 4.00.1 #3 OUTPUT GND + 1.5 0.1 -0 0.01 F 0.1 F E/D SW #1 #2 0.8 DC Power Supply 0.01 F 1.1 0.1 F M B F A V CL D TRI-STATE 1.750.1 L 2.00.1 J CL : including fixture and probe capacitance. 2.3 A B C D F J L M Reel Dia. Qty/Reel 178 1000pcs 3.5 2.8 8.0 3.5 4.0 1.0 0.3 1.4 C CLK OSC |
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