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| 74ACTQ541 Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs March 1993 Revised March 2005 74ACTQ541 Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs General Description The 74ACTQ541 is an octal buffer/line driver designed to be employed as memory and address drivers, clock drivers and bus oriented transmitter/receivers. This device is similar in function to the 74ACTQ244 while providing flow-through architecture (inputs on opposite side from outputs). This pinout arrangement makes this device especially useful as an output port for microprocessors, allowing ease of layout and greater PC board density. The 74ACTQ541 utilizes FACT Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to split ground bus for superior performance. Features s ICC and IOZ reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Inputs and outputs on opposite sides of package for easy board layout s Non-inverting 3-STATE outputs s Guaranteed 4 kV minimum ESD immunity s TTL compatible inputs s Outputs source/sink 24 mA Ordering Code: Order Number 74ACTQ541SC 74ACTQ541SCX_NL (Note 1) 74ACTQ541MTC 74ACTQ541PC MTC20 N20A Package Number M20B Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter "X" to the order code. Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. FACT, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation. (c) 2005 Fairchild Semiconductor Corporation DS010932 www.fairchildsemi.com 74ACTQ541 Logic Symbol IEEE/IEC Connection Diagram Pin Descriptions Pin Name OE1 - OE2 I0 -I7 O1 - O7 Pin Description 3-STATE Output Enable (Active-LOW) Inputs Outputs Truth Table Inputs OE1 L H X L H HIGH Voltage Level L LOW Voltage Level Outputs I H X X L H Z Z L OE2 L X H L X Immaterial Z High Impedance www.fairchildsemi.com 2 74ACTQ541 Absolute Maximum Ratings(Note 2) Supply Voltage (VCC) DC Input Diode Current (IIK) VI VI 0.5V to 7.0V 20 mA 20 mA 0.5V to VCC 0.5V Recommended Operating Conditions Supply Voltage VCC Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate 'V/'t VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns 4.5V to 5.5V 0V to VCC 0V to VCC 0.5V VCC 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO VO 40qC to 85qC 20 mA 20 mA DC Output Voltage (VO) 0.5V to VCC 0.5V r50 mA DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) DC Latch-up Source or Sink Current Junction Temperature (TJ) 0.5V VCC 0.5V r50 mA 65qC to 150qC r 300 mA 140qC Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 3.0 4.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC VOLP VOLV VIHD VILD Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 4) Maximum Quiescent Supply Current Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Plastic DIP package. Note 6: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND. Note 7: Max number of Data Inputs (n) switching. (n-1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD), f 1 MHz. TA Typ 1.5 1.5 1.5 1.5 2.99 4.49 25qC 2.0 2.0 0.8 0.8 2.9 4.4 3.86 4.86 TA 40qC to 85qC 2.0 2.0 0.8 0.8 2.9 4.4 3.76 4.76 0.1 0.1 0.44 0.44 Guaranteed Limits Units V V V VOUT VOUT Conditions 0.1V 0.1V or VCC 0.1V or VCC 0.1V IOUT 50 PA V VIN VIL or VIH (Note 3) IOH = 24 mA 24 mA IOUT 50 PA 0.002 0.001 0.1 0.1 0.36 0.36 V V VIN VIL or VIH (Note 3) IOH = 24 mA 24 mA VI VI VO VI VCC, GND V IL, VIH VCC, GND VCC 2.1V 1.65V Max 3.85V Min VCC or GND 5.5 5.5 5.5 5.5 5.5 5.5 5.0 5.0 5.0 5.0 1.1 0.6 r 0.1 r0.25 r 1.0 r2.5 1.5 75 PA PA mA mA mA VOLD VOHD VIN 75 4.0 1.5 40.0 PA V V V V Figure 1, Figure 2 (Note 5)(Note 6) Figure 1, Figure 2 (Note 5)(Note 6) (Note 5)(Note 7) (Note 5)(Note 7) 0.6 1.9 1.2 1.2 2.2 0.8 3 www.fairchildsemi.com 74ACTQ541 AC Electrical Characteristics VCC Symbol Parameter (V) (Note 8) tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Output to Output Skew Data to Output (Note 9) Output Disable Time Propagation Delay Data to Output Output Enable Time 5.0 5.0 5.0 Min 2.0 2.0 2.0 2.0 1.5 1.5 TA CL 25qC 50 pF Typ 4.5 5.5 5.0 6.5 5.5 5.5 0.5 0.5 Max 7.0 7.0 9.0 9.0 7.5 7.5 1.0 1.0 TA 40qC to 85qC CL 50 pF Max 7.5 7.5 9.5 9.5 8.0 8.0 1.0 1.0 ns ns ns ns Units Min 2.0 2.0 2.0 2.0 1.5 1.5 Note 8: Voltage Range 5.0 is 5.0V r 0.5V Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 70 Units pF pF VCC VCC OPEN 5.0V Conditions www.fairchildsemi.com 4 74ACTQ541 FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500:. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. VOLP/VOLV and VOHP/VOHV: * Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50: coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: * Monitor one of the switching outputs using a 50: coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. * Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability on the measurements. VOHVand VOLP are measured with respect to ground reference. Input pulses have the following characteristics: f ns, skew 150 ps. 1 MHz, tr 3 ns, tf 3 FIGURE 1. Quiet Output Noise Voltage Waveforms FIGURE 2. Simultaneous Switching Test Circuit 5 www.fairchildsemi.com 74ACTQ541 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 6 74ACTQ541 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com 74ACTQ541 Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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