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74LVT162240 * 74LVTH162240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25: Series Resistors in the Outputs
June 1999 Revised June 2005
74LVT162240 * 74LVTH162240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25: Series Resistors in the Outputs
General Description
The LVT162240 and LVTH162240 contain sixteen inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Individual 3-STATE control inputs can be shorted together for 8-bit or 16-bit operation. The LVT162240 and LVTH162240 are designed with equivalent 25: series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The LVTH162240 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These inverting buffers and line drivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT162240 and LVTH162240 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at 5V VCC s Outputs include equivalent series resistance of 25: to make external termination resistors unnecessary and reduce overshoot and undershoot s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH162240), also available without bushold feature (74LVT162240) s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Functionally compatible with the 74 series 162240 s Latch-up performance exceeds 500 mA s ESD performance:
Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V
Ordering Code:
Order Number 74LVT162240MEA (Note 1) 74LVT162240MTD (Note 1) 74LVTH162240MEA 74LVTH162240MEX (Note 2) 74LVTH162240MTD 74LVTH162240MTX (Note 2) Package Number MS48A MTD48 MS48A MS48A MTD48 MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TUBE] 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBE] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL]
Note 1: Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Note 2: Use this Order Number to receive devices in Tape and Reel.
(c) 2005 Fairchild Semiconductor Corporation
DS012490
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74LVT162240 * 74LVTH162240
Logic Symbol
Pin Descriptions
Pin Names OEn I0-I15 O0-O15 Description Output Enable Inputs (Active LOW) Inputs 3-STATE Outputs
Truth Table Connection Diagram
OE1 L L H Inputs OE2 L L H Inputs OE3 L L H Inputs OE4 L L H
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance
Inputs I0-I3 L H X
Outputs O0-O3 H L Z Outputs I4-I7 L H X O4-O7 H L Z Outputs I8-I11 L H X O8-O11 H L Z Outputs I12-I15 L H X O12-O15 H L Z
Functional Description
The LVT162240 and LVTH162240 contain sixteen inverting buffers with 3-STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVT162240 * 74LVTH162240
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 4) VI GND VO GND VO ! VCC Output at HIGH State VO ! VCC Output at LOW State V mA mA mA mA mA
0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 50 50
64 128
r64 r128 65 to 150
qC
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH-Level Output Current LOW-Level Output Current Free Air Operating Temperature Input Edge Rate, VIN 0.8V-2.0V, VCC 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA mA
12
12
40
0
85
10
qC
ns/V
't/'V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol Parameter VCC (V) 2.7 2.7-3.6 2.7-3.6 2.7-3.6 3.0 VOL II(HOLD) (Note 6) II(OD) (Note 6) II Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZH IOZH ICCH ICCL ICCZ Power Off Leakage Current Power Up/Down 3-STATE Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current 3.0 3.6 3.6 3.6 0 0-1.5V 3.6 3.6 3.6 3.6 3.6 3.6 Output LOW Voltage Bushold Input Minimum Drive 2.7 3.0 3.0 75 VCC0.2 2.0 0.2 0.8 2.0 0.8 TA Min
40qC to 85qC
Typ (Note 5) Max Units Conditions
VIK VIH VIL VOH
Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage
1.2
V V V V V
II
18 mA
VO d 0.1V or VO t VCC 0.1V IOH IOH IOL IOL VI VI
100 PA 12 mA
100 PA 12 mA 0.8V 2.0V
75
500
PA PA
10
(Note 7) (Note 8) VI 5.5V 0V or VCC 0V VCC 0.5V to 3.0V GND or VCC 0.5V 3.0V VI VI VI
500 r1 5
1
PA
r100 r100 5
5 10 0.19 5 0.19
PA PA PA PA PA
mA mA mA
0V d VI or VO d 5.5V VO VI VO VO
VCC VO d 5.5V Outputs HIGH Outputs LOW Outputs Disabled
3
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74LVT162240 * 74LVTH162240
DC Electrical Characteristics
Symbol ICCZ Parameter Power Supply Current Increase in Power Supply Current (Note 9)
Note 5: All typical values are at VCC 3.3V, TA 25qC. Note 6: Applies to bushold versions only (74LVTH162240).
(Continued)
TA Min
VCC (V)
40qC to 85qC
Typ (Note 5) Max Units Conditions VCC d VO d 5.5V, Outputs Disabled One Input at V CC 0.6V Other Inputs at V CC or GND
3.6 3.6
0.19 0.2
mA mA
'ICC
Note 7: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 8: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 9: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3
(Note 10)
TA Min 25qC Units Typ 0.8 Max V V CL Conditions 50 pF, RL (Note 11) (Note 11) 500:
0.8
Note 10: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 11: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
TA Symbol Parameter Min tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Output to Output Skew (Note 13)
3.3V, TA 25qC.
40qC to 85qC, CL
3.3V r 0.3V Typ (Note 12) Max 4.0 4.0 4.8 4.9 4.9 4.5 1.0
50 pF, RL
500: 2.7V Max 4.8 4.6 5.7 6.1 5.4 4.5 1.0 Units
VCC
VCC Min 1.0 1.0 1.0 1.0 2.0 2.0
Propagation Delay Data to Output Output Enable Time Output Disable Time
1.0 1.0 1.0 1.0 2.0 2.0
ns ns ns ns
Note 12: All typical values are at VCC
Note 13: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance
Symbol CIN COUT
(Note 14)
Parameter Conditions VCC VCC 0V, VI 0V or VCC 0V or VCC 3.0V, VO Typical 4 8 Units pF pF
Input Capacitance Output Capacitance
Note 14: Capacitance is measured at frequency f
1 MHz, per MIL-STD-883, Method 3012.
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4
74LVT162240 * 74LVTH162240
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
5
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74LVT162240 * 74LVTH162240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25: Series Resistors in the Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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