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A3995 DMOS Dual Full Bridge PWM Motor Driver
Features and Benefits
36Voutputrating 2.4Adcmotordriver Synchronousrectification Internalundervoltagelockout(UVLO) Thermalshutdowncircuitry Crossover-currentprotection VerythinprofileQFNpackage
Description
The A3995 is designed to drive two dc motors at currents up to 2.4 A. Capable of drive voltages up to 36 V, the A3995 includes two independent fixed off-time PWM current regulators that operate in either fast or slow decay mode, as determined by the MODE input. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Protection features include: thermal shutdown with hysteresis, undervoltage lockout (UVLO) and crossover current protection. Special power-up sequencing is not required. The A3995 is supplied in a 36 pin QFN package (suffix EV) with exposed power tab for enhanced thermal performance. It has a 6 mm x 6 mm footprint, with a nominal overall package height of 0.90 mm, and is lead (Pb) free, with 100% matte tin leadframe plating.
Package: 36 pin QFN 0.90 mm nominal height (suffix EV)
Approximate scale 1:1
Typical Application Diagram
CP1 VDD
CP2
VCP
VBB
VBB OUT1A OUT1A OUT1B OUT1B SENSE1 SENSE1
MODE1 PHASE1 Microcontroller or Controller Logic ENABLE1 VREF1 MODE2 PHASE2 ENABLE2 VREF2
A3995
OUT2A OUT2A OUT2B OUT2B
GND
GND
GND
A3995DS
GND
SENSE2 SENSE2
A3995
Selection Guide
Part Number A3995SEV-T A3995SEVTR-T 61 pieces per tube 1500 pieces per reel
DMOS Dual Full Bridge PWM Motor Driver
Packing
Absolute Maximum Ratings
Characteristic Load Supply Voltage Logic Supply Voltage Output Current* Logic Input Voltage Range SENSEx Pin Voltage VREFx Pin Voltage Operating Temperature Range Junction Temperature Storage Temperature Range Symbol VBB VDD IOUT VIN VSENSEx VREFx TA TJ(max) Tstg Range S Pulsed tw < 1s Continuous Pulsed tw < 1s Pulsed tw < 1 s Notes Rating -0.5 to 36 38 -0.4 to 7 .4 3.5 -0.3 to 7 0.5 .5 .5 -0 to 85 150 -55 to 150 Units V V V A A V V V V C C C
* May be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a Junction Temperature of 150C.
Thermal Characteristics (may require derating at maximum conditions)
Characteristic Package Thermal Resistance Symbol RJA Test Conditions EV package, 4 layer PCB based on JEDEC standard Min. Units 7 C/W
Power Dissipation versus Ambient Temperature
5500 5000 4500 4000
Power Dissipation, PD (mW)
3500 3000 2500 2000 1500 1000 500 0 25 50 75 100 125 Temperature (C) 150 175
EV Package 4-layer PCB (R JA = 27 C/W)
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A3995
DMOS Dual Full Bridge PWM Motor Driver
Functional Block Diagram
VCP
VBB
VDD
OSC
CHARGE PUMP
VCP
DMOS Full Bridge 1
MODE1 PHASE1 ENABLE1 CONTROL LOGIC GATE DRIVE
VBB
CP1
CP1
OUT1A OUT1A OUT1B OUT1B
Sense1 VREF1 3
-
PWM Latch BLANKING
SENSE1 SENSE1
+
VCP
DMOS Full Bridge 2
RS1
MODE2 PHASE2 ENABLE2 CONTROL LOGIC GATE DRIVE OUT2A OUT2A OUT2B OUT2B
Sense2 VREF2 3
GND
GND
GND
GND
+
-
PWM Latch BLANKING Sense2 SENSE2 SENSE2
NC
NC
NC
NC
NC
NC
RS2
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3995
Characteristics
DMOS Dual Full Bridge PWM Motor Driver
Symbol VBB VDD IDD RDS(on) IDSS IBB VIN(1) VIN(0) IIN Vhys PWM change to source on tpd tCOD tBLANK VREFx IREF VUV(VBB) VUV(VBB)hys VUV(VDD) VUV(VDD)hys TJTSD TJTSDhys VDD rising Operating VREF = 1.5 VBB rising PWM change to source off PWM change to sink on PWM change to sink off VIN = 0 to 5 V Source driver, IOUT = -1. A, TJ = 5C Sink driver, IOUT = 1. A, TJ = 5C IOUT = 1. A Outputs, VOUT = 0 to VBB IOUT = 0 mA, outputs on, PWM = 50 kHz, DC = 50% Test Conditions Min. 8.0 3.0 - - - - -0 - 0.7xVDD - -0 150 350 35 350 35 300 .5 0.0 - 7.3 400 .65 75 155 - Typ. - - 7 350 350 - - - - - <1.0 300 550 - 550 - 45 3. - - 7.6 500 .8 105 165 15 Max. 36 5.5 10 450 450 1. 0 8 - 0.3xVDD 0 500 1000 300 1000 50 1000 4 1.5 1 7.9 600 .95 15 175 - Units V V mA m m V A mA V V A mV ns ns ns ns ns s V A V mV V mV C C
ELECTRICAL CHARACTERISTICS1, valid at TA = 25 C, VBB = 36 V, unless otherwise noted Load Supply Voltage Range Logic Supply Voltage Range VDD Supply Current Output On Resistance Vf , Outputs Output Leakage VBB Supply Current Control Logic Logic Input Voltage Logic Input Current Input Hysteresis Operating Operating
Propagation Delay Times
Crossover Delay Blank Time VREFx Pin Input Voltage Range VREFx Pin Reference Input Current Protection Circuits VBB UVLO Threshold VBB Hysteresis VDD UVLO Threshold VDD Hysteresis Thermal Shutdown Temperature Thermal Shutdown Hysteresis
1For Typical
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 3V ERR = [(VREF/3) - VSENSE] / (VREF/3).
DC Control Logic PHASE ENABLE MODE OUTA OUTB Function 1 1 1 H L Forward (slow decay SR) 1 1 0 H L Forward (fast decay SR) 0 1 1 L H Reverse (slow decay SR) 0 1 0 L H Reverse (fast decay SR) X 0 1 L L Brake (slow decay SR) 1 0 0 L H Fast decay SR* 0 0 0 H L Fast decay SR* * To prevent reversal of current during fast decay SR - the outputs will go to the high impedance state as the current gets near zero.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3995
DMOS Dual Full Bridge PWM Motor Driver
Logic Timing Diagram, DC Driver
ENB
PH
MODE VBB
OUTA
0V
VBB
OUTB
0V
IOUT
0A
A
1
2
3
4
5
6
7
8
9
VBB 15 6 OutA 3 24 OutB OutA 8
VBB
7 OutB
9
A
Charge Pump and VREG Power-up Delay ( 200 s)
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3995
DMOS Dual Full Bridge PWM Motor Driver
Functional Description
Device Operation The A3995 is designed to operate two
dc motors. The currents in each of the output full-bridges, all N-channel DMOS, are regulated with fixed off-time pulse width modulated (PWM) control circuitry. The peak current to each full bridge is set by the value of an external current sense resistor, RSx , and a reference voltage, VREFx . If the logic inputs are pulled up to VDD, it is good practice to use a high value pullup resistor in order to limit current to the logic inputs should an overvoltage event occur. Logic inputs include: PHASEx, ENABLEx, and MODE.
Control Logic Dc motor commutation is accomplished by
applying a PWM signal together with the PHASE or ENABLE inputs. Fast or slow current decay during the off-time is selected via the MODE pin. Synchronous Rectification is always active regardless of the state of the MODE pin.
Charge Pump (CP1 and CP2) The charge pump is used to
Internal PWM Current Control Each full-bridge is con-
generate a gate supply greater than the VBB in order to drive the source-side DMOS gates. A 0.1 F ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1 F ceramic capacitor is required between VCP and VBBx to act as a reservoir to operate the high-side DMOS devices.
trolled by a fixed off-time PWM current control circuit that limits the load current to a desired value, ITRIP . Initially, a diagonal pair of source and sink DMOS outputs are enabled and current flows through the motor winding and RSx. When the voltage across the current sense resistor equals the voltage on the VREFx pin, the current sense comparator resets the PWM latch, which turns off the source driver. The maximum value of current limiting is set by the selection of RS and the voltage at the VREF input with a transconductance function approximated by: ITripMax = VREF / (3xRS) Note: It is critical to ensure that the maximum rating of 500 mV on each SENSEx pin is not exceeded.
Shutdown In the event of a fault (excessive junction tem-
perature, or low voltage on VCP), the outputs of the device are disabled until the fault condition is removed. At power-up, the undervoltage lockout (UVLO) circuit disables the drivers.
Synchronous Rectification When a PWM-off cycle is
triggered by an internal fixed off-time cycle, load current will recirculate. The A3995 synchronous rectification feature will turn on the appropriate MOSFETs during the current decay. This effectively shorts the body diode with the low RDS(on) driver. This significantly lowers power dissipation. When a zero current level is detected, synchronous rectification is turned off to prevent reversal of the load current.
Fixed Off-Time The internal PWM current control circuitry
MODE Control input MODE is used to toggle between fast
uses a one shot circuit to control the time the drivers remain off. The one shot off-time, toff , is internally set to 30 s.
decay mode and slow decay mode. A logic high puts the device in slow decay mode. Synchronous rectification is always enabled when ENABLE is low.
Blanking This function blanks the output of the current sense
comparator when the outputs are switched by the internal current control circuitry. The comparator output is blanked to prevent false detections of overcurrent conditions, due to reverse recovery currents of the clamp diodes, or to switching transients related to the capacitance of the load. The driver blank time, tBLANK , is approximately 3 s.
Braking The Braking function is implemented by driving the
Phase Input (PHASEx) The state of the PHASEx input
determines the direction of rotation of the motor.
device in slow decay mode via the MODE pin and applying an ENABLE chop command. Because it is possible to drive current in both directions through the DMOS switches, this configuration effectively shorts the motor-generated BEMF as long as the ENABLE chop mode is asserted. The maximum current can be approximated by VBEMF/RL. Care should be taken to ensure that the maximum ratings of the device are not exceeded in worst case braking situations: high speed and high inertia loads.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3995
DMOS Dual Full Bridge PWM Motor Driver
A low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. The recommended PCB layout shown in the diagram below, illustrates how to create a star ground under the device, to serve both as low impedance ground point and thermal path. The two input capacitors should be placed in parallel, and as close to the device supply pins as possible. The ceramic capacitor should be closer to the pins than the bulk capacitor. This is necessary because the ceramic capacitor will be responsible for delivering the high frequency current components.
Motor Configurations For applications that require either a
stepper/dc motor driver or dual stepper motor driver, Allegro offers the A3989 and A3988. These devices are offered in the same QFN package as the A3995. The A3988 is capable of driving 2 bipolar stepper motors at output currents up to 1.2 A. The stepper control logic is industry standard parallel communication. Please refer to the Allegro website for further information and datasheets about those devices.
Layout The printed circuit board should use a heavy ground-
plane. For optimum electrical and thermal performance, the A3995 must be soldered directly onto the board. On the underside of the A3995 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB.
Sense Pins The sense resistors, RSx, should have a very
Grounding In order to minimize the effects of ground bounce
and offset issues, it is important to have a low impedance singlepoint ground, known as a star ground, located very close to the device. By making the connection between the exposed thermal pad and the groundplane directly under the A3995, that area becomes an ideal location for a star ground point.
VBB CVCP GND
low impedance path to ground, because they must carry a large current while supporting very accurate voltage measurements by the current sense comparators. Long ground traces will cause additional voltage drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. As shown in the layout below, the SENSEx pins have very short traces to the RSx resistors and very thick, low impedance traces directly to the star ground underneath the device. If possible, there should be no other components on the sense circuits. Note: When selecting a value for the sense resistors, be sure not to exceed the maximum voltage on the SENSEx pins of 500 mV.
VBB CVCP CCP CIN3
ENABLE2
ENABLE1
VCP
CP2
GND
CP1
GND
NC
RS1
RS2
1
NC
MODE2
OUT1B
U1
OUT1A
OUT2B
RS1 CIN1
SENSE1 OUT1B VBB OUT1B SENSE1 OUT1A PHASE2 NC
A3995
PAD
OUT2A SENSE2 OUT2B VBB OUT2B SENSE2 OUT2A PHASE1 NC GND
MODE1
CCP
GND
CIN3
RS2 CIN2
CIN1
CIN2
VREF1
CVDD1
CVDD1
GND VDD CVDD2
CVDD2
EV package layout shown. Figure 5. Printed circuit board layout with typical application circuit, shown at right. The copper area directly under the A3995 (U1) is soldered to the exposed thermal pad on the underside of the device. The thermal vias serve also as electrical vias, connecting it to the ground plane on the other side of the PCB , so the two copper areas together form the star ground.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
GND
VDD
NC
NC
OUT1A
OUT2A
VREF2
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A3995
DMOS Dual Full Bridge PWM Motor Driver
Pin-out Diagram
25 SENSE2
21 SENSE2
27 MODE2
26 OUT2A
24 OUT2B
22 OUT2B
20 OUT2A
23 VBB
19 NC
MODE1 28 NC 29 GND 30 VCP 31 CP1 32 CP2 33 GND 34 ENABLE1 35 ENABLE2 36 1 2 3 4 5 6 7 8 9 PAD
18 17 16 15 14 13 12 11 10
GND PHASE1 GND NC VREF2 VREF1 NC VDD PHASE2
OUT1A
OUT1B
SENSE1
OUT1B
SENSE1
OUT1A
VBB
NC
Terminal List Table
Number 1 3 4 5 6 7 8 9 10 11 1 13 14 15 16 17 18 19 0 1 3 4 5 6 7 8 9 30 31 3 33 34 35 36 - Name NC OUT1A SENSE1 OUT1B VBB OUT1B SENSE1 OUT1A NC PHASE VDD NC VREF1 VREF NC GND PHASE1 GND NC OUTA SENSE OUTB VBB OUTB SENSE OUTA MODE MODE1 NC GND VCP CP1 CP GND ENABLE1 ENABLE PAD Description No Connect DMOS Full Bridge 1 Output A Sense Resistor Terminal for Bridge 1 DMOS Full Bridge 1 Output B Load Supply Voltage DMOS Full Bridge 1 Output B Sense Resistor Terminal for Bridge 1 DMOS Full Bridge 1 Output A No Connect Control Input Logic Supply Voltage No Connect Analog Input Analog Input No Connect Ground Control Input Ground No Connect DMOS Full Bridge Output A Sense Resistor Terminal for Bridge DMOS Full Bridge Output B Load Supply Voltage DMOS Full Bridge Output B Sense Resistor Terminal for Bridge DMOS Full Bridge Output A Control Input Control Input No Connect Ground Reservoir Capacitor Terminal Charge Pump Capacitor Terminal Charge Pump Capacitor Terminal Ground Control Input Control Input Exposed pad for enhanced thermal performance. Should be soldered to the PCB
NC
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3995
DMOS Dual Full Bridge PWM Motor Driver
EV Package, 36 Pin QFN with Exposed Thermal Pad
Preliminary dimensions, for reference only (reference JEDEC MO-220VJJD-1, except exposed thermal pad) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P600X600X100-37V1M); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
6.15 .242 5.85 .230 36 A
A B
1 2
6.15 .242 5.85 .230
36X 0.08 [.003] C 36X 0.30 .012 0.18 .007 0.10 [.004] M C A B 0.05 [.002] M C 0.50 .020
SEATING PLANE 1.00 .039 0.80 .031 0.20 .008 REF 0.05 .002 0.00 .000
C
0.25 .010 NOM 1.15 .045 NOM 1 2 4X0.20 .008 MIN 36
32X0.20 .008 MIN 0.50 .020 NOM
0.75 .030 0.35 .014
C 4.15 .163 NOM
5.8 .228 NOM R0.30 .012 REF 2 1 36 4.15 .163 NOM
4.15 .163 NOM
4X0.20 .008 MIN
4.15 .163 NOM 5.8 .228 NOM
The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright(c) 2006 AllegroMicrosystems, Inc.
For the latest version of this document, visit our website: www.allegromicro.com
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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