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A48P4616
Preliminary
Document Title 16M X 16 Bit DDR DRAM Revision History
Rev. No.
0.0
16M X 16 Bit DDR DRAM
History
Initial issue
Issue Date
September 5, 2005
Remark
Preliminary
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Features
CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 (5T) 166 200 DDR333 (6K) 133 166 DQS is edge-aligned with data for reads and is centeraligned with data for writes. Differential clock inputs (CK and CK) Four internal banks for concurrent operation. Data mask (DM) for write data. DLL aligns DQ and DQS transitions with CK transitions. Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS. Burst lengths: 2, 4, or 8 CAS Latency: 2/2.5(DDR333), 2.5/3(DDR400) Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.8s Maximum Average Periodic Refresh Interval 2.5V (SSTL_2 compatible) I/O VDD = VDDQ = 2.5V 0.2V (DDR333) VDD = VDDQ = 2.6V 0.1V (DDR400) Available in Halogen and Lead Free packaging
DDR 256M bit, die C, based on 110nm design rules. Double data rate architecture: two data transfers per clock cycle. Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
General Description
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edgealigned with data for Reads and center-aligned with data for Writes. The 256Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going high and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4, or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided along with a power-saving Power Down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II com-patible. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
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Pin Configuration
TSOP (II)
Column Address Table
Organization 64Mb x 4 32Mb x 8 16Mb x16 Coiumn Addres A0-A9, A11 A0-A9 A0-A8
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Block Diagram (64Mb x 4)
Note: 1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 2. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
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Block Diagram (32Mb x 8)
Note: 1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 2. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
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Block Diagram (16Mb x 16)
Note: 1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 2. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
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Pin Descriptions
Symbol Type Description Clock: CK and CK are differential clock inputs. All address and control input signals CK, CK Input are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self Refresh operation (all banks idle), or Active Power Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during Power Down. Input buffers, excluding CKE, are disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might include CKE1 on a different pin, in addition to CKE0, to facilitate independent power down control of stacked devices. Chip Select: All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of CS , CS0 , CS1 Input the command code. The standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in addition to CS0 , to allow upper or lower deck selection on stacked devices.
RAS , CAS , WE
CKE, CKE0, CKE1
Input
Input
Command Inputs: RAS , CAS , WE (along with CS ) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. During a Read, DM can be driven high, low, or floated. Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 and BA1 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs: Provide the row address for Active commands, and the column address and Auto Precharge bit for Read/Write commands, to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode Register Set command. Data Input/Output: Data bus. Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15 No Connect: No internal electrical connection is present.
DM
Input
BS0, BS1
Input
A0-A12
Input
DQ DQS. LDQS, UDQS NC NU VDDQ VSSQ VDD VSS VREF
Input / Output Input / Output
Electrical connection is present. Should not be connected at second level of assembly. Supply Supply Supply Supply Supply
DQ Power Supply: 2.5V 0.2V. DQ Ground Power Supply: 2.5V 0.2V. Ground SSTL_2 reference voltage: (VDDQ / 2) 1%.
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Functional Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The doubledata-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
Initialization
Only one of the following two conditions must be met. * No power sequencing is specified during power up or power down given the following criteria: VDD and VDDQ are driven from a single power converter output VTT meets the specification A minimum resistance of 42 ohms limits the input current from the VTT supply into any pin and VREF tracks VDDQ /2 or * The following relationships must be followed: VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3V VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3V VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3V The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200s delay prior to applying an executable command. Once the 200s delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be brought HIGH. Following the NOP command, a Precharge ALL command must be applied. Next a Mode Register Set command must be issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command must be issued for the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and any read command. A Precharge ALL command should be applied, placing the device in the "all banks idle" state Once in the idle state, two auto refresh cycles must be performed. Additionally, a Mode Register Set command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation. DDR SDRAM's may be reinitialized at any time during normal operation by asserting a valid MRS command to either the base or extended mode registers without affecting the contents of the memory array. The contents of either the mode register or extended mode register can be modified at any valid time during device operation without affecting the state of the internal address refresh counters used for device refresh.
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Register Definition
Mode Register Burst Length
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements results in unspecified operation.
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both Read and Write bursts.
Mode Register Operation BA1
0* BA0 0* A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 BT A2 A1 A0 Address Bus Mode Register
Operating Mode
CAS Latency CAS Latency
Burst Length
Operating Mode
A12-A9 A8 A7 A6-A0 Type A6
A3 Burst Type Type
Burst Length A2 A1 A0 Type
A5
A4
0 1
Sequential Interleave
0 0 0 -
0 1 0 -
0 0 1 -
Valid Valid VS**
Normal operation Do not reset DLL Normal operation in DLL Reset Vendor-Specific Test Mode Reserved
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Reserved Reserved 2 3 (Option) Reserved 1.5 (Option) 2.5 Reserved
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Reserved 2 4 8 Reserved Reserved Reserved Reserved
Note: 1. VS** Vendor Specific 2. * BA0 and BA1 must be 0, 0 to select the Mode Register (vs. the Extended Mode Register).
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Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definition on page 10.
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks. If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Burst Definition
Burst Length A2 Starting Column Address A1 A0 Order of Accesses Within a Burst Type = Sequential Type = Interleaved
2 0 4 0 1 1 0 0 0 8 0 1 1 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1
0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
Note: 1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block. 3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
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Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set command to select normal operating mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result.
CAS Latencies
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Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2 (NTC optional). These functions are controlled via the bit settings shown in the Extended Mode Register Definition. The Extended Mode Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before a Read command can be issued. This is the reason for introducing timing parameter tXSRD for DDR SDRAM's (Exit Self Refresh to Read Command). Non- Read commands can be issued 2 clocks after the DLL is enabled via the EMRS command (tMRD) or 10 clocks after the DLL is enabled via self refresh exit command (tXSNR, Exit Self Refresh to Non-Read Command).
QFC Enable/Disable Output Drive Strength
The QFC signal is an optional DRAM output control used to isolate module loads (DIMMs) from the system memory bus by means of external FET switches when the given module (DIMM) is not being accessed. The QFC function is an optional feature for NANYA and is not included on all DDR SDRAM devices. The normal drive strength for all outputs is specified to be SSTL_2, Class II.
Extended Mode Register Definition
BA1
0*
BA0 1*
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2 QFC
A1 DS
A0 DLL
Address Bus Extended Mode Register
Operating Mode
Operating Mode A12-A3 A2-A0 Type
A2
QFC
Drive Strength A1 Type
A0
DLL
0 1
Disable Enable (Optional)
0 1
Enable Disable
0 -
Valid -
Normal Operation All Other States Reserved
0 1
Normal Reserved
Note: * BA0 and BA1 must be 1, 0 to select the Extended Mode Register (vs. the base Mode Register)
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Commands
Truth Tables 1a and 1b prvide a reference of the commands supported by DDR SDRAM device. A verbal description of each commands follows.
Name (Function)
CS RAS CAS
WE
Address
MNE
Note
Deselect (Nop) No Openration (Nop) Active (Select Bank And Activate Row) Read (Select Bank And Activate Column, And Start Read Burst) Write (Select Bank And Activate Column, And Start Write Burst) Burst Terminate Precharge (Deactivate Row In Bank Or Banks) Auto Refresh Or Self Refresh (Enter Self Refresh Mode) Mode Register Set
H L L L L L L L L
X H L H H H L L L
X H H L L H H L L
X H H H L L L H L
X X Bank/Row Bank/Col Bank/Col X Code X Op-Code
NOP NOP ACT Read Write BST PRE AR/SR MRS
1, 9 1, 9 1, 3 1, 4 1, 4 1, 8 1, 5 1, 6, 7 1, 2
Note: 1. CKE is high for all commands shown except Self Refresh. 2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode Register.) 3. BA0-BA1 provide bank address and A0-A12 provide row address. 4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the Auto Precharge feature (non-persistent), A10 low disables the Auto Precharge feature. 5. A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are "Don't Care." 6. This command is auto refresh if CKE is high; Self Refresh if CKE is low. 7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto Precharge enabled or for write bursts 9. Deselect and NOP are functionally interchangeable. Truth Table 1b: DM Operation Name (Function) DM DQs Note
Write Enable Write Inhibit
L H
Valid X
1 1
Note: Used to mask write data; provided coincident with the corresponding data.
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Deselect The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. No Operation (NOP)
The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. If Auto Precharge is selected, the row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte/column location.
Precharge
The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write commands being issued to that bank. A precharge command is treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging.
Mode Register Set
The mode registers are loaded via inputs A0-A12, BA0 and BA1 while issuing the Mode Register Set Command. See mode register descriptions in the Register Definition section. The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met.
Active
The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before opening a different row in the same bank.
Auto Precharge
Auto Precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read or Write command. A precharge of the bank/row that is addressed with the Read or Write command is automatically performed upon completion of the Read or Write burst. Auto Precharge is non-persistent in that it is either enabled or disabled for each individual Read or Write command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This is determined as if an explicit Precharge command was issued at the earliest possible time without violating tRAS(min). The user must not issue another command to the same bank until the precharge (tRP) is completed. The NTC DDR SDRAM devices supports the optional tRAS lockout feature. This feature allows a Read command with Auto Precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS(min) specification. The tRAS lockout feature essentially delays the onset of the auto precharge operation until two conditions occur. One, the entire burst length of data has been successfully prefetched from the memory array; and two, tRAS(min) has been satisfied.
Read
The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don't care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open for subsequent accesses.
Write
The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don't care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used.
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As a means to specify whether a DDR SDRAM device supports the tRAS lockout feature, a new parameter has been defined, tRAP (RAS Command to Read Command with Auto Precharge or better stated Bank Activate to Read Command with Auto Precharge). For devices that support the tRAS lockout feature, tRAP = tRCD(min). This allows any Read Command (with or without Auto Precharge) to be issued to an open bank once tRCD(min) is satisfied. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an Auto Refresh command. The 256Mb DDR SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8s (maximum).
Self Refresh
The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The DLL is automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read command can be issued). Input signals except CKE (low) are "Don't Care" during Self Refresh operation. The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE returning high. Once CKE is high, the SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.
Burst Terminate
The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most re-cently registered Read command prior to the Burst Terminate command is truncated, as shown in the Operation section of this data sheet. Write burst cycles are not to be terminated with the Burst Terminate command.
Auto Refresh
Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a refresh is required.
tRAP Definition
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Operations
Bank/Row Activation
Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be "opened" (activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see Activating a Specific Row in a Specific Bank), which decode and select both the bank and the row to be activated. After opening a row (issuing an Active command), a Read or Write command may be issued to that row, subject to the tRCD specification. A subsequent Active command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive Active commands to the same bank is defined by tRC. A subsequent Active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive Active commands to different banks is defined by tRRD.
Reads
Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a Read command. The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the burst, provided tRAS has been satisfied. For the generic Read commands used in the following illustrations, Auto Precharge is disabled.
During Read bursts, the valid data-out element from the starting column address is available following the CAS latency after the Read command. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (i.e. at the next crossing of CK and CK). The following timing figure entitled "Read Burst: CAS Latencies (Burst Length=4)" illustrates the general timing for each supported CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low state on DQS is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQS and DQS goes High-Z. Data from any Read burst may be concatenated with or truncated with data from a subsequent Read command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new Read command should be issued x cycles after the first Read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in timing figure entitled "Consecutive Read Bursts: CAS Latencies (Burst Length =4 or 8)". A Read command can be initiated on any positive clock cycle following a previous Read command. Nonconsecutive Read data is shown in timing figure entitled "Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)". Full-speed Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) within a page (or pages) can be performed as shown on page 20.
Activating a Specific Row in a Specific Bank
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tRCD and tRRD Definition
Read Command
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Read Burst: CAS Latencies (Burst Length = 4)
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Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)
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Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)
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Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)
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Data from any Read burst may be truncated with a Burst Terminate command, as shown in timing figure entitled Terminating a Read Burst: CAS Latencies (Burst Length = 8) on page 22. The Burst Terminate latency is equal to the read (CAS) latency, i.e. the Burst Terminate command should be issued x cycles after the Read command, where x equals the number of desired data element pairs. Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If truncation is necessary, the Burst Terminate command must be used, as shown in timing figure entitled Read to Write: CAS Latencies (Burst Length = 4 or 8) on page 24. The example is shown for tDQSS(min). The tDQSS(max) case, not shown here, has a longer bus idle time. tDQSS(min) and tDQSS(max) are defined in the section on Writes. A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto Precharge was not activated).
The Precharge command should be issued x cycles after the Read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in timing figure Read to Precharge: CAS Latencies (Burst Length = 4 or 8) on page 25 for Read latencies of 2 and 2.5. Following the Precharge command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data elements. In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as described above) provides the same operation that would result from the same Read burst with Auto Precharge enabled. The disadvantage of the Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to truncate bursts.
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Terminating a Read Burst: CAS Latencies (Burst Length = 8)
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Read to Write: CAS Latencies (Burst Length = 4 or 8)
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Read to Precharge: CAS Latencies (Burst Length = 4 or 8)
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Read with Auto Precharge: CAS Latencies (Burst Length = 4)
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Writes
Write bursts are initiated with a Write command, as shown in timing figure Write Command on page 27. The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic Write commands used in the following illustrations, Auto Precharge is disabled. During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write command, and subsequent data elements are registered on successive edges of DQS. The Low state on DQS between the Write command and the first rising edge is known as the write preamble; the Low state on DQS following the last datain element is known as the write postamble. The time between the Write command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75% to 125% of one clock cycle), so most of the Write diagrams that follow are drawn for the two extreme cases (i.e. tDQSS(min) and tDQSS(max)). Timing figure Write Burst (Burst Length = 4) on page 28 shows the two extremes of tDQSS for a burst of four. Upon completion of a burst, assuming no other commands have been initiated, the DQS and DQS enters High-Z and any additional input data is ignored. Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case, a continuous flow of input data can be maintained. The new Write command can be issued on any positive edge of clock following the previous Write command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new Write command should be issued x cycles after the first Write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). Timing figure Write to Write (Burst Length = 4) on page 29 shows concatenated bursts of 4. An example of nonconsecutive Writes is shown in timing figure Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4) on page 30. Fullspeed random write accesses within a page or pages can be performed as shown in timing figure Random Write Cycles (Burst Length = 2, 4 or 8) on page 31. Data for any Write burst may be followed by a subsequent Read command. To follow a Write without truncating the write burst, tWTR (Write to Read) should be met as shown in timing figure Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4) on page 32. Data for any Write burst may be truncated by a subsequent (interrupting) Read command. This is illustrated in timing figures "Write to Read: Interrupting (CAS Latency =2; Burst Length = 8)", "Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS Latency = 2; Burst Length = 8)", and "Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)". Note that only the data-in pairs that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in must be masked with DM, as shown in the diagrams noted previously. Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without truncating the write burst, tWR should be met as shown in timing figure Write to Precharge: Non-Interrupting (Burst Length = 4) on page 36. Data for any Write burst may be truncated by a subsequent Precharge command, as shown in timing figures Write to Precharge: Interrupting (Burst Length = 4 or 8) on page 37 to Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8) on page 40. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data in should be masked with DM. Following the Precharge command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as described above) provides the same operation that would result from the same burst with Auto Precharge. The disadvantage of the Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to truncate bursts.
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Write Command
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Write Burst (Burst Length = 4)
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Write to Write (Burst Length = 4)
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Write To Write: Max DQSS, Non-Consecutive (Burst Length = 4)
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Random Write Cycles (Burst Length = 2, 4 or 8) .
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Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)
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Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)
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Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS Latency = 2; Burst Length = 8)
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Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)
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Write to Precharge: Non-Interrupting (Burst Length = 4)
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Write to Precharge: Interrupting (Burst Length = 4 or 8)
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Write to Precharge: Minimum DQSS, Odd Number of Data (1 bit Write), Interrupting (Burst Length = 4 or 8)
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Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8)
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Precharge
The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) is available for a subsequent row access some specified time (tRP) after the Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write commands being issued to that bank.
Precharge Command
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Power Down
Power Down is entered when CKE is registered low (no accesses can be in progress). If Power Down occurs when all banks are idle, this mode is referred to as Precharge Power Down; if Power Down occurs when there is a row active in any bank, this mode is referred to as Active Power Down. Entering Power Down deactivates the input and output buffers, excluding CK, CK and CKE. The DLL is still running in Power Down mode, so for maximum power savings, the user has the option of disabling the DLL prior to entering Power Down. In that case, the DLL must be enabled after exiting Power Down, and 200 clock cycles must occur before a Read command can be issued. In Power Down mode, CKE Low and a stable clock signal must be maintained at the inputs of the DDR SDRAM, and all other input signals are "Don't Care". However, Power Down duration is limited by the refresh requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled Power Down mode. The Power Down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command). A valid, executable command may be applied one clock cycle later.
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Power Down
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Truth Table 2: Clock Enble(CKE)
Current CKE n-1 CKE n Command n Action n Note
Previous Cycle Previous Cycle
Self Refresh Self Refresh Power Down Power Down All Banks Idle All Banks Idle Bank(s) Active
L L L L H H H H
L H L H L L L H
X Deselect or NOP X Deselect or NOP Deselect or NOP Auto Refresh Deselect or NOP See "Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)" on page 44
Maintain Self-Refresh Exit Self-Refresh Maintain Power Down Exit Power Down Precharge Power Down Entry Self Refresh Entry Active Power Down Entry 1
Note: 1. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the DDR SDRAM immediately prior to clock edge n. 3. Command n is the command registered at clock edge n, and action n is a result of command n. 4. All states and sequences not shown are illegal or reserved.
5. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
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Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)
Current State
CS RAS CAS WE
Command
Action
NOP. Continue previous operation NOP. Continue previous operation
Note
Any
H L L L L L L L L L L L L L
X H L L L H H L H L H H H L
X H H L L L L H L H H L L H
X H H H L H L L H L L H L L
Deselect No Operation Active Auto Refresh Mode Register Set Read Write Precharge Read Precharge Burst Terminate Read Write Precharge
1-6 1-6 1-6 1-7 1-7 1-6, 10 1-6, 10 1-6, 8 1-6, 10 1-6, 8 1-6, 9 1-6, 10, 11 1-6, 10 1-6, 8, 11
Select and Activate Row
Idle
Row Active Read (Auto Precharge Disabled) Write (Auto Precharge Disabled)
Select column and start Read Burst Select column and start Write Burst
Deactivate row in bank(s)
Select column and start new Read Burst
Burst Terminate
Select column and start Read Burst Select column and start Write Burst
Truncate Write burst, start Precharge
Note: 1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle state. Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the "row active" state. Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4. 5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR SDRAM is in the "all banks idle" state. Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM is in the "all banks idle" state. Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 9. Not bank-specific; Burst terminate affects the most recent Read burst, regardless of bank. 10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled.
11. Requires appropriate DM masking.
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Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
Current State
CS RAS CAS WE
Command
Action
NOP/Continue previous operation NOP/Continue previous operation
Note
Any Idle Row Activating, Active, or Precharging Read (Auto Precharge Disabled) Write (Auto Precharge Disabled)
H L X L L L L L L L L L L L
X H X L H H L L H L L H H L
X H X H L L H H L H H L L H
X H X H H L L H H L H H L L
Deselect No Operation Any Command Otherwise Allowed to Bank m Active Read Write Precharge Active Read Precharge Active Read Write Precharge
1-6 1-6 1-6
Select and Activate Row Select column and start Read Burst Select column and start Write Burst
Select and Activate Row
Select column and start new Read Burst
Select and Activate Row
Select column and start Read Burst Select column and start new Write Burst
1-6 1-7 1-7 1-6 1-6 1-7 1-6 1-6 1-8 1-7 1-6
Note: 1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See note 10. Write with Auto Precharge Enabled: See note 10. 4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle. 5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8. Requires appropriate DM masking. 9. A Write command may be applied after the completion of data output. 10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).
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Truth Table 4: Current State Bank n - Command to Bank m (Different bank) (continued)
Current State
CS RAS CAS WE
Command
Action
Select and Activate Row
Note
Read (With Auto Precharge) Write (With Auto Precharge)
L L L L L L L L
L H H L L H H L
H L L H H L L H
H H L L H H L L
Active Read Write Precharge Active Read Write Precharge
Select column and start new Read Burst Select column and start Write Burst
Select and Activate Row
Select column and start Read Burst Select column and start new Write Burst
1-6 1-7, 10 1-7, 9, 10 1-6 1-6 1-7, 10 1-7, 10 1-6
Note: 1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See note 10. Write with Auto Precharge Enabled: See note 10. 4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle. 5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8. Requires appropriate DM masking. 9. A Write command may be applied after the completion of data output. 10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).
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Simplified State Diagram
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Absolute Maximum Ratings*
Symbol Parameter Rating Unit
VIN, VOUT VIN VDD VDDQ TA TATG PD IOUT
Voltage on I/O pins relative to VSS Voltage on Inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating Temperature (Ambient) Storage Temperature (Plastic) Power Dissipation Short Circuit Output Current
-
0.5 to VDDQ+ 0.5
V V V V
C C
-0.5 to +3.6 -0.5 to +3.6 -0.5 to +3.6 0 to +70 -55 to +150 1.0 5.0
W mA
Notes: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DQS/DQ/DM Slew Rate DDR333 Parameter Symbol Min (6K) Max Min DDR400 (5T) Max Unit Note
DCS/DQ/DM Slew Rate
DCSLEW
TBD
TBD
TBD
TBD
V/ns
1.2
Notes: 1. Measured between V IH (DC), V IL (DC), and V IL (DC), V IH (DC). 2. DQS, DQ, and DM input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transition through the DC region must be monotonic.
Capacitance
Parameter Symbol Min Max Unit Note
Input Capacitance: CK, CK Delta Input Capacitance: CK, CK Input Capacitance: All Other Input-only pins (except DM) Delta Input Capacitance: All Other Input-only pins (except DM) Input/Output Capacitance: DQ, DQS, DM Delta Input/Output Capacitance: DQ, DQS, DM
CI1 Delta CI1 CI2 Delta CI2 CI/O Delta CI/O
2.0
3.0 0.25
pF pF pF pF pF pF
1 1 1 1 1.2 1
2.0
3.0 0.5
4.0
5.0 0.5
Notes: 1. VDDQ = VDD = 2.5V 0.2V (minimum range to maximum range), f = 100MHz, TA = 25C, VODC = VDDQ/2, VOPeak -Peak = 0.2V.
2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is required to match input propagation times of DQ, DQS and DM in the system.
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DC Electrical Characteristics and Operating Conditions (0C TA 70xC; VDDQ = 2.5V 0.2V, VDD = + 2.5V 0.2V, see AC Characteristics)
Symbol Parameter Min Max Unit Note
VDD VDDQ VSS, VSSQ VREF VTT VIH (DC) VIL (DC) VIN (DC) VID (DC) VIX (DC) VIRatio II IOZ IOH IOL
Supply Voltage I/O Supply Voltage Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (System) Input High (Logic 1) Voltage Input Low (logic 0) Voltage Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs Input Crossing Point Voltage, CK and CK Inputs V-I Matching Pulup Current to Puldown Current Ratio Input Leakage Current Any Input 0V VOUT VDD; (All other pins not under test = 0V) Output Leakage Current (DQs are disabled; 0V VOUT VDDQ Output Current: Nominal Strength Driver High current (VOUT= VDDQ -0.373V, min VREF, min VTT) Low current (VOUT= 0.373V, max VREF, max VTT)
2.3 2.3 0 0.49 x VDDQ VREF + 0.04 VREF + 0.15 - 0.3 - 0.3 0.30 0.30 0.71 -5 -5 - 16.8
2.7 2.7 0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 1.4 5 5
V V V V V V V V V V
1 1
1.2 1.3 1 1 1 1.4 1.4 5
A A
1 1
A
1
16.8
Notes: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peakto-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK . 5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
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DC Electrical Characteristics and Operating Conditions
(0C TA 70xC; VDDQ = 2.5V 0.2V, VDD = + 2.5V 0.2V, see AC Characteristics)
Symbol Parameter Min Max Unit Note
IOHW IOLW
Output Current: Half- Strength Driver High current (VOUT= VDDQ -0.763V, min VREF, min VTT) Low current (VOUT= 0.763V, max VREF, max VTT)
- 9.0 mA 9.0 1
Notes: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peakto-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK . 5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
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Normal Strength Driver Pulldown and Pullup Characteristics
1. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve. 2. It is recommended that the "typical" IBIS pulldown V-I curve lie within the shaded region of the V-I curve. 3. The full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve. 4. It is recommended that the "typical" IBIS pullup V-I curve lie within the shaded region of the V-I curve. 5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 6. The full variation in the ratio of the "typical" IBIS pullup to "typical" IBIS pulldown current should be unity 10%, for device drain to source voltages from 0.1 to 1.0. This specification is a design objective only. It is not guaranteed. 7. These characteristics are intended to obey the SSTL_2 class II standard. 8. This specification is intended for DDR SDRAM only.
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Normal Strength Driver Pulldown and Pullup Currents
Pulldown Current (mA) Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Typical Low Tycpial High 6.0 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.9 63.3 63.8 64.1 64.6 64.8 65.0 6.8 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 104.6 105.4 Min 4.6 9.2 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 50.4 50.5 Max 9.6 18.2 26.0 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 88.3 93.8 99.1 103.8 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 139.2 140.8 -6.1 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -43.8 -46.0 -47.8 -49.2 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5 -52.7 -52.8 Pullup Current (mA) Tycpial Low Tycpial High -7.6 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5 -155.3 -160.1 Min -4.6 -9.2 -13.8 -18.4 -23.0 -27.7 -32.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0 -41.1 -41.2 Max -10.0 -20.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6 -192.9 -198.2
Normal Strength Driver Evaluation Conditions
typical Temperature (Tambient) VDDQ Process conditions 25 C 2.5V Typical process
Minimum 70 C 2.3V Slow-slow process
Maximum 0 C 2.7V Fast-fast process
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AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD Specifications and Conditions, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK ), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input low (high) level.
AC Output Load Circuit Diagrams
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AC Input Operating Conditions
(0 C TA 70 C; VDD = VDDQ = 2.5V 0.2V (DDR333); VDD = VDDQ = 2.6V 0.1V (DDR400), See AC Characteristics)
Symbol Parameter/Condition Min Max Unit Note
VIH (AC) VIL (AC) VID (AC) VIX (AC)
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals Input Differential Voltage, CK and CK Inputs Input Crossing Point Voltage, CK and CK Inputs
VREF + 0.31 VREF - 0.31 0.7 0.5*VDDQ - 0.2 VDDQ + 0.6 0.5* VDDQ + 0.2
V V V V
1, 2 1, 2 1, 2, 3 1, 2, 4
Notes: 1. Input slew rate = 1V/ns. 2. Inputs are not recognized as valid until VREF stabilizes. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK . 4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
IDD Specifications and Conditions
(0 C TA 70 C; VDD = VDDQ = 2.5V 0.2V(DDR333); VDD = VDDQ = 2.6V 0.1V (DDR400), See AC Characteristics)
Symbol
DDR333 (6KL) tCK = 6ns
Parameter/Condition
Operating Current: One bank; active / precharge; tRC = tRC (min); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: One bank; active / read / precharge; Burst = 2; tRC = tRC (min); CL = 2.5; IOUT = 0mA; address and control inputs changing once per clock cycle Precharge Power Down Standby Current: All banks idle; Power Down mode; CKE VIL (max)
(min);
DDR333 (6K) tCK = 6ns
DDR400 (5T) tCK = 5.0ns
Unit Note
mA 1
IDD0
68
68
76
IDD1 IDD2P IDD2N IDD3P
72 4 25 10
72 4 25 10
79 4 29 11
mA mA mA mA
1 1 1 1
Idle Standby Current: CS VIH (min); all banks idle; CKE VIH address and control inputs changing once per clock cycle Active Power Down Standby Current: one bank active; Power Down mode; CKE VIL (max) Active Standby Current: One bank; active / precharge; CS
IDD3N
IDD4R
IDD4W IDD5 IDD6 IDD7
VIH (min); CKE VIH (min); tRC = tRAS (max); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: One bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; IOUT = 0mA Operating Current: One bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL = 2.5
Auto-Refresh Current: tRC = tRFC (min) Self-Refresh Current: CKE 0.2V Operating current: Four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = t RC (min); IOUT = 0mA.
39
39
46
mA
1
87
87
105
mA
1
98 118 2 207
98 118 1.5 207
119 124 2 246
mA mA mA mA
1 1 1.2 1
Notes: 1. IDD specifications are tested after the device is properly initialized. 2. Enables on-chip refresh and address counters.
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Electrical Characteristics & AC Timing - Absolute Specifications
(0 C TA 70 C; VDD = VDDQ = 2.5V 0.2V (DDR333); VDD = VDDQ = 2.6V 0.1V (DDR400), See AC Characteristics)
Symbol Parameter DDR333 (6K) DDR400 (5T) Min Max Unit Note
Min
tAC DQ output access time from CK/ CK -0.70 -0.60 0.45 0.45 CL = 2 tCK Clock cycle time CL = 2.5 CL = 3 tDH tDS tIPW tDIPW tHZ tLZ tDQSQ DQ and DM input hold time DQ and DM input setup time Input pulse width DQ and DM input pulse width (each input) Data-out high-impedance time from CK/ CK Data-out low-impedance time from CK/ CK DQS-DQ skew (DQS & associated DQ signals) TSOP Package 7.5 6 0.45 0.45 2.2 1.75 -0.7 -0.7
Max
+0.70 +0.60 0.55 0.55 12 12 -
-0.65 -0.55 0.45 0.45 6 5 0.40 0.40 2.2 1.75
+0.65 +0.55 0.55 0.55 12 8
ns ns tCK tCK
1-4 1-4 1-4 1-4
tDQSCK DQS output access time from CK/ CK tCH tCL CK high-level width CK low-level width
ns
1-4
ns ns ns ns +0.65 +0.65 +0.40 ns ns ns
1-4, 15, 16 1-4, 15, 16
2-4,12
1-4 1-4,5 1-4,5 1-4
+0.7 +0.7 +0.45
-0.65 -0.65
tHP tQH tQHS tDQSS tDQSH tDQSL tDSS tDSH tMRD
Minimum half clk period for any given cycle; Defined by clk high (tCH) or low (tCL) time. Data output hold time from DQS Data hold Skew Factor TSOP Package
min tCL, tCH tHP, tQHS 0.55 0.75 0.35 0.35 0.2 0.2 12 0 0.40 0.25 0.75 0.75 0.60 1.25
min tCL, tCH tHP, tQHS 0.5 0.72 0.35 0.35 0.2 0.2 12 0 0.40 0.25 0.6 0.6 0.60 1.25
tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ns ns
1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4,7 1-4,6 1-4
2-4,9,11,12 2-4,9,11,12
Write command to 1st DQS latching transition
DQS input high pulse width (write cycle) DQS input low pulse width (write cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time
tWPRES Write preamble setup time tWPST tWPRE tIH tIS Write postamble Write postamble
Address and control input hold time (fast slew rate) Address and control input hold time (fast slew rate)
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Electrical Characteristics & AC Timing - Absolute Specifications (continued)
(0 C TA 70 C; VDD = VDDQ = 2.5V 0.2V (DDR333); VDD = VDDQ = 2.6V 0.1V (DDR400), See AC Characteristics)
Symbol DDR333 6K DDR400 5T Min Max
Parameter
Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Read preamble Read postamble Active to Precharge Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read or write dalay Active to read command with Autoprecharge Precharge command period Active bank A to Active bank B command Write vecovery time Auto precharge write recovery + precharge time Intemal write to read command delay Power down exit time Exit self-refresh to non-read command
Exit self-refresh to read command
Unit
Note
2-4,10,11, 12,14 2-4,10,11, 12,14
Min
tIH tIH tRPRE tRPST tRAS tRC tRFC tRCD tRAP tRP tRRD tWR tDAL tWTR tPDEX tXSNR tXSRD tREFI 0.8 0.8 0.9 0.40 40 60 72 18 min (tRCD, tRAS) 18 12 15 1 6 75 200
Max
0.65 0.65 1.1 0.60 70K 0.9 2.0 42 55 70 15 min (tRCD, tRAS) 15 10 15 2 6 75 200 7.8 7.8 1.1 0.6 70K
ns ns tCK tCK ns ns tCK tCK tCK tCK tCK tCK tCK tCK ns tCK tCK s
1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4,13 1-4 1-4 1-4
1-4
Average Periodic Refresh Interval
1-4,8
Notes: 1. Input slew rate = 1V/ns.
2. The CK/ CK input reference level (for timing reference to CK/ CK ) is the point at which CK and CK cross; the input reference level for signals other than CK/ CK is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on tDQSS. 8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 9. For command/address input slew rate 1.0V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 10. For command/address input slew rate 0.5V/ns and < 1.0V/ns. Slew rate is measured between VOH (AC) and VOL (AC).
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Electrical Characteristics & AC Timing - Absolute Specifications (continued)
11. CK/ CK slew rates are 1.0V/ns. 12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. For example, for DDR266B at CL = 2.5, tDAL = (15ns/7.5ns) + (20ns/7.5ns) = 2 + 3 = 5. 14. An input setup and hold time derating table is used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns.
Input Slew Rate Delta (tIS) Delta (tIH) Unit Note
0.5 V/ns 0.4 V/ns 0.3 V/ns
0 +50 +100
0 0 0
ps ps ps
1, 2 1, 2 1, 2
1. Input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
15. An input setup and hold time derating table is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5
V/ns.
Input Slew Rate Delta (tDS) Delta (tDH) Unit Note
0.5 V/ns 0.4 V/ns 0.3 V/ns
0 +75 +150
0 +75 +150
ps ps ps
1, 2 1, 2 1, 2
1. I/O slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
16. An I/O Delta Rise, Fall Derating table is used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ.
Input Slew Rate Delta (tDS) Delta (tDH) Unit Note
0.0 V/ns 0.25 V/ns 0.5 V/ns
0 +50 +100
0 +50 +100
ps ps ps
1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4
1. Input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. 2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. 3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in t DS and t DH of 100 ps. 4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
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Data Input (Write) (Timing Burst Length = 4)
Data Output (Read) (Timing Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
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Initialize and Mode Register Sets
Preliminary (September, 2005, Version 0.0)
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Power Down Mode
Preliminary (September, 2005, Version 0.0)
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Auto Refresh Mode
Preliminary (September, 2005, Version 0.0)
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Self Refresh Mode
Preliminary (September, 2005, Version 0.0)
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Read without Auto Precharge (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
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Read with Auto Precharge (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
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Bank Read Access (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
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Write without Auto Precharge (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
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Write with Auto Precharge (Burst Length = 4)
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Bank Write Access (Burst Length = 4)
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Write DM Operation (Burst Length = 4)
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Package Dimensions (400mil; 66 lead TSOP Package)
Preliminary (September, 2005, Version 0.0)
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