View AKD4683-A_1208670.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ASAHI KASEI
[AKD4683-A]
AKD4683-A
AK4683 Evaluation Board Rev.1
FEATURE AKD4683-A is an evaluation board for AK4683, a single chip 24bit CODEC that has two channels of ADC and four channels of DAC with internal DIR, DIT. This board has interfaces with AKM's evaluation boards for A/D converter and D/A converter and makes easy to evaluate AK4683. Also this board has the digital audio interface and then achieves the interface with digital audio systems via opt-connector or RCA connector. Ordering guide
AKD4683-A --- AK4683 Evaluation Board 10 wire flat cable for connection with printer port of PC (IBM-AT compatible machine), control software for AK4589, driver for control software on Windows 2000/XP are packed with this. Control software does not work on Windows NT Windows 2000/XP needs an installation of driver. Windows 95/98/ME does not need an installation of driver. AK4683 supports the standard-mode I2C-bus (max: 100kHz), and does not support a fast-mode I2C-bus system (max: 400kHz).
FUNCTION On-board clock generator (use AK4114, x2) Compatible with 2 types of digital audio interface - Optical output/input and RCA input/output - 10pin header for interface with external data source (x2) RCA connector for clock input with external clock source 10pin header for register control
AVDD1 AVDD2 HVDD DVDD PVDD TVDD GND 5V Regulator Regulator 3.3V Opt Out TX1 TX1
+12V -12V
Opt IN RX0/1/2/3 RX0 Control Data 10pin Header PORT A
OpAmp LOUT1/ROUT1
OpAmp LOUT2/ROUT2 HP-Jack HPL/HPR LIN1/RIN1
AK4683
10pin Header PORT B 10pin Header AK4114 AK4114 RCA IN/OUT
LIN2/RIN2 LIN3/RIN3 LIN5/RIN5 LIN4/RIN4 LIN6/RIN6 MCKI
RCA IN/OUT
AK4114 has DIR, DIT and X'tal oscillator. Figure 1. AKD4683-A Block Diagram (* Circuit diagram and PCB layout are attached at the end of this manual.) -12005/08
ASAHI KASEI
[AKD4683-A]
EVALUATION BOARD MANUAL Operation sequence
1. Power supply lines and jumpers for power supply / ground 1-1. Power supply circuit 1-2. Power supply lines 1-3. Jumpers for power supply / ground 2. Register control 2-1. 10-wire flat cable for register control 2-2. 4-wire serial control 2-3. I2C-bus control 3. 10-wire flat cable for interface with external data source 3-1. PORT4 (for PORTA) 3-2. PORT5 (for PORTB) 4. Jumpers of Master Clock: MCKI / MCLK2 4-1. External Master Clock 4-2. PORTA: AK4114 (U7) 4-3. PORTB: AK4114 (U10) 5. Jumpers of Master Clock: MCKO / X'tal 5-1. PORTA: AK4114 (U7) 5-2. PORTB: AK4114 (U10) 6. DIP Switches 6-1. SW2 (PORTA_DIR/4683) 6-2. SW4 (PORTB_DIR) 7. Evaluation mode 7-1. DAC with internal DIR 7-2. ADC with internal DIT 7-3. DAC with external DIR 7-3-1. DAC with PORTA: AK4114 (U7) as external DIR 7-3-2. DAC with PORTB: AK4114 (U10) as external DIR 7-4. ADC with external DIT 7-4-1. ADC with PORTA: AK4114 (U7) as external DIT 7-4-2. ADC with PORTB: AK4114 (U10) as external DIT 7-5. Internal loop back (Analog input ADC DAC Analog output) 7-6. Headphone output 8. Power on 8-1. Toggle switch 8-2. LED 8-3. Reset after power on
-2-
2005/08
ASAHI KASEI
[AKD4683-A]
1. Power supply lines and jumpers for power supply / ground
1-1. Power supply circuit
-12V R86 N12V C72 47u HVSS AVDD1 L2 + C67 47u AVSS1 AVDD1 AVDD2 L3 + C74 47u HVSS AVDD2 DVDD L5 + C76 47u DVSS R88 DVDD (short) PVDD L7 + C78 47u PVSS PVDD
IN
C73 0.1u
(short)
(short)
JP25
AVDD1 REG
3
T4 NJM78M05FA
GND OUT IN 1
+12V R87 P12V C70 + 0.1u HVSS HVSS C71 47u (short)
AVDD1_SEL
+ C68 47u
C69 0.1u
AVSS1
AVSS1
AVSS1
(short)
JP26 AVDD2 AVDD1 AVDD2_SEL
HVDD L4 + C75 47u HVSS HVDD (short) JP27 HVDD AVDD1 HVDD_SEL
(short)
JP28 DVDD AVDD1 DVDD_SEL VDD L6 + C77 47u PVDD JP30 AVDD1 PVDD_SEL T5 TA48M033F
GND OUT 1
(short)
2
JP29 VDD DVDD
PVSS VDD
DVDD VDD_SEL
(short)
L8 (short) + C82 47u DVSS L9 4683_TVDD (short) L11 4114_TVDD (short)
TVDD(4683) JP32 REG2 TVDD_SEL L10 D3.3V (short) DVSS
Figure 2. Power supply circuit
-3-
2
TVDD(4683)
JP31 DVDD
C79 0.1u
C80 0.1u
C81 + 47u
+
HVSS
2005/08
ASAHI KASEI
[AKD4683-A]
1-2. Power supply lines Name of jack Color of jack Voltage Used for Comment and attention Default Setting Open
Should be always connected when JP25 (AVDD1_SEL) is set to AVDD1 side. AVDD1 Orange +4.5+5.5V AVDD1 of AK4683 Can be open when JP25 (AVDD1_SEL) is set to REG side. Should be always connected when JP26 (AVDD2_SEL) is set to AVDD2 side. AVDD2 Orange +4.5+5.5V AVDD2 of AK4683 Can be open when JP26 (AVDD2_SEL) is set to AVDD1 side. Should be always connected when JP28 (DVDD_SEL) is set to DVDD side. DVDD Orange +4.5+5.5V DVDD of AK4683 Can be open when JP28 (DVDD_SEL) is set to AVDD1 side. Should be always connected when JP30 (PVDD_SEL) is set to PVDD side. PVDD Orange +4.5+5.5V PVDD of AK4683 Can be open when JP30 (PVDD_SEL) is set to AVDD1 side. Should be always connected when JP27 (HVDD_SEL) is set to HVDD side. HVDD Orange +4.5+5.5V HVDD of AK4683 Can be open when JP27 (HVDD_SEL) is set to AVDD1 side. Should be always connected when JP29 (VDD_SEL) is set to VDD side. VDD Orange +4.5+5.5V Logic Parts Can be open when JP29 (VDD_SEL) is set to DVDD side. Should be always connected when JP31 (DVDD) is open, and JP32 (TVDD_SEL) is set to TVDD side. TVDD TVDD of AK4683, Orange +2.7+5.5V Can be open when JP31 (DVDD) is open, (4683) TVDD of AK4114 and JP32 (TVDD_SEL) is set to REG2 side, or when JP31 (DVDD) is short, and JP32 (TVDD_SEL) is set to TVDD side. Power supply for Regulator, Output Buffer Regulator, +12V Red (Op-amp). +12+15V Output Buffer (Op-amp) Should be always connected. Power supply for Output Buffer (Op-amp). -12V Blue Output Buffer (Op-amp) -12-15V Should be always connected. AVSS1 Black 0V Analog Ground Analog Ground. Should be always connected. HVSS Black 0V Analog Ground Analog Ground. Should be always connected. DVSS Black 0V Analog Ground Analog Ground. Should be always connected. PVSS Black 0V Analog Ground Analog Ground. Should be always connected. Digital Ground. DGND Black 0V Digital Ground Should be connected when JP1 is open. Can be open when JP1 is short. Table 1. Power supply lines (Note) Each supply line should be distributed from the power supply unit.
Open
Open
Open
+5V
+5V
Open
+12V -12V 0V 0V 0V 0V 0V
-4-
2005/08
ASAHI KASEI
[AKD4683-A]
1-3. Jumpers for power supply / ground 1-3-1. AVDD1 JP25 (AVDD1_SEL) controls AVDD1 source (regulator T4 or jack "AVDD1").
JP25 AVDD1_SEL
JP25 AVDD1_SEL
AVDD1
REG
AVDD1
REG
REG
AVDD1
Figure 3. JP25 (AVDD1_SEL) 1-3-2. AVDD2 JP26 (AVDD2_SEL) controls AVDD2 source (AVDD1 line or jack "AVDD2").
JP26 AVDD2_SEL
JP26 AVDD2_SEL
AVDD1
AVDD2
AVDD1
AVDD2
(AVDD1) Figure 4. JP26 (AVDD2_SEL)
(AVDD2)
1-3-3. DVDD JP28 (DVDD_SEL) controls DVDD source (AVDD1 line or jack "DVDD").
JP28 DVDD_SEL
JP28 DVDD_SEL
AVDD1
DVDD
AVDD1
DVDD
(AVDD1) (DVDD) Figure 5. JP28 (DVDD_SEL)
-5-
2005/08
ASAHI KASEI
[AKD4683-A]
1-3-4. PVDD JP30 (PVDD_SEL) controls PVDD source (AVDD1 line or jack "PVDD").
JP30 PVDD_SEL
JP30 PVDD_SEL
PVDD
AVDD1
PVDD
AVDD1
(AVDD1) Figure 6. JP30 (PVDD_SEL)
1-3-5. HVDD
(PVDD)
JP27 (HVDD_SEL) controls HVDD source (AVDD1 line or jack "HVDD").
JP27 HVDD_SEL
JP27 HVDD_SEL
AVDD1
HVDD
AVDD1
HVDD
(AVDD1)
Figure 7. JP27 (HVDD_SEL) 1-3-6. VDD
(HVDD)
JP29 (VDD_SEL) controls VDD source (DVDD line or jack "VDD").
JP29 VDD_SEL
JP29 VDD_SEL
VDD
DVDD
VDD
DVDD
(DVDD)
Figure 8. JP29 (VDD_SEL)
(VDD)
-6-
2005/08
ASAHI KASEI
[AKD4683-A]
1-3-7. TVDD and DVDD JP31 (DVDD) controls separate (open) or connect (short) of TVDD and DVDD.
JP31 DVDD
JP31 DVDD
(open)
Figure 9. JP31 (DVDD)
(short)
1-3-8. TVDD for AK4683 and AK4114 JP32 (TVDD_SEL) controls TVDD source (regulator T5 or jack "TVDD (4683)") for AK4683 and AK4114.
JP32 TVDD_SEL
JP32 TVDD_SEL
REG2
TVDD
REG2
TVDD
(REG2) (TVDD) Figure 10. JP32 (TVDD_SEL)
1-3-9. Analog Ground and Digital Ground JP1 (DGND) controls separate (open) or connect (short) of Analog Ground and Digital Ground. In this case, jack "DGND" can be open.
JP1 DGND JP1 DGND
(open) (short) Figure 11. JP1 (DGND)
-7-
2005/08
ASAHI KASEI
[AKD4683-A]
2. Register control
2-1. 10-wire flat cable for register control AK4683 can be controlled via printer port (parallel port) of IBM-AT compatible PC. Connect printer port (parallel port) of PC and PORT2 (uP-I/F) of AKD4683-A by 10-wire flat cable (packed with AKD4683-A). Take care of the direction of 10-pin connector and 10-pin header. (The red line side of 10-wire flat cable of 10-pin connector should be connected to No.5pin and No.6pin of 10-pin header.)
PORT2 1 UP-I/F 10 CSN Connect PC SCL / CCLK SDA / CDTI SDA (ACK) / CDTO RED 10-wire flat cable 10-pin connector
5 6 10-pin header
AKD4683-A
Figure 12. 10-wire flat cable, 10-pin connector and 10-pin header 2-2. 4-wire serial control (1) Set JP3 (SDA/CDTO) to "CDTO/CM0=H".
JP3 SDA/CDTO
SDA CDTO/CM0=H CM0=L
(CDTO/CM0=H) Figure 13. JP3 (SDA/CDTO)
(2) Set SW2 (PORT A_DIR/4683): No.8 pin (I2C) to "OFF".
-8-
2005/08
ASAHI KASEI
2
[AKD4683-A]
2-3. I C-bus control (1) Set JP3 (SDA/CDTO) to "SDA".
JP3 SDA/CDTO
SDA CDTO/CM0=H CM0=L
(SDA) Figure 14. JP3 (SDA/CDTO)
(2) Set SW2 (PORT A_DIR/4683): No.8 pin (I2C) to "ON".
-9-
2005/08
ASAHI KASEI
[AKD4683-A]
3. 10-wire flat cable for interface to external
AK4683 can achieve the interface with external data source via PORT4 (PORTA), PORT5 (PORTB). Connect PORT4 (PORTA) and external port or PORT5 (PORTB) and external port by 10-wire flat cable. Take care of the direction of 10-pin connector and 10-pin header. (The red line side of 10-wire flat cable of 10-pin connector should be connected to No.5pin and No.6pin of 10-pin header.) 3-1. PORT4 (for PORTA) Pin layout of PORT4 (for PORTA) is shown in Figure 15.
1 PORT4 10 MCLK BICKA OLRCKA SDTOA GND MCKO SDTIA1 SDTIA2
SDTIA3 ILRCKA 5 PORTA 6
Figure 15. PORT4 (for PORTA) 3-2. PORT5 (for PORTB) Pin layout of PORT5 (for PORTB) is shown in Figure 16.
1 MCLK BICKB LRCKB SDTOB 5 PORTB 6 PORT5 10 GND MCKO SDTIB
Figure 16. PORT5 (for PORTB)
- 10 -
2005/08
ASAHI KASEI
[AKD4683-A]
4. Jumpers of Master Clock: MCKI / MCLK2
4-1. External Master Clock JP19 (MCLK_SEL) controls External Master Clock source (MCKI / MCLK2) for AK4683. In these two cases above, JP16 (MCLKA_SEL) and JP22 (MCLKB_SEL) should be open.
JP19 MCLK_SEL MCLK_SEL
MCLK2
MCKI
MCLK2
MCKI
(MCKI) JP16 MCLKA_SEL
(MCLK2)
MCKO1
(open)
MCKO2
JP22 MCLKB_SEL
MCKO1
MCKO2
(open)
Figure 17. JP19 (MCLK_SEL)
- 11 -
2005/08
ASAHI KASEI
[AKD4683-A]
4-2. PORTA: AK4114 (U7) JP16 (MCLKA_SEL) controls PORTA: AK4114 (U7): Master Clock source (MCKO1 / MCKO2) for AK4683: MCLK2. In these two cases above, JP19 (MCLK_SEL) and JP22 (MCLKB_SEL) should be open.
JP16 MCLKA_SEL MCLKA_SEL
MCKO1
MCKO2
MCKO1
MCKO2
(MCKO1) JP19 MCLK_SEL
(MCKO2)
MCLK2
MCKI
(open) JP22 MCLKB_SEL
MCKO1
MCKO2
(open)
Figure 18. JP16 (MCLKA_SEL)
- 12 -
2005/08
ASAHI KASEI
[AKD4683-A]
4-3. PORTB: AK4114 (U10) JP22 (MCLKB_SEL) controls PORTB: AK4114 (U10): Master Clock source (MCKO1 / MCKO2) for AK4683: MCLK2. In these two cases above, JP19 (MCLK_SEL) and JP16 (MCLKA_SEL) should be open.
JP22 MCLKB_SEL MCLKB_SEL
MCKO1
MCKO2
MCKO1
MCKO2
(MCKO1)
(MCKO2) JP19 MCLK_SEL
MCLK2
MCKI
(open) JP16 MCLKA_SEL
MCKO1
(open)
MCKO2
Figure 19. JP22 (MCLKB_SEL)
- 13 -
2005/08
ASAHI KASEI
[AKD4683-A]
5. Jumpers of Master Clock: MCKO / X'tal
5-1.PORTA: AK4114 (U7) JP10 (XTIA) controls Master Clock source (AK4683: MCKO (short) / X2: X'tal (open)) for PORTA: AK4114 (U7):XTI.
JP10 XTIA
JP10 XTIA
(open)
Figure 20. JP10 (XTIA) 5-2. PORTB: AK4114 (U10)
(short)
JP20 (XTIB) controls Master Clock source (AK4683: MCKO (short) / X3: X'tal (open)) for for PORTB: AK4114 (U10):XTI.
JP20 XTIB
JP20 XTIB
(open)
Figure 21. JP20 (XTIB)
(short)
- 14 -
2005/08
ASAHI KASEI
[AKD4683-A]
6. DIP Switches
6-1. SW2 (PORT A_DIR/4683) Setting for AK4683 and PORT A: AK4114 (U7) No. Name ON ("H") OFF ("L") 1 DIF0 Setting of Audio Format of AK4114 2 DIF1 (Refer Table 2.) 3 DIF2 4 CM0 Selection of Clock Mode (Clock Source) 5 CM1 Table 3. 6 OCKS0 Selection of frequency of Master Clock Output 7 OCKS1 Table4. 8 I2C I2C-bus control mode 4-wire serial control mode Table 2. SW2 (PORT A_DIR / 4683) (Note) ON: "H" ("1"), OFF: "L" ("0") 6-2. SW4 (PORT B_DIR) Setting for PORT B: AK4114 (U10) No. Name ON ("H") OFF ("L") 1 DIF0 Setting of Audio Format of AK4114 2 DIF1 (Refer Table 2. 3 DIF2 4 CM0 Selection of Clock Mode (Clock Source) 5 CM1 Refer Table 3. 6 OCKS0 Selection of frequency of Master Clock Output 7 OCKS1 Refer Table4. 8 NC Table 3. SW4 (PORT B_DIR) (Note) ON: "H" ("1"), OFF: "L" ("0")
Default OFF ("L", "0") ON ("H", "1") ON ("H", "1") OFF ("L", "0") OFF ("L", "0") OFF ("L", "0") OFF ("L", "0") OFF ("L", "0")
Default OFF ("L", "0") ON ("H", "1") ON ("H", "1") OFF ("L", "0") OFF ("L", "0") OFF ("L", "0") OFF ("L", "0") OFF ("L", "0")
- 15 -
2005/08
ASAHI KASEI
[AKD4683-A]
Mode 0 1 2 3 4 5 6 7
DIF2 0 0 0 0 1 1 1 1
DIF1 0 0 1 1 0 0 1 1
DIF0 0 1 0 1 0 1 0 1
LRCK I/O 24bit, Left justified 16bit, Right justified H/L O 24bit, Left justified 18bit, Right justified H/L O 24bit, Left justified 20bit, Right justified H/L O 24bit, Left justified 24bit, Right justified H/L O 24bit, Left justified 24bit, Left justified H/L O 24bit, I2S 24bit, I2S L/H O 24bit, Left justified 24bit, Left justified H/L I 24bit, I2S 24bit, I2S L/H I Table 4. Audio Interface Format of AK4114 DAUX SDTO
BICK 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs I/O O O O O O O I I

Mode 0 1 2
UNLOCK PLL X'tal Clock source SDTO ON ON (Note1) PLL RX OFF ON X'tal DAUX 0 ON ON PLL RX 1 0 1 ON ON X'tal DAUX 3 1 1 ON ON X'tal DAUX Table 5. Clock Mode (Clock Source) (Note1) When X'tal is not used on reference clock (XTL0, 1= "1, 1"), this setting is "OFF" (Note2) Normally, use "Default" setting. No. 0 1 2 3 OCKS1 0 0 1 1 OCKS0 MCKO1 MCKO2 X'tal fs (max) 0 256fs 256fs 256fs 96 kHz 1 256fs 128fs 256fs 96 kHz 0 512fs 256fs 512fs 48 kHz 1 128fs 64fs 128fs 192 kHz Table 6. Frequency of Master Clock Output
CM1 0 0
CM0 0 1

- 16 -
2005/08
ASAHI KASEI
[AKD4683-A]
7. Evaluation mode
7-1. DAC with internal DIR 7-1-1. Connection of connector In case of input through RX0, optical connector PORT3 (TORX176) or RCA connector J14 (RX0) are available. In case of input through RX1, RX2 or RX3, only the optical connector PORT3 is available. 7-1-2. Setting of jumper pin In case of input through RX0, JP4 (RX0) controls digital input (optical connector PORT3 or RCA connector J14).
JP4 RX0
JP4 RX0
OPT
RCA
OPT
RCA
(OPT)
Figure 22. JP4 (RX0)
(RCA)
In case of input through RX1, RX2 or RX3, jumpers JP5 (RX1), JP6 (RX2) or JP7 (RX3) control digital input channels (RX1, RX2 or RX3) from PORT3. About only input channels, set some of jumpers JP5 (RX1), JP6 (RX2) or JP7 (RX3) to OPT. About no-input channels, set other of jumpers JP5 (RX1), JP6 (RX2) or JP7 (RX3) to GND.
JP5 RX1
JP5 RX1
OPT
GND
OPT
GND
(OPT) JP6 RX2
(GND) JP6 RX2
OPT
GND
OPT
GND
(OPT) JP7 RX3
(GND) JP7 RX3
OPT
GND
OPT
GND
(OPT)
(GND)
Figure 23. JP5 (RX1), JP6 (RX2), JP7 (RX3)
- 17 -
2005/08
ASAHI KASEI
[AKD4683-A]
Setting of interface signal of PORTA: AK4114 (U7) is as follows.
JP17 BICKA
JP18 OLRCKA
JP11 ILRCKA
JP12 SDTIA
JP14 JP13 SDTIA1_SEL SDTIA2_SEL
JP15 SDTIA3_SEL
(GND) (GND) (GND) Figure 24. JP17 (BICKA), JP18 (OLRCKA), JP11 (ILRCKA), JP12 (SDTIA), JP13 (SDTIA1_SEL), JP14 (SDTIA2_SEL), JP15 (SDTIA3_SEL)
Setting of interface signal of PORTB: AK4114 (U10) is as follows.
(open)
(open)
(open)
(open)
DIR
GND
DIR
GND
DIR
GND
JP23 BICKB
JP24 LRCKB
JP21 SDTIB_SEL
(open)
(open)
DIR
GND
(GND)
Figure 25. JP23 (BICKB), JP24 (LRCKB), JP21 (SDTIB_SEL) 7-1-3. Setting of DIP switch SW2 (PORTA_DIR/4683) and SW4 (PORTB_DIR) are "Don't care". 7-1-4. Setting of toggle switch Set SW3 (DIR PORTA) to OFF. Set SW5 (DIR PORTB) to OFF. Set SW1 (PDN) to OFF ON.
- 18 -
2005/08
ASAHI KASEI
[AKD4683-A]
7-2. ADC with internal DIT 7-2-1. Connection of connector For output, optical connector PORT1 (TOTX176) or RCA connector J13 (TX1) are available. 7-2-2. Setting of jumper pin JP2 (TX1) controls digital output (optical connector PORT1 or RCA connector J13).
JP2 TX1 JP2 TX1
OPT
RCA
OPT
RCA
(OPT)
(RCA)
Figure 26. JP2 (TX1) Setting of interface signal of PORTA: AK4114 (U7) is as follows.
JP17 BICKA
JP18 OLRCKA
JP11 ILRCKA
JP12 SDTIA
JP14 JP13 SDTIA1_SEL SDTIA2_SEL
JP15 SDTIA3_SEL
(open)
(open)
(open)
(open)
DIR
GND
DIR
GND
DIR
GND
(GND)
(GND)
(GND)
Figure 27. JP17 (BICKA), JP18 (OLRCKA), JP11 (ILRCKA), JP12 (SDTIA), JP13 (SDTIA1_SEL), JP14 (SDTIA2_SEL), JP15 (SDTIA3_SEL) Setting of interface signal of PORTB: AK4114 (U10) is as follows.
JP23 BICKB
JP24 LRCKB
JP21 SDTIB_SEL
(open)
(open)
DIR
GND
(GND)
Figure 28. JP23 (BICKB), JP24 (LRCKB), JP21 (SDTIB_SEL) 7-2-3. Setting of DIP switch SW2 (PORTA_DIR/4683) and SW4 (PORTB_DIR) are "Don't care". 7-2-4. Setting of toggle switch Set SW3 (DIR PORTA) to OFF. Set SW5 (DIR PORTB) to OFF. Set SW1 (PDN) to OFF ON.
- 19 -
2005/08
ASAHI KASEI
[AKD4683-A]
7-3. DAC with external DIR 7-3-1. DAC with PORT A: AK4114 (U7) as external DIR 7-3-1-1. Connection of connector For digital input, RCA connector J22 (PORTA_RX0) is available. 7-3-1-2. Setting of jumper pin Setting of interface signal of PORTA: AK4114 (U7) is as follows.
JP17 BICKA
JP18 OLRCKA
JP11 ILRCKA
JP12 SDTIA
JP14 JP13 SDTIA1_SEL SDTIA2_SEL
JP15 SDTIA3_SEL
(short)
(open)
(short)
(short)
DIR
GND
DIR
GND
DIR
GND
(DIR)
(DIR)
(DIR)
Figure 29. JP17 (BICKA), JP18 (OLRCKA), JP11 (ILRCKA), JP12 (SDTIA), JP13 (SDTIA1_SEL), JP14 (SDTIA2_SEL), JP15 (SDTIA3_SEL) Setting of interface signal of PORTB: AK4114 (U10) is as follows.
JP23 BICKB
JP24 LRCKB
JP21 SDTIB_SEL
(open)
(open)
DIR
GND
(GND)
Figure 30. JP23 (BICKB), JP24 (LRCKB), JP21 (SDTIB_SEL) When master clock of PORTA: AK4114 (U7): MCKO1 is supplied to AK4683: MCLK2, setting of master clock is as follows.
JP16 MCLKA_SEL
JP22 MCLKB_SEL
JP19 MCLK_SEL
MCKO1
MCKO2
MCKO1 MCKO2
MCLK2
MCKI
(MCKO1)
(open)
(open)
Figure 31. JP16 (MCLKA_SEL), JP22 (MCLKB_SEL), JP19 (MCLK_SEL) 7-3-1-3. Setting of DIP switch Set SW2 (PORTA_DIR/4683): 5pin (CM1) to OFF. Set SW2 (PORTA_DIR/4683): 4pin (CM0) to OFF. 7-3-1-4. Setting of toggle switch Set SW3 (DIR PORTA) to ON. Set SW5 (DIR PORTB) to OFF. Set SW1 (PDN) to OFF ON.
- 20 -
2005/08
ASAHI KASEI
[AKD4683-A]
7-3-2. DAC with PORT B: AK4114 (U10) as external DIR 7-3-2-1. Connection of connector For digital input, RCA connector J25 (PORTB_RX0) is available. 7-3-2-2. Setting of jumper pin Setting of interface signal of PORTA: AK4114 (U7) is as follows.
JP17 BICKA
JP18 OLRCKA
JP11 ILRCKA
JP12 SDTIA
JP14 JP13 SDTIA1_SEL SDTIA2_SEL
JP15 SDTIA3_SEL
(open)
(open)
(open)
(open)
DIR
GND
DIR
GND
DIR
GND
(GND)
(GND)
(GND)
Figure 32. JP17 (BICKA), JP18 (OLRCKA), JP11 (ILRCKA), JP12 (SDTIA), JP13 (SDTIA1_SEL), JP14 (SDTIA2_SEL), JP15 (SDTIA3_SEL) Setting of interface signal of PORTB: AK4114 (U10) is as follows.
JP23 BICKB
JP24 LRCKB
JP21 SDTIB_SEL
(short)
(short)
DIR
GND
(DIR)
Figure 33. JP23 (BICKB), JP24 (LRCKB), JP21 (SDTIB_SEL) When master clock of PORTB: AK4114 (U10): MCKO1 is supplied to AK4683: MCLK2, setting of master clock is as follows.
JP22 MCLKB_SEL
JP16 MCLKA_SEL
JP19 MCLK_SEL
MCKO1
(open) (open) (MCKO1) Figure 34. JP22 (MCLKB_SEL), JP16 (MCLKA_SEL), JP19 (MCLK_SEL)
MCKO2
MCKO1
MCKO2
MCLK2
MCKI
7-3-2-3. Setting of DIP switch Set SW4 (PORTB_DIR): 5pin (CM1) to OFF. Set SW4 (PORTB_DIR): 4pin (CM0) to OFF. 7-3-2-4. Setting of toggle switch Set SW3 (DIR PORTA) to OFF. Set SW5 (DIR PORTB) to ON. Set SW1 (PDN) to OFF ON.
- 21 -
2005/08
ASAHI KASEI
[AKD4683-A]
7-4. ADC with external DIT 7-4-1. ADC with PORT A: AK4114 (U7) as external DIT 7-4-1-1. Connection of connector For digital output, RCA connector J23 (PORTA_TX1) is available. 7-4-1-2. Setting of jumper pin Setting of interface signal of PORTA: AK4114 (U7) is as follows.
JP17 BICKA
JP18 OLRCKA
JP11 ILRCKA
JP12 SDTIA
JP14 JP13 SDTIA1_SEL SDTIA2_SEL
JP15 SDTIA3_SEL
(short)
(short)
(open)
(open)
DIR
GND
DIR
GND
DIR
GND
(GND)
(GND)
(GND)
Figure 35. JP17 (BICKA), JP18 (OLRCKA), JP11 (ILRCKA), JP12 (SDTIA), JP13 (SDTIA1_SEL), JP14 (SDTIA2_SEL), JP15 (SDTIA3_SEL) Setting of interface signal of PORTB: AK4114 (U10) is as follows.
JP23 BICKB
JP24 LRCKB
JP21 SDTIB_SEL
(open)
(open)
DIR
GND
(GND)
Figure 36. JP23 (BICKB), JP24 (LRCKB), JP21 (SDTIB_SEL) When master clock of AK4683: MCKO is supplied to PORTA: AK4114 (U7): XTI, setting of master clock is as follows.
JP10 XTIA
(short) Figure 37. JP10 (XTIA)
7-4-1-3. Setting of DIP switch Set SW2 (PORTA_DIR/4683): 5pin (CM1) to OFF. Set SW2 (PORTA_DIR/4683): 4pin (CM0) to ON. 7-4-1-4. Setting of toggle switch Set SW3 (DIR PORTA) to ON. Set SW5 (DIR PORTB) to OFF. Set SW1 (PDN) to OFF ON.
- 22 -
2005/08
ASAHI KASEI
[AKD4683-A]
7-4 -2. ADC with PORT B: AK4114 (U10) as external DIT 7-4-2-1. Connection of connector For digital output, RCA connector J26 (PORTB_TX1) is available. 7-4-2-2. Setting of jumper pin Setting of interface signal of PORTA: AK4114 (U7) is as follows.
JP17 BICKA
JP18 OLRCKA
JP11 ILRCKA
JP12 SDTIA
JP14 JP13 SDTIA1_SEL SDTIA2_SEL
JP15 SDTIA3_SEL
(open)
(open)
(open)
(open)
DIR
GND
DIR
GND
DIR
GND
(GND)
(GND)
(GND)
Figure 38. JP17 (BICKA), JP18 (OLRCKA), JP11 (ILRCKA), JP12 (SDTIA), JP13 (SDTIA1_SEL), JP14 (SDTIA2_SEL), JP15 (SDTIA3_SEL) Setting of interface signal of PORTB: AK4114 (U10) is as follows.
JP23 BICKB
JP24 LRCKB
JP21 SDTIB_SEL
(short)
(short)
DIR
GND
(GND)
Figure 39. JP23 (BICKB), JP24 (LRCKB), JP21 (SDTIB_SEL) When master clock of AK4683: MCKO is supplied to PORTB: AK4114 (U10): XTI, setting of master clock is as follows.
JP20 XTIB
(short) Figure 40. JP20 (XTIB)
7-4-2-3. Setting of DIP switch Set SW4 (PORTB_DIR): 5pin (CM1) to OFF. Set SW4 (PORTB_DIR): 4pin (CM0) to ON. 7-4-2-4. Setting of toggle switch Set SW3 (DIR PORTA) to OFF. Set SW5 (DIR PORTB) to ON. Set SW1 (PDN) to OFF ON.
- 23 -
2005/08
ASAHI KASEI
[AKD4683-A]
7-5. Internal loop back (Analog input ADC DAC Analog output) 7-5-1. Connection of connector For analog input, RCA connector J1 (LIN1)/ J4 (RIN1), J2 (LIN2)/ J5 (RIN2), J3 (LIN3)/ J6 (RIN3), J7 (LIN4)/ J10 (RIN4), J8 (LIN5)/ J11 (RIN5), J9 (LIN6)/ J12 (RIN6) are available. For analog output, RCA connector J15 (LOUT1)/ J17 (ROUT1), J16 (LOUT2)/ J18 (ROUT2) are available. 7-5-2. Setting of jumper pin Setting of interface signal of PORTA: AK4114 (U7) is as follows.
JP17 BICKA
JP18 OLRCKA
JP11 ILRCKA
JP12 SDTIA
JP14 JP13 SDTIA1_SEL SDTIA2_SEL
JP15 SDTIA3_SEL
(open)
(open)
(open)
(open)
DIR
GND
DIR
GND
DIR
GND
(GND)
(GND)
(GND)
Figure 41. JP17 (BICKA), JP18 (OLRCKA), JP11 (ILRCKA), JP12 (SDTIA), JP13 (SDTIA1_SEL), JP14 (SDTIA2_SEL), JP15 (SDTIA3_SEL) Setting of interface signal of PORTB: AK4114 (U10) is as follows.
JP23 BICKB
JP24 LRCKB
JP21 SDTIB_SEL
(open)
(open)
DIR
GND
(GND)
Figure 42. JP23 (BICKB), JP24 (LRCKB), JP21 (SDTIB_SEL) 7-5-3. Setting of DIP switch SW2 (PORTA_DIR/4683) and SW4 (PORTB_DIR) are "Don't care". 7-5-4. Setting of toggle switch Set SW3 (DIR PORTA) to OFF. Set SW5 (DIR PORTB) to OFF. Set SW1 (PDN) to OFF ON.
- 24 -
2005/08
ASAHI KASEI
[AKD4683-A]
7-6. Headphone output 7-6-1. Connection of connector For headphone output, RCA connector J19 (HPL) and J21 (HPR) or stereo mini jack J20 (HP) are available. 7-6-2. Setting of jumper pin JP8 (HPL) and JP9 (HPR) control headphone output (RCA connector J19 and J21 or stereo mini jack J20).
JP8 HPL
JP8 HPL
RCA (RCA) JP9 HPR
HP
RCA
HP (HP) JP9 HPR
HP
(RCA)
RCA
HP
RCA (HP)
Figure 43. JP8 (HPL), JP9 (HPR) 7-6-3. Setting of DIP switch In case of evaluation mode of DAC using external DIR, settings of DIP switches: SW2 (PORTA_DIR/4683) and SW4 (PORTB_DIR) should be done following to the setting of the evaluation mode. In case of evaluation mode of DAC using internal DIR, settings of DIP switches: SW2 (PORTA_DIR/4683) and SW4 (PORTB_DIR) are "Don't care". 7-6-4. Setting of toggle switch In case of evaluation mode of DAC using external DIR, settings of toggle switches: SW3 (DIR PORTA) and SW5 (DIR PORTB) should be done following to the setting of the evaluation mode. In case of evaluation mode of DAC using internal DIR, settings of toggle switches: SW3 (DIR PORTA) and SW5 (DIR PORTB) are OFF. Set SW1 (PDN) to OFF ON.
- 25 -
2005/08
ASAHI KASEI
[AKD4683-A]
8. Power on
8-1. Toggle switch Switch for power down reset of AK4589. Power down reset of AK4589 will be done by setting SW1 (PDN) to "L" once, after power on. Keep "H" during operation of AK4589. [SW3] (DIR PORTA): Switch for power down reset of PORTA: AK4114 (U7). Power down reset of PORTA: AK4114 (U7) will be done by setting SW3 (DIR PORTA) to "L" once, after power on. Keep "H" during operation of PORTA: AK4114 (U7) . [SW5] (DIR PORTB): Switch for power down reset of PORTB: AK4114 (U10). Power down reset of PORTB: AK4114 (U10) will be done by setting SW5 (DIR PORTB) to "L" once, after power on. Keep "H" during operation of PORTB: AK4114 (U10). 8-2. LED [LE1] (INT): LED for output of AK4683: INT. It turns on when output of AK4683: INT is "H". [LED1] (ERF): LED for output of PORTA: AK4114 (U7): INT0. It turns on when output of PORTA: AK4114 (U7): INT0 is "H". [LED2] (ERF): LED for output of PORTB: AK4114 (U10): INT0. It turns on when output of PORTB: AK4114 (U10): INT0 is "H". 8-3. Reset after power on AK4683, PORTA: AK4114 (U7), PORTB: AK4114 (U10) should be reset by setting SW1 (PDN), SW3 (DIR PORTA), SW5 (DIR PORTB) to "L" once, after power on. [SW1] (PDN):
- 26 -
2005/08
ASAHI KASEI
[AKD4683-A]
Analog Input Circuit
C18 + LIN1 1u J1 LIN1
2 3 1
C19 + LIN2 1u
J2 LIN2
2 3 1
MR-552LS AVSS1 C21 + RIN1 1u J4 RIN1
2 3 1
MR-552LS AVSS1 C22 + RIN2 1u J5 RIN2
2 3 1
MR-552LS AVSS1 AVSS1
MR-552LS
C20 + LIN3 1u
J3 LIN3
2 3 1
C24 + LIN4 1u
J7 LIN4
2 3 1
MR-552LS AVSS1 C23 + RIN3 1u J6 RIN3
2 3 1
MR-552LS AVSS1 C27 + RIN4 1u J10
2 3 1
RIN4
MR-552LS AVSS1 AVSS1
MR-552LS
C25 + LIN5 1u
J8 LIN5
2 3 1
C26 + LIN6 1u
J9 LIN6
2 3 1
MR-552LS AVSS1 C28 + RIN5 1u AVSS1 J11
2 3 1
MR-552LS AVSS1
RIN5 RIN6
C29 + 1u
J12
2 3 1
RIN6
MR-552LS AVSS1
MR-552LS
Figure 44. Analog Input Circuit For analog input, RCA connector: J1 (LIN1)/ J4 (RIN1), J2 (LIN2)/ J5 (RIN2), J3 (LIN3)/ J6 (RIN3), J7 (LIN4)/ J10 (RIN4), J8 (LIN5)/ J11 (RIN5), J9 (LIN6)/ J12 (RIN6) are available to use. Analog inputs are single-ended and input ranges of each channel are nominally 6.1Vpp@5V. Input range: AIN is proportional to AVDD1 (AIN=1.22 x AVDD1=1.22 x 5=6.1).
- 27 -
2005/08
ASAHI KASEI
[AKD4683-A]
Analog Output Circuit
P12V
3 2
C35 22u + LOUT1 R54 10k HVSS
+ -
U5A R55 NJM5532 220
1 2 3 1
J15
LOUT1
N12V 330p C37 HVSS R58 4.7K R59 4.7k
MR-552LS
HVSS
C39 + 22u ROUT1 R62 10k HVSS
5 6
P12V + N12V 330p C42 HVSS R66 4.7K R67 4.7k U5B R63 NJM5532 220
7 2 3 1
J17
ROUT1
MR-552LS
HVSS C36 22u + LOUT2 R56 10k P12V
3 2
+ -
U6A R57 NJM5532 220
1 2 3 1
J16
LOUT2
HVSS
N12V 330p C38 HVSS R60 4.7K R61 4.7k
MR-552LS
HVSS P12V C40 +22u ROUT2 R64 10k HVSS U6B R65 NJM5532 220
7 2 3 1
5 6
+ -
J18
ROUT2
N12V 330p C41 HVSS R68 4.7K R69 4.7k
MR-552LS
HVSS
Figure 45. Analog Output Circuit
For analog output, RCA connector: J15 (LOUT1)/ J17 (ROUT1), J16 (LOUT2)/ J18 (ROUT2) are available to use. Analog outputs are single-ended and output ranges of each channel are nominally 3.0Vpp@5V. Output range: AOUT is proportional to AVDD2 (AOUT=0.6 x AVDD2=0.6 x 5=3.0).
- 28 -
2005/08
ASAHI KASEI
[AKD4683-A]
Digital Input Circuit (Internal DIR)
RX0/1/2/3 PORT3
6 5 6 5 GND VCC GND OUT 4 3 2 1
L1 10u VDD C31 0.1u C32 + 10u
TORX176
R50 OPT 470
PVSS RX0 J14
2 3 1
JP4 RX0 C34 R52 75 PVSS 0.1u RCA
RX0
MR-552LS PVSS
OPT JP5 RX1 GND PVSS RX1
OPT JP6 RX2 GND PVSS RX2
OPT JP7 RX3 GND PVSS RX3
Figure 46. Digital Input Circuit (Internal DIR)
In case of input through RX0, optical connector PORT3 (TORX176) or RCA connector J14 (RX0) are available. In case of input through RX1, RX2 or RX3, only the optical connector PORT3 is available. In case of input through RX0, JP4 (RX0) controls digital input (optical connector PORT3 or RCA connector J14). In case of input through RX1, RX2 or RX3, jumpers JP5 (RX1), JP6 (RX2) or JP7 (RX3) control digital input channels (RX1, RX2 or RX3) from PORT3. About only input channels, set some of jumpers JP5 (RX1), JP6 (RX2) or JP7 (RX3) to OPT. About no-input channels, set other of jumpers JP5 (RX1), JP6 (RX2) or JP7 (RX3) to GND. Digital input: RX0, RX1, RX2 and RX3 is available to select overwriting IPS10 bit of control register (Addr=03H) of AK4683: DIR/DIT part by control software.
Digital Input Circuit (External DIR: PORT A)
J22 PORTA_RX0
2 3 1
C46 R74 75 DGND2 0.1u
MR-552LS DGND2
Figure 47. Digital Input Circuit (External DIR: PORT A) For digital input, RCA connector: J22 (PORTA_RX0) is available.
Digital Input Circuit (External DIR: PORT B)
J25 PORTB_RX0
2 3 1
C56 R80 75 DGND1 0.1u
MR-552LS DGND1
Figure 48. Digital Input Circuit (External DIR: PORT B)
For digital input, RCA connector: J25 (PORTB_RX0) is available.
- 29 -
2005/08
ASAHI KASEI
[AKD4683-A]
Digital Output Circuit (Internal DIT)
TX1 PORT1
5 6 5 6 IN VCC IF GND 4 3 2 1
VDD JP2 R42 1k C30 0.1u DVSS TX1
OPT TX1
TOTX176 DVSS TX1 J13
2 3 1
RCA T1 DA02 R46 330 MR-552LS DVSS R45 100
DVSS
Figure 49. Digital Output Circuit (Internal DIT) For digital output, optical connector PORT1 (TOTX176) or RCA connector J13 (TX1) are available. JP2 (TX1) controls digital output (optical connector PORT1 or RCA connector J13).
Digital Output Circuit (External DIT: PORT A)
J23 PORTA_TX1
2 3 1
T2 DA02
R79 240
MR-552LS
DGND2
R78 150
DGND2
Figure 50. Digital Output Circuit (External DIT: PORT A) For digital output, RCA connector: J23 (PORTA_TX1) is available.
Digital Output Circuit (External DIT: PORT B)
J26 PORTB_TX1
2 3 1
T3 DA02
R85 240
MR-552LS
DGND1
R84 150
DGND1
Figure 51. Digital Output Circuit (External DIT: PORT B) For digital output, RCA connector: J26 (PORTB_TX1) is available.
- 30 -
2005/08
ASAHI KASEI
[AKD4683-A]
+
R70 HPL (short)
RCA JP8 HPL HP HVSS HVSS
6 4 3
2 3 1
J19
HPL
C43 100u
R71 16
MR-552LS
J20
HP
+
R72 HPR (short)
HP JP9 HPR HVSS
01J0154
C44 RCA 100u
R73 16
2 3 1
J21
HPR
MR-552LS HVSS
HVSS
Figure 52. Headphone Output Circuit For headphone output, RCA connector J19 (HPL), J21 (HPR) or stereo mini jack J20 (HP) are available. JP8 (HPL) and JP9 (HPR) control headphone output (RCA connector J19 and J21 or stereo mini jack J20).
- 31 -
2005/08
ASAHI KASEI
[AKD4683-A]
AKD4683 (DIR/DIT) part Control Program operation manual
Set-up of evaluation board and control software
(Note) Control software does not work on Windows NT Windows 2000/XP needs an installation of driver. Windows 95/98/ME does not need an installation of driver. Please refer to "Installation Manual of Control Software Driver by AKM device control software", about the method of installation of driver. AK4683 supports the standard-mode I2C-bus (max: 100kHz), and does not support a fast-mode I2C-bus system (max: 400kHz).
1. Set up the AKD4683-A according to above mentioned setting. 2. Connect printer port (parallel port) of PC and PORT1 (up-I/F) of AKD4683-A by 10-wire flat cable packed with AKD4683-A. Then take care of the direction of 10pin connector and 10-pin header. 3. Insert the CD-ROM labeled "AKD4683-A Control Program ver. 2.0" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "AKD4683-A_dir_dit_2.exe", and set up the control program. 5. Then evaluate AK4683 (DIR/DIT) part according to the follows. (Note) Chip Address of DIR/DIT: CAD1, CAD0 is 0(L), 0(L) fixed. (CAD10=00)
Operation flow
Keep the following flow. 1. 2. 3. Set up the control program according to explanation above. Click Write default button. Then set up the dialog and input data and evaluate AK4683 (DIR/DIT) part.
Explanation of each buttons
1. [Write default]: Write default data into all registers. Default data is indicated on the register map of all registers. Red letter indicates "H" or "1" and blue letter indicates "L" or "0". Blank is the part that is not defined in the datasheet. 2. [All Read]: Read data of all registers. Read data is indicated on the register map of all register. Red letter indicates "H" or "1" and blue letter indicates "L" or "0". Blank is the part that is not defined in the datasheet. 3. [Function1]: Set up dialog to write data by keyboard operation. 4. [Write]: It exists on each register corresponding to all registers. Set up dialog to write data to each register by mouse operation. Set ON/OFF by clicking each bits. Click "OK" button if you write input data to register. Click "Cancel" button if you don't write input data to register. 5. [Read]: It exists on each register corresponding to some registers. Read data from one of each register. Read data is indicated on the register map of the register. Red letter indicates "H" or "1" and blue letter indicates "L" or "0". Blank is the part that is not defined in the datasheet.
- 32 -
2005/08
ASAHI KASEI
[AKD4683-A]
Explanation of each dialog
1. [Function1 Dialog]: Dialog to write data by keyboard operation Address Input Box: Input address of register which data should be written into, in 2 figures of hexadecimal. Data Input Box: Input data which should be written into the register, in 2 figures of hexadecimal. Click "OK" button, if you write input data into register. Click "Cancel" button, if you don't write input data into register. 2. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the "Write" button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". Click "OK" button, if you write input data into register. Click "Cancel" button, if you don't write input data into register.
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue letter indicates "L" or "0". Blank is the part that is not defined in the datasheet.
Attention on the operation
Input data to all boxes when you have set up "Function1 dialog". An "attention dialog" is indicated if you input data or address that is not specified in the datasheet or you click "OK" button before you input data. In that case set up the dialog and input data once more again. These operations does not need if you click "Cancel" button or check the check box.
- 33 -
2005/08
ASAHI KASEI
[AKD4683-A]
AK4683 (ADC/DAC) part Control Program Operation Manual
Set-up of evaluation board and control software
(Note) Control software does not work on Windows NT. Windows 2000/XP needs an installation of driver. Windows 95/98/ME does not need an installation of driver. Please refer to "Installation Manual of Control Software Driver by AKM device control software", about the method of installation of driver. AK4683 supports the standard-mode I2C-bus (max: 100kHz), and does not support a fast-mode I2C-bus system (max: 400kHz).
1. Set up the AKD4683-A according to above mentioned setting. 2. Connect printer port (parallel port) of PC and PORT1 (up-I/F) of AKD4683-A by 10-wire flat cable packed with AKD4683-A. Then take care of the direction of 10pin connector and 10-pin header. 3. Insert the CD-ROM-disk labeled "AKD4683-A Control Program ver. 2.0" into the CD-ROM-disk drive. 4. Access the CD-ROM-disk drive and double-click the icon of "AKD4683-A_adc_dac_2.exe" and set up the control program. 5. Then evaluate AK4683 (ADC/DAC) part according to the followings. (Note) Chip Address of ADC/DAC: CAD1, CAD0 is 1(H), 0(L) fixed, (CAD10=10) Register of ADC/DAC part is "write only", and it cannot be read.
Operation flow
Keep the following flow. 1. 2. 3. Set up the control program according to explanation above Click Write default button. Then set up the dialog and input data and evaluate AK4683 (ADC/DAC) part.
Explanation of each buttons
1. [Write default]: Write default data into all register. Default data is indicated on the register map of all registers. Red letter indicates "H" or "1" and blue letter indicates "L" or "0". Blank is the part that is not defined in the datasheet. 2. [Function1]: Set up dialog to write data by keyboard operation. 3. [Function2]: Set up dialog to write data by keyboard operation. 4. [Write]: It exists corresponding to each register. Set up dialog to write data to each register by mouse operation. Set ON/OFF by clicking each bits. Click "OK" button if you write input data into register. Click "Cancel" button if you don't write input data into register.
- 34 -
2005/08
ASAHI KASEI
[AKD4683-A]
Explanation of each dialog
1. [Function1 Dialog]: Dialog to write data by keyboard operation Address Input Box: Input address of register which data should be written into, in 2 figures of hexadecimal. Data Input Box: Input data which should be written into the register, in 2 figures of hexadecimal. Click "OK" button, if you write input data into register. Click "Cancel" button, if you don't write input data into register. 2. [Function2 Dialog]: Dialog to evaluate ATT of LIN/RIN/LOUT1/ROUT1/LOUT2/ROUT2 Volume Control. This dialog corresponds to addr:0CH, 0DH, 0EH, 0FH, 10H, and 11H. Address Input Box: Input address of register which data should be written into, in 2 figures of hexadecimal. Start Data Input Box: Input first data (start data) which should be written into the register, in 2 figures of hexadecimal. End Data Input Box: Input last data (end data) which should be written into the register, in 2 figures of hexadecimal. Interval Input Box: Input time distance (interval time) between write and write when data is written into the register, in decimal. Unit of time is ms. Step Input Box: Input value distance (step of data) between data and data when data is written into the register, in decimal. Mode Select Check Box: Select mode of data flow, "Data returns to start data after data reached end data." Or "Data flow is end when data reached end data." Set mode of data flow by checked or no into this check box. When you checked into this: Data returns to start data after data reached end data. When you did not check into this: Data flow is end when data reached end data. [Example when you checked into this] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 [Example when you did not check into this] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 Click "OK" button, if you write input data into register. Click "Cancel" button, if you don't write input data into register. 3. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the "Write" button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". Click "OK" button, if you write input data into register. Click "Cancel" button, if you don't write input data into register.
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue letter indicates "L" or "0". Blank is the part that is not defined in the datasheet.
Attention on the operation
Input data to all boxes when you have set up "Function1 dialog" or "Function2 dialog". An "attention dialog" is indicated if you input data or address that is not specified in the datasheet or you click "OK" button before you input data. In that case set up the dialog and input data once more again. These operations does not need if you click "Cancel" button or check the check box.
- 35 -
2005/08
ASAHI KASEI
[AKD4683-A]
Measure Result
1) ADC part [Measurement condition] * Measurement unit : Audio Precision System two Cascade (AP2) * MCLK : 256fs (fs=48kHz), 256fs (fs=96kHz) * BICK : 64fs * fs : 48kHz, 96kHz * BW : 20Hz20kHz (fs=48kHz), 20Hz40kHz (fs=96kHz) * Bit : 24bit * Power Supply : AVDD=PVDD=DVDD=5V, TVDD=3.3V * Interface : Internal DIT (fs=48kHz, 96kHz) * Temperature : Room Temp fs=48kHz Parameter S/(N+D) DR DR S/N S/N fs=96kHz Parameter S/(N+D) DR DR S/N S/N
Input signal 1kHz, -0.5dB 1kHz, -60dB 1kHz, -60dB No signal No signal
Measurement filter 20kLPF 20kLPF 20kLPF, A-weighted 20kLPF 20kLPF, A-weighted
Results 93.1 dB 97.1 dB 100.6 dB 98.2 dB 101.1 dB
Input signal 1kHz, -0.5dB 1kHz, -60dB 1kHz, -60dB No signal No signal
Measurement filter fs/2 fs/2 20kLPF, A-weighted fs/2 20kLPF, A-weighted
Results 92.0 dB 96.3 dB 102.7 dB 96.3 dB 102.9 dB
- 36 -
2005/08
ASAHI KASEI
[AKD4683-A]
2) DAC part [Measurement condition] * Measurement unit : Audio Precision System two Cascade (AP2) * MCLK : 256fs (fs=48kHz, 96kHz), 128fs (fs=192kHz) * BICK : 64fs * fs : 48kHz, 96kHz, 192kHz * BW : 20Hz20kHz (fs=48kHz), 20Hz40kHz (fs=96kHz), 20Hz40kHz (fs=192kHz) * Resolution : 24bit * Power Supply : AVDD=PVDD=DVDD=5V, TVDD=3.3V * Interface : Internal DIR (48kHz, 96kHz, 192kHz) * Temperature : Room Temp fs=48kHz Parameter S/(N+D) DR DR S/N S/N fs=96kHz Parameter S/(N+D) DR DR S/N S/N fs=192kHz Parameter S/(N+D) DR DR S/N S/N
Input signal 1kHz, 0dB 1kHz, -60dB 1kHz, -60dB "0" data "0" data
Measurement filter 20kLPF 20kLPF 22kLPF, A-weighted 20kLPF 22kLPF, A-weighted
Results 94.3 dB 105.0 dB 105.6 dB 103.4 dB 106.0 dB
Input signal 1kHz, 0dB 1kHz, -60dB 1kHz, -60dB "0" data "0" data
Measurement filter 40kLPF 40kLPF 22kLPF, A-weighted 40kLPF 22kLPF, A-weighted
Results 92.3 dB 102.0 dB 105.6 dB 101.0 dB 106.2 dB
Input signal 1kHz, 0dB 1kHz, -60dB 1kHz, -60dB "0" data "0" data
Measurement filter 40kLPF 40kLPF 22kLPF, A-weighted 40kLPF 22kLPF, A-weighted
Results 88.8 dB 102.5 dB 106.2 dB 101.3 dB 106.2 dB
- 37 -
2005/08
ASAHI KASEI
[AKD4683-A]
Plots
1) ADC [Measurement condition] * Measurement Unit * MCLK * BICK * fs * BW * Resolution * Power Supply * Interface * Temperatur
: Audio Precision System two Cascade : 256fs(fs=48kHz), 256fs(fs=96kHz) : 64fs : 48kHz, 96kHz : 20Hz20kHz (fs=48kHz), 40Hz40kHz (fs=96kHz) : 24bit : AVDD=PVDD=DVDD=5V, TVDD=3.3V : Internal DIT (fs=48kHz, 96kHz) : Room Temp
fs=48kHz Figure 7. FFT (Input Frequency =1kHz, Input Level =-0.5dBFS) Figure 8. FFT (Input Frequency =1kHz, Input Level =-60dBFS) Figure 9. FFT (noise floor) Figure 10. THD+N vs Input Level (Input Frequency =1kHz) Figure 11. THD+N vs Input Frequency (Input Level=-0.5dBFS) Figure 12. Linearity (Input Frequency =1kHz) Figure 13. Frequency Response (Input Level=-0.5dBFS) Figure 14. Cross-talk (Input Level=-0.5dBFS) fs=96kHz Figure 15. FFT (Input Frequency =1kHz, Input Level =-0.5dBFS) Figure 16. FFT (Input Frequency =1kHz, Input Level =-60dBFS) Figure 17. FFT (noise floor) Figure 18. THD+N vs Input Level (Input Frequency =1kHz) Figure 19. THD+N vs fin (Input Level=-0.5dBFS) Figure 20. Linearity (Input Frequency =1kHz) Figure 21. Frequency Response (Input Level=-0.5dBFS) Figure 22. Cross-talk (Input Level=-0.5dBFS) FFT point=16384, Avg=8, Window=Equirriple
- 38 -
2005/08
ASAHI KASEI
[AKD4683-A]
2) DAC [Measurement Condition] * Measurement Unit * MCLK * BICK * fs * BW * Resolution * Power Supply * Interface * Temperature
: Audio Precision System two Cascade : 256fs(fs=48kHz, 96kHz), 128fs(fs=192kHz) : 64fs : 48kHz, 96kHz, 192kHz : 20Hz20kHz (fs=48kHz), 40Hz40kHz (fs=96kHz), 40Hz80kHz (fs=192kHz) : 24bit : AVDD=PVDD=DVDD=5V, TVDD=3.3V : Internal DIR (48kHz, 96kHz, 192kHz) : Room Temp
fs=48kHz Figure 23. FFT (Input Frequency =1kHz, Input Level =0dBFS) Figure 24. FFT (Input Frequency =1kHz, Input Level =-60dBFS) Figure 25. FFT (noise floor) Figure 26. FFT (out-of-band noise) Figure 27. THD+N vs Input Level (Input Frequency =1kHz) Figure 28. THD+N vs Input Frequency (Input Level=0dBFS) Figure 29. Linearity (Input Frequency =1kHz) Figure 30. Frequency Response (Input Level=0dBFS) Figure 31. Cross-talk (Input Level=0dBFS) fs=96kHz Figure 32. FFT (Input Frequency =1kHz, Input Level =0dBFS) Figure 33. FFT (Input Frequency =1kHz, Input Level =-60dBFS) Figure 34. FFT (noise floor) Figure 35. FFT (out-of-band noise) Figure 36. THD+N vs Input Level (Input Frequency =1kHz) Figure 37. THD+N vs fin (Input Level=0dBFS) Figure 38. Linearity (Input Frequency =1kHz) Figure 39. Frequency Response (Input Level=0dBFS) Figure 40. Cross-talk (Input Level=0dBFS) fs=192kHz Figure 41. FFT (Input Frequency =1kHz, Input Level =0dBFS) Figure 42. FFT (Input Frequency =1kHz, Input Level =-60dBFS) Figure 43. FFT (noise floor) Figure 44. FFT (out-of-band noise) Figure 45. THD+N vs Input Level (Input Frequency =1kHz) Figure 46. THD+N vs fin (Input Level=0dBFS) Figure 47. Linearity (Input Frequency =1kHz) Figure 48. Frequency Response (Input Level=0dBFS) Figure 49. Cross-talk (Input Level=0dBFS) FFT point=16384, Avg=8, Window=Equirriple
- 39 -
2005/08
ASAHI KASEI
[AKD4683-A]
1.ADC (ADC fs=48kHz)
AKM
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Red=Lch,Blu=Rch
Figure 1. FFT(Input Frequency=1kHz,Input Level=-0.5dBFS)
AKM
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200
Red=Lch,Blu=Rch
500 Hz
1k
2k
5k
10k
20k
Figure 2. FFT(Input Frequency=1kHz,Input Level=-60dBFS)
- 40 -
2005/08
ASAHI KASEI
[AKD4683-A]
(ADC fs=48kHz)
AKM
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Red=Lch,Blu=Rch
Figure 3. FFT(noise floor)
AKM
-80 -82 -84 -86 -88 -90 -92 -94 -96 d B F S -98 -100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 -140 -130 -120 -110 -100 -90
Red=Lch,Blu=Rch
-80
-70 dBr
-60
-50
-40
-30
-20
-10
+0
Figure 4. THD + N vs Input Level(Input Frequency=1kHz)
- 41 -
2005/08
ASAHI KASEI
[AKD4683-A]
(ADC fs=48kHz)
AKM
-80 -82 -84 -86 -88 -90 -92 -94 -96 d B F S -98 -100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Red=Lch,Blu=Rch
Figure 5. THD + N vs Input Frequency (Input Level=-0.5dBFS)
AKM
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -140
Red=Lch,Blu=Rch
-130
-120
-110
-100
-90
-80
-70 dBr
-60
-50
-40
-30
-20
-10
+0
Figure 6. Linearity (Input Frequency=1kHz)
- 42 -
2005/08
ASAHI KASEI
[AKD4683-A]
(ADC fs=48kHz)
AKM
-0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 d B F S -0.45 -0.5 -0.55 -0.6 -0.65 -0.7 -0.75 -0.8 -0.85 -0.9 -0.95 -1 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Red=Lch,Blu=Rch
Figure 7. Frequency Response (Input Level=-0.5dBFS)
AKM
-70 -75 -80 -85 -90 -95 -100 d B -105 -110 -115 -120 -125 -130 -135 -140 20
Red=Lch,Blu=Rch
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 8. Crosstalk (Input Level=-0.5dBFS)
- 43 -
2005/08
ASAHI KASEI
[AKD4683-A]
(ADC fs=96kHz)
AKM
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
Red=Lch,Blu=Rch
Figure 9. FFT(Input Frequency=1kHz,Input Level=-0.5dBFS)
AKM
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500
Red=Lch,Blu=Rch
1k Hz
2k
5k
10k
20k
40k
Figure 10. FFT(Input Frequency=1kHz,Input Level=-60dBFS)
- 44 -
2005/08
ASAHI KASEI
[AKD4683-A]
(ADC fs=96kHz)
AKM
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
Red=Lch,Blu=Rch
Figure 11. FFT(Noise floor)
AKM
-80 -82 -84 -86 -88 -90 -92 -94 -96 d B F S -98 -100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 -140 -130 -120 -110 -100 -90
Red=Lch,Blu=Rch
-80
-70 dBr
-60
-50
-40
-30
-20
-10
+0
Figure 12. THD + N vs Input Level (Input Frequency=1kHz)
- 45 -
2005/08
ASAHI KASEI
[AKD4683-A]
(ADC fs=96kHz)
AKM
-80 -82 -84 -86 -88 -90 -92 -94 -96 d B F S -98 -100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 40 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
Red=Lch,Blu=Rch
Figure 13. THD + N vs Input Frequency (Input Level=-0.5dBFS)
AKM
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -140
Red=Lch,Blu=Rch
-130
-120
-110
-100
-90
-80
-70 dBr
-60
-50
-40
-30
-20
-10
+0
Figure 14. Linearity (Input Frequency=1kHz)
- 46 -
2005/08
ASAHI KASEI
[AKD4683-A]
(ADC fs=96kHz)
AKM
-0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 d B F S -0.45 -0.5 -0.55 -0.6 -0.65 -0.7 -0.75 -0.8 -0.85 -0.9 -0.95 -1 40 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
Red=Lch,Blu=Rch
Figure 15. Frequency Response (Input Level=-0.5dBFS)
AKM
-70 -75 -80 -85 -90 -95 -100 d B -105 -110 -115 -120 -125 -130 -135 -140 40
Red=Lch,Blu=Rch
50
100
200
500
1k Hz
2k
5k
10k
20k
40k
Figure 16. Crosstalk (Input Level=-0.5dBFS)
- 47 -
2005/08
ASAHI KASEI
[AKD4683-A]
2.DAC (DAC fs=48kHz)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Red=Lch,Blu=Rch
Figure 17. FFT(Input Frequency=1kHz, Input Level=0dBFS)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200
Red=Lch,Blu=Rch
500 Hz
1k
2k
5k
10k
20k
Figure 18. FFT(Input Frequency=1kHz, Input Level=-60dBFS)
- 48 -
2005/08
ASAHI KASEI
[AKD4683-A]
(DAC fs=48kHz)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Red=Lch,Blu=Rch
Figure 19. FFT(noise floor)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 100 200 500 1k
Red=Lch,Blu=Rch
2k Hz
5k
10k
20k
50k
100k
Figure 20. FFT(out-of-band noise)
- 49 -
2005/08
ASAHI KASEI
[AKD4683-A]
(DAC fs=48kHz)
AKM
-80 -82 -84 -86 -88 -90 -92 -94 -96 d B r A -98 -100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 -140 -130 -120 -110 -100 -90 -80 -70 dBFS -60 -50 -40 -30 -20 -10 +0
Red=Lch,Blu=Rch
Figure 21. THD+N vs Input Level (Input Frequency=1kHz)
AKM
-70 -72 -74 -76 -78 -80 -82 -84 -86 d B r A -88 -90 -92 -94 -96 -98 -100 -102 -104 -106 -108 -110 20 50 100 200
Red=Lch,Blu=Rch
500 Hz
1k
2k
5k
10k
20k
Figure 22. THD+N vs Input Frequency (Input Level=0dBFS)
- 50 -
2005/08
ASAHI KASEI
[AKD4683-A]
(DAC fs=48kHz)
AKM
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -140
Red=Lch,Blu=Rch
-130
-120
-110
-100
-90
-80
-70 dBFS
-60
-50
-40
-30
-20
-10
+0
Figure 23. Linearity (Input Frequency=1kHz)
AKM
+0.5 +0.45 +0.4 +0.35 +0.3 +0.25 +0.2 +0.15 +0.1 d B r A +0.05 +0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 -0.45 -0.5 2k 4k 6k 8k
Red=Lch,Blu=Rch
10k Hz
12k
14k
16k
18k
20k
Figure 24. Frequency Response (Input Level=0dBFS)
- 51 -
2005/08
ASAHI KASEI
[AKD4683-A]
(DAC fs=48kHz)
AKM
-90 -92 -94 -96 -98 -100 -102 -104 -106 -108 d B -110 -112 -114 -116 -118 -120 -122 -124 -126 -128 -130 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Red=Lch,Blu=Rch
Figure 25. Cross-talk (Input Level=0dBFS)
- 52 -
2005/08
ASAHI KASEI
[AKD4683-A]
(DAC fs=96kHz)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
Red=Lch,Blu=Rch
Figure 26. FFT(Input Frequency=1kHz, Input Level=0dBFS)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500
Red=Lch,Blu=Rch
1k Hz
2k
5k
10k
20k
40k
Figure 27. FFT(Input Frequency=1kHz, Input Level=0dBFS,Notch-on)
- 53 -
2005/08
ASAHI KASEI
[AKD4683-A]
(DAC fs=96kHz)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
Red=Lch,Blu=Rch
Figure 28. FFT(Input Frequency=1kHz, Input Level=-60dBFS)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500
Red=Lch,Blu=Rch
1k Hz
2k
5k
10k
20k
40k
Figure 29. FFT(noise floor)
- 54 -
2005/08
ASAHI KASEI
[AKD4683-A]
(DAC fs=96kHz)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 100
Red=Lch,Blue=Rch
200
500
1k
2k Hz
5k
10k
20k
50k
100k
Figure 30. FFT (out-of-band noise)
AKM
-80 -82 -84 -86 -88 -90 -92 -94 -96 d B r A -98 -100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 -140 -130 -120 -110 -100 -90
Red=Lch,Blu=Rch
-80
-70 dBFS
-60
-50
-40
-30
-20
-10
+0
Figure 31. THD+N vs Input Level (Input Frequency=1kHz)
- 55 -
2005/08
ASAHI KASEI
[AKD4683-A]
(DAC fs=96kHz)
AKM
-80 -82 -84 -86 -88 -90 -92 -94 -96 d B r A -98 -100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 40 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
Red=Lch,Blu=Rch
Figure 32. THD+N vs Input Frequency (Input Level=0dBFS)
AKM
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -140
Red=Lch,Blu=Rch
-130
-120
-110
-100
-90
-80
-70 dBFS
-60
-50
-40
-30
-20
-10
+0
Figure 33. Linearity (Input Frequency=1kHz)
- 56 -
2005/08
ASAHI KASEI
[AKD4683-A]
(DAC fs=96kHz)
AKM
+0.1 +0.05 -0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 d B r A -0.35 -0.4 -0.45 -0.5 -0.55 -0.6 -0.65 -0.7 -0.75 -0.8 -0.85 -0.9 2.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k Hz 22.5k 25k 27.5k 30k 32.5k 35k 37.5k 40k
Red=Lch,Blu=Rch
Figure 34. Frequency Response (Input Level=0dBFS)
AKM
-80 -82.5 -85 -87.5 -90 -92.5 -95 -97.5 -100 -102.5 d B -105 -107.5 -110 -112.5 -115 -117.5 -120 -122.5 -125 -127.5 -130 40 50 100 200 500
Red=Lch,Blu=Rch
1k Hz
2k
5k
10k
20k
40k
Figure 35. Cross-talk (Input Level=0dBFS)
- 57 -
2005/08
ASAHI KASEI
[AKD4683-A]
(DAC fs=192kHz)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k 2k Hz 5k 10k 20k 50k 80k
Red=Lch,Blu=Rch
Figure 36. FFT(Input Frequency=1kHz, Input Level=0dBFS)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500
Red=Lch,Blu=Rch
1k
2k Hz
5k
10k
20k
50k
80k
Figure 37. FFT(Input Frequency=1kHz, Input Level=0dBFS,Notch-on)
- 58 -
2005/08
ASAHI KASEI
[AKD4683-A]
(DAC fs=192kHz)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k 2k Hz 5k 10k 20k 50k 80k
Red=Lch,Blu=Rch
Figure 38. FFT(Input Frequency=1kHz, Input Level=-60dBFS)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500
Red=Lch,Blu=Rch
1k
2k Hz
5k
10k
20k
50k
80k
Figure 39. FFT(noise floor)
- 59 -
2005/08
ASAHI KASEI
[AKD4683-A]
(DAC fs=192kHz)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 100 200 500 1k 2k Hz 5k 10k 20k 50k 100k
Red=Lch,Blu=Rch
Figure 40. FFT(out-of-band noise)
AKM
-80 -82 -84 -86 -88 -90 -92 -94 -96 d B r A -98 -100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 -140 -130 -120 -110 -100 -90
Red=Lch,Blu=Rch
-80
-70 dBFS
-60
-50
-40
-30
-20
-10
+0
Figure 41. THD+N vs Input Level (Input Frequency=1kHz)
- 60 -
2005/08
ASAHI KASEI
[AKD4683-A]
(DAC fs=192kHz)
AKM
-80 -82 -84 -86 -88 -90 -92 -94 -96 d B r A -98 -100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 40 50 100 200 500 1k 2k Hz 5k 10k 20k 50k 80k
Red=Lch,Blu=Rch
Figure 42. THD+N vs Input Frequency (Input Level=0dBFS)
AKM
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -140
Red=Lch,Blu=Rch
-130
-120
-110
-100
-90
-80
-70 dBFS
-60
-50
-40
-30
-20
-10
+0
Figure 43. Linearity (Input Frequency=1kHz)
- 61 -
2005/08
ASAHI KASEI
[AKD4683-A]
(DAC fs=192kHz)
AKM
+0.2 +0 -0.2 -0.4 -0.6 -0.8 -1 d B r A -1.6 -1.8 -2 -2.2 -2.4 -2.6 5k 10k 15k 20k 25k 30k 35k 40k Hz 45k 50k 55k 60k 65k 70k 75k 80k -1.2 -1.4
Red=Lch,Blu=Rch
Figure 44. Frequency Response (Input Level=0dBFS)
AKM
-70 -75 -80 -85 -90 -95 d B -100 -105 -110 -115 -120 -125 -130 40
Red=Lch,Blu=Rch
50
100
200
500
1k
2k Hz
5k
10k
20k
50k
80k
Figure 45. Cross-talk (Input Level=0dBFS)
- 62 -
2005/08
ASAHI KASEI
[AKD4683-A]
Revision History
Date (YY/MM/DD) 05/03/10 05/04/05 Manual Revision KM077501 KM077502 Board Reason Contents Revision 0 First Edition 1 Circuit Change Board REV Change: REV.0 REV.1 Resistance Value Change R45: 150 100 R46: 240 330 1 Measurement Device Revision Change: Rev.A Rev.C Result Change Measurement Result Change (ADC part: fs=48KHz, DAC part: fs=48KHz) Plots Add (ADC part:fs=48KHz,96KHz, DAC part:fs=48KHz,96KHz,192KHz) 1 Measurement Measurement Result Change (DAC part: fs=48KHz, Result Change 96KHz, 192KHz)
05/07/19
KM077503
05/08/03
KM077504
IMPORTANT NOTICE
* These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
- 63 -
2005/08
5
4
3
2
1
RIN6
LIN6
RIN5
LIN5
RIN4
LIN4
RIN3
LIN3
RIN2
LIN2
RIN1
LIN1
AVDD1
PVSS
64pin_4 CN1
AVSS1
D
D
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
R1 47k PVSS R13 12k
61
R2 47k
R3 47k
R4 47k
R5 47k
R6 47k
R7 47k
R8 47k
R9 47k
R10 47k
R11 47k
R12 47k
10u C1 + 0.1u C2
49
AVSS1
49 AVSS1
59
57
55
53
62
60
58
56
54
52
51
U1 C3 10u
1
LIN6
LIN5
LIN4
LIN3
LIN2
LIN1
AVDD1
RIN6
RIN5
RIN4
RIN3
RIN2
PVSS
RIN1
PVDD
RX0
2
I2C
C
3
RX1
4
RX2
5
C5 0.1u RX3
6 6 RX3 AVDD2 43
INT
7
7
INT
VCOM
42
C7 0.1u
41
8
8
VOUT
R16 (short) CDTO R17 (short) LRCKB R18 (short) BICKB R19 (short) SDTOB R20 (short) OLRCKA
B
AK4683
C8 + 2.2u
ROUT1
9
TST1
9
CDTO
LOUT1
40
10
10
LRCKB
ROUT2
39
11
11
BICKB
LOUT2
38
12
12
SDTOB
MUTET
37
C9
13 13 OLRCKA HPL 36
+
1u
R21 (short) ILRCKA R22 (short) BICKA R23 (short) SDTOA
16 16 SDTOA SDTIA1 SDTIA2 SDTIA3 MCLK2 MCKO SDTIB DVDD DVSS TVDD CCLK CDTI PDN CSN XTO HVDD 33 15 15 BICKA HVSS 34 34 14 14 ILRCKA HPR 35 35
C10 0.1u
C11 10u
XTI
64pin_1
TX
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
12.288MHz C12 0.1u + C13 0.1u
1
X1
2
C14 10u
C15 10u
C16 5p
C17 5p
DVSS
DVSS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
32
32
CN4 64pin_2 DVSS MCKO 4683_TVDD DVDD PDN R24 (short) TX R25 (short) R26 R27 R28 R29 R30 R31 R32
(short) (short) (short) (short) (short) (short) (short)
MCLK2
CDTI/SDA
CCLK/SCL
SDTIA1
SDTIA2
SDTIA3
SDTIB
CSN
MCKI
5
4
3
+
+ +
+
CN2
C4 0.1u
1 PVDD
R
64
63
50
64pin_3
RISEL 48 48
2
RX0
ROPIN
47
R15 24k
47
3
I2C
LOPIN
46
46
4
RX1
LISEL
45
R14 24k
45
C
5
RX2
AVSS2
44
44
C6 10u
HVSS
43
HVSS AVDD2
42
HVSS
41
ROUT1
40
LOUT1
39
ROUT2
38
LOUT2
37
HVSS
36
HPL
B
HPR
HVSS
33
HVSS HVDD
CN3
+
A
Title Size
Document Number
AKD4683-A
AK4683
Sheet
Rev
A2
Date:
2 1
1 1
of
Tuesday, April 05, 2005
7
5
4
3
2
1
C18 + LIN1 1u
D
+
2 3 1
LIN2 1u MR-552LS
2 3 1
+
J1 LIN1
C19
J2 LIN2 LIN3
C20
2 3 1
J3 LIN3
1u MR-552LS
MR-552LS
D
AVSS1 C21 + RIN1 1u
2 3 1
AVSS1 + RIN2 1u MR-552LS
2 3 1
AVSS1 + J5 RIN2 RIN3 1u MR-552LS C23
2 3 1
J4 RIN1
C22
J6 RIN3
MR-552LS AVSS1
AVSS1
AVSS1
C24 + LIN4 1u
C
+
2 3 1
LIN5 1u MR-552LS
2 3 1
+
J7 LIN4
C25
J8 LIN5 LIN6
C26
2 3 1
J9 LIN6
1u MR-552LS
MR-552LS AVSS1
C
AVSS1 C27 + RIN4 1u
2 3 1
AVSS1 + RIN5 1u MR-552LS
2 3 1
+
J10
RIN4
C28
J11
RIN5 RIN6
C29
2 3 1
J12
RIN6
1u MR-552LS
MR-552LS AVSS1
AVSS1
AVSS1
B
B
A
A
Title Size Document Number
AK4683-A
LIN/RIN
Sheet
1
A3
Date:
5 4 3 2
Rev 1 of
Tuesday, April 05, 2005
2
7
5
4
3
2
1
VDD U2 VDD R33 R35 R40 10k 10k 10k R34 R38 R36 470 470 470
2 3 5 6 11 10 14 13 1 15 1A 1B 2A 2B 3A 3B 4A 4B A/B G 1Y 2Y 3Y 4Y 4 7
TX R37 R39 U3A
9 12 1 2
100 100 100 100
CSN CCLK/SCL CDTI/SDA CDTO DVSS
PORT1
5 6 5 6 IN VCC IF GND 4 3 2 1
VDD JP2 R42 1k C30 0.1u DVSS TX1
OPT TX RCA
D
R41 R43
74LS07 VDD
TOTX176
D
PORT2 A1-10PA-2.54DSA
1 2 3 4 5 10 9 8 7 6
TX J13
2 3 1
CSN SCL/CCLK SDA/CDTI SDA(ACK)/CDTO
74HCT157 R44 (short) DGND2 MR-552LS R48 10k
T1 DA02
R46 330
DVSS
R45 100
DGND2
uP-I/F
VDD
R47
(open) JP3
VDD DVSS RX0/1/2/3 SDA/CDTO DGND2 PORT3
6 5 6 5 GND VCC GND OUT 4 3 2 1
SDA CDTO/CM0=H CM0=L
L1 10u VDD C31 0.1u C32 + 10u R50 OPT 470
VDD D1 1S1588 R49 VDD 10k U4A
1
C
TORX176 VDD U4B
3 4
R51 PDN PVSS RX0 J14
2 3 1
2
JP4 RX0 C34 R52 75 PVSS 0.1u RCA
RX0
C
H SW1 ATE1D-2M3 PDN
L C33 0.1u
74HC14
74HC14 100
MR-552LS DGND2 LE1 R53 1k 4683_TVDD U13A
2 1
PVSS
4683_TVDD PR4553K
INT
OPT JP5 RX1 PVSS RX1 GND
OPT JP6 RX2 PVSS RX2 GND
OPT JP7 RX3 PVSS RX3 GND
74HC14
B
JP1 DGND
B
DGND2
DVSS
A
A
Title Size Document Number
AKD4683-A
INPUT/OUTPUT
Sheet
1
Rev
A3
Date:
5 4 3 2
1
of
Tuesday, April 05, 2005
3
7
5
4
3
2
1
+
+
D
LOUT1 R54 10k HVSS
3+ 2-
J15
2 3 1
LOUT1 LOUT2
8
C35 22u
P12V U5A R55 NJM5532 220
1
C36 22u R56 10k
3+ 2-
P12V R57 U6A NJM5532 220
1 2 3 1
8
D
J16
LOUT2
N12V HVSS
4
330p C37 HVSS
N12V 330p C38 HVSS
4
MR-552LS
MR-552LS
R58 4.7K
R59 4.7k
R60 4.7K
R61 4.7k
HVSS HVSS
P12V + J17
2 3 1
C
ROUT1 R62 10k HVSS
5+ 6-
ROUT1
+
C39 22u
P12V U5B R63 NJM5532 220
7
C40 22u R64 10k
8
8
ROUT2
5+ 6-
U6B R65 NJM5532 220
7 2 3 1
J18
ROUT2
C
N12V 330p C42
4
MR-552LS HVSS HVSS
N12V 330p C41
4
MR-552LS
HVSS R66 4.7K R67 4.7k R68 4.7K R69 4.7k
HVSS
HVSS
J19
B
HPL
B
RCA + R70 HPL (short) C43 100u HP HVSS HVSS
6 4 3
2 3 1
JP8 HPL
R71 16
MR-552LS
J20
HP
HP + R72 HPR (short) C44 RCA 100u JP9 HPR HVSS
01J0154
HPR J21 R73 16
2 3 1
MR-552LS HVSS
A
HVSS
A
Title Size Document Number
AKD4683-A
LOUT/ROUT
Sheet
1
Rev
A3
Date:
5 4 3 2
1
of
Tuesday, April 05, 2005
4
7
A
B
C
D
E
DGND2 C45 10u
2 1
D3.3V D3.3V R75 10k D3.3V U14B D3.3V U14A
3 2 1 K
J22 PORTA_RX0
2 3 1
E
C46 R74 75 DGND2 DGND2 C48 0.47u 0.1u
MR-552LS DGND2 DVDD D3.3V PORT A_DIR/4683
C47 0.1u
R76 18k
4
74HC14
74HC14
L C49 0.1u
A
+
D2 HSU119
E
H SW3 ATE1D-2M3 DIR PORTA
45
41
39
47
43
48
46
44
42
40
38
DIF0 DIF1 DIF2 CM0 CM1 OCKS0 OCKS1 I2C
D
SW2
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
U7
VCOM
AVSS
R
TEST1
AVDD
NC
NC
INT1
RX3
RX2
RX1
RX0
37
D3.3V U8A
INT0 36 1 2
R77 1k
K
LED1 ERF
A
1
IPS0
D3.3V DGND2
74HC04
2 NC OCKS0 35
OCKS0
D
RP1
9 8 7 6 5 4 3 2 1 3 DIF0 OCKS1 34
OCKS1
CM0 CM1 OCKS0 OCKS1 I2C
4
TEST2
CM1
33
CM1
5
DIF1
CM0
32
CM0
47k DGND2
6 NC
DIF2
XTI
1
7
AK4114
PDN
31
C50 (open)
30
JP10 XTIA MCKO
X2 11.2896MHz
C
C51 (open)
C
IPS1
XTO
2
8
29
DGND2
9 P/SN DAUX 28
DGND2 SDTOA MCLK2
10 XTL0 MCKO2 27
BICKA OLRCKA
11
XTL1
BICK
26
JP12 SDTIA
12 VIN MCKO1 DVDD COUT UOUT BOUT VOUT DVSS DVSS TVDD LRCK TX0 TX1 SDTO 25
JP11 ILRCKA JP13 SDTIA1_SEL DIR GND JP14 SDTIA2_SEL DIR GND JP15 SDTIA3_SEL
B
ILRCKA
SDTIA1
13
14
15
16
17
18
19
20
21
22
23
DGND2
B
C52 0.1u +
C53 0.1u +
24
SDTIA2
1
2
1
2
C54 10u 4114_TVDD J23 PORTA_TX1
2 3 1
C55 10u DGND2 D3.3V DGND2 MCKO2 MCKO1
DIR JP16 MCLKA_SEL DGND2 GND
1 2 3 4 5 10 GND 9 MCKO 8 SDTIA1 7 SDTIA2 6 SDTIA3
SDTIA3
T2 DA02
R79 240
JP17 BICKA R78 150 JP18 OLRCKA
MCLK BICKA OLRCKA SDTOA ILRCKA
MR-552LS
DGND2
PORT A PORT4 A1-10PA-2.54DSA DGND2
VDD
A
DGND2
J24 MCKI
2 3 1 1
U9A
2
JP19 MCLK_SEL MCKI MCLK2
A
MCKI MCLK2
Title Size Document Number
74VHC04 DVSS
MR-552LS
AKD4683-A
PORT A
Sheet
E
Rev
A3
Date:
D
1 5
of
Tuesday, April 05, 2005
7
A
B
C
5
4
3
2
1
DGND1 C57 10u
2 1
D3.3V D3.3V R81 10k
K
J25 PORTB_RX0
2 3 1
C56 R80 75 DGND1 DGND1 C59 0.47u 0.1u
C58 0.1u D3.3V R82 18k U14C
6 5
+
MR-552LS
D
DGND1
U14D
8 9
D3.3V PORT B_DIR
45 41 39 47 43 48 46 44 42 40 38 37
74HC14
74HC14
L C60 0.1u
A
D3.3V
D3 HSU119
D
H SW5 ATE1D-2M3 DIR PORTB
SW4 DIF0 DIF1 DIF2 CM0 CM1 OCKS0 OCKS1
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
U10
VCOM
AVSS
TEST1
AVDD
NC
NC
INT1
RX3
RX2
RX1
RX0
D3.3V U8B
3 INT0 36 4
R
R83 1k
K
LED2 ERF
A
1
D3.3V DGND2
IPS0
74HC04
35
2
OCKS0
NC
OCKS0
RP2
9 8 7 6 5 4 3 2 1 3 DIF0 OCKS1 34
OCKS1
C
CM0 CM1 OCKS0 OCKS1
4
TEST2
CM1
33
CM1
C
5
47k DGND1
6
DIF1
CM0
32
CM0
NC
7
DIF2
AK4114
PDN
31
C61 (open)
30 1
JP20 XTIB MCKO
XTI
X3 11.2896MHz
29 2
C62 (open)
8
IPS1
XTO
DGND1
9 P/SN DAUX 28
DGND1 SDTOB
10
XTL0
MCKO2
27
MCLK2
11
B
XTL1
BICK
26
BICKB
B
LRCKB
12 VIN MCKO1 DVDD COUT UOUT BOUT VOUT DVSS DVSS TVDD LRCK TX0 TX1 SDTO 25
JP21 SDTIB_SEL DIR SDTIB GND DGND1
13
14
15
16
17
18
19
20
21
22
23
C63 0.1u +
C64 0.1u +
1
2
1
2
C65 10u 4114_TVDD J26 PORTB_TX1
2 3 1
C66 10u DGND1 D3.3V MCKO2 DGND1 MCKO1
24
DGND1
JP22 MCLKB_SEL
MCLK BICKB LRCKB SDTOB
PORT5 A1-10PA-2.54DSA
1 2 3 4 5 10 GND 9 MCKO 8 SDTIB 7 6
DGND1
T3 DA02
R85 240
JP23 BICKB DGND1 R84 150 JP24 LRCKB
MR-552LS
A
PORT B
A
DGND1
Title Size Document Number
AKD4683-A
PORT B
Sheet
1
A3
Date:
5 4 3 2
Rev 1
Tuesday, April 05, 2005
6
of
7
5
4
3
2
1
AVDD1 L2 (short) + C67 47u AVSS1
D
JP25
AVDD1 REG
3
T4 NJM78M05FA
GND OUT IN 1
+12V R87 P12V
-12V R86 N12V C72 47u HVSS C73 0.1u (short)
D
AVDD1_SEL
AVDD1 AVDD2 L3 (short) + C74 47u HVSS AVDD2 DVDD L5 + C76 47u (short) JP28 DVDD AVDD1 DVDD_SEL R88 DVDD (short) PVDD L7 (short) + C78 47u PVSS PVDD PVDD JP30 AVDD1 PVDD_SEL PVSS VDD VDD HVDD JP26 AVDD2 AVDD1 AVDD2_SEL HVDD AVSS1
AVSS1
AVSS1
HVSS
HVSS HVSS
L4 + C75 47u HVSS (short) JP27 HVDD AVDD1 HVDD_SEL
C
DVSS
L6 (short) + C77 47u DVDD VDD_SEL JP29 VDD DVDD
for NJM5532 x2 T5 TA48M033F
IN GND OUT 1
N12V C100 0.1u C80 0.1u C81 + 47u + +
L8
B
(short) + C82 47u DVSS L9 4683_TVDD (short) L11 4114_TVDD (short)
TVDD(4683) JP32 REG2 TVDD_SEL L10 D3.3V (short) DVSS P12V
2
TVDD(4683)
JP31 DVDD
C79 0.1u
HVSS
C104 10u
for NJM5532 x2 VDD C102 0.1u + +
HVSS U14F
13 12
C106 10u
74HC14 U3B
3 4 3
U9B
4 11
U14E
10 13
U13F
12
for 74HC04(U8) ,74HC14(U14) D3.3V C84 0.1u C85 0.1u 4683_TVDD
74LS07 U3C
5 6 5
U8C
6 5
74VHC04 U9C
6 13
74HC14 U4F
12 11
74HC14 U13E
10
74LS07 U3D
9
A
74HC04 U8D
9 8 9
8
74VHC04 U9D
8 11
74HC14 U4E
10 9
74HC14 U13D
8
DGND2 for 74HCT157(U2), 74HC14(U4), 74LS07(U3) VDD C88 0.1u C89 0.1u C90 0.1u
74LS07 U3E
11 10 11
74HC04 U8E
10 11
74VHC04 U9E
10 9
74HC14 U4D
8 5
74HC14 U13C
6
74LS07 U3F
13 12 13
74HC04 U8F
12 13
74VHC04 U9F
12 5
74HC14 U4C
6 3
74HC14 U13B
4
74LS07
74HC04 DVSS
4
74VHC04 DGND2
74HC14 DGND2
74HC14
DGND2
DGND2
5
DGND2
3
+
+ C68 47u
C69 0.1u
C70 0.1u
2
+
C71 47u
(short)
C
C101 0.1u
C105 10u
for 74VHC04(U9)
B
C83 0.1u
C103 0.1u
C107 10u
DVSS
for 74HC14(U13)
C86 0.1u
DGND2
A
Title Size Document Number
AKD4683-A
Power Supply
Sheet
1
Rev
A3
Date:
2
1
of
Tuesday, April 05, 2005
7
7

▲Up To Search▲

Price & Availability of AKD4683-A

	To Download AKD4683-A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .