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ASAHI KASEI
[AKD4702]
AKD4702
Evaluation board Rev.A for AK4702
GENERAL DESCRIPTION AKD4702 is an evaluation board for quickly evaluating the AK4702 , 2ch DAC with AV SCART switch. Evaluation requires a audio/video analog analyzer, an analog video signal source, a digital audio signal source, and a power supply. AKM's ADC evaluation board can be also used for the audio source. Also included is a AK4112B digital audio interface receiver which receives SPDIF compatible audio data. The digital audio data is available via optical connector or BNC.
AKD4702 --Evaluation board for AK4702 (Cable for connecting with printer port of IBM-AT compatible PC and control software are enclosed with board.)
FUNCTION < BNC connectors for analog audio input/output < BNC connectors for analog video input/output < On-board clock generator < BNC connector for an external clock input < Compatible with 2 types of digital interface 1. Serial interface: Direct interface with evaluation boards for AKM's A/D converter evaluation boards. 2. S/PDIF: On-board AK4112BVF as DIR that accepts optical input or BNC input < 10pin header for serial control interface
D5V VVD2 VVD1
JP10
+5V
Reg.
+12V
Gnd
PORT3 P-IF Control Data 10pin Heder Port1
AD DATA ROM DATA 10pin Header
JP11
(Digital)
JP8 JP9
TVOUTR VCROUTR TVINL VCRINL VCRSB VCRB TVSB VCRINR TVINR MONOIN VCROUTL
JP2~ 5
RX
PORT2 Opt In
JP6
DIR
RFV
J1 EXT JP1 Clock Generator
AK4702
VCRVOUT
TVFB
JP12
VCRC
TVRC
TVB
TVG
TVVOUT
ENCB
ENCRC
ENCV
TVVIN
VCRFB
VCRG
ENCG
ENCC
ENCY
VCRVIN
VCRRC
Figure 1. AKD4702 Block Diagram l Circuit diagram and PCB layout are attached at the end of this manual.
-1-
TVOUTL
MONOOUT
2002/12
ASAHI KASEI
[AKD4702]
n Operation sequence
1) Set up the power supply lines. (Note 1) [+12V] [+5V] [D5V] [VVD1] [VVD2] [AGND] [DGND] [VVSS2] (Orange) (Red) (Red) (Red) (Blue) (Black) (Black) (Black) = +11.4 +12.6V = +4.75 +5.25V (Note 2) = +4.75 +5.25V (Note 3) = +4.75 VVD2 (Note 4) = VDD1 +5.25V (Note 4) = 0V = 0V = 0V
Note: 1. Each supply line should be distributed from the power supply unit. 2. JP9 (REG) should be open when the "+5V" jack is used. 3. JP8 (D-A) should be open when the "D5V" jack is used. 4. JP10 (VDD1) / JP11 (VDD2) should be open when the "VDD1" jack / "VDD2" jack are used respectively. 2) Set-up the evaluation modes, jumper pins and DIP-switches. (Refer following sections.) 3) Connect the PORT3 (=P-I/F) with PC by the enclosed 10-wire flat cable. 4) Set up the PC and execute the enclosed control software. (See "CONTROL SOFTWARE MANUAL".) 5) Turn the power on. 6) Reset the AK4702 once by bringing the SW1 (PDN) "L", and turn it to "H".
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ASAHI KASEI
[AKD4702]
n Evaluation mode 1) S/PDIF mode (Optical Link or BNC: default)
When the CM0 (DIP-switch S1_1 on board) is "L", the AK4112B (DIR) generates MCLK, BICK, LRCK and SDATA from the received bitstream through PORT2 (TORX176: optical link) or J2 (BNC). This mode is used for the evaluation using CD test disk. The PORT1 (EXT) should be open. 1)-1. DIP-switch set-up No. 1 2 3 4 CM0 "L" "L" "L" "L" DIF1 "L" "L" "H" "H" DIF0 "L" "H" "L" "H" Audio Data Format of AK4112B 16bit LSB justified 18bit LSB justified MSB justified I 2S Notes 1 2 3 4
Table 1. DIP-switch set-up Please match the data format of AK4702 via I C-bus control as following notes. Note 1. 16bit LSB justified Set up the DIP-switch as follows.
2
S1 AK4112B ON OFF
(Reserved) (Reserved) (Reserved) (Reserved)
12345
Set up the control registers DIF1/0 of AK4702 by enclosed software as follows.
Note 2. 18bit LSB justified Set up the DIP-switch as follows.
ON OFF
Set up the control registers DIF1/0 of AK4702 by enclosed software as follows.
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CM0 DIF2 DIF0
CM0 DIF2 DIF0
S1 AK4112B 12345
2002/12
ASAHI KASEI
[AKD4702]
Note 3. MSB justified Set up the DIP-switch as follows.
S1 AK4112B ON OFF
(Reserved) (Reserved) (Reserved) (Reserved)
12345
Set up the control registers DIF1/0 of AK4702 by enclosed software as follows.
Note 4. I2S Set up the DIP-switch as follows.
ON OFF
Set up the control registers DIF1/0 of AK4702 by enclosed software as follows.
-4-
CM0 DIF2 DIF0
CM0 DIF2 DIF0
S1 AK4112B 12345
2002/12
ASAHI KASEI
[AKD4702]
1)-2. Jumper pins set up
JP1 EXT
JP2 MCLK
JP3 BICK
JP4 SDTI
JP5 LRCK
The JP6 selects the input port of S/P DIF bitstream form Port2 (TOTX176) or J2 (BNC RX).
JP6
RX
JP6
RX
TORX
TORX
BNC Using TORX
BNC Using BNC
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ASAHI KASEI
[AKD4702]
2) On-board X'tal mode/ Feeding external MCLK via BNC
When the CM0 (DIP-switch S1_1 on board) is "H", the AK4112B generates MCLK, BICK and LRCK from on-board X'tal or external clock form J1. SDATA should be fed via PORT1. 2)-1. DIP-switch set-up No. 1 CM0 "H" DIF1 Don't care DIF0 Don't care
Table 2. DIP-switch set-up
2)-2. Jumper pins set up
2)-2-a. Using on-board X'tal
JP1 EXT JP2 MCLK JP3 BICK JP4 SDTI JP5 LRCK
JP6: Don't care. 2)-2-b. Using external clock via BNC connector J1 JP1 EXT JP2 MCLK JP3 BICK JP4 SDTI JP5 LRCK
JP6: Don't care. Remove the on-board X'tal.
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ASAHI KASEI
[AKD4702]
3) Feeding all clocks from external
Under the following set-up, all external signals can be fed to AK4702 through POTR1 (EXT). The AKM's evaluation board for ADC can be used. 3)-1. DIP-switch set-up No. 1 CM0 Don't care DIF1 Don't care DIF0 Don't care
Table 3. DIP-switch set-up 3)-2. Jumper pins set up JP1 EXT JP2 MCLK JP3 BICK JP4 SDTI JP5 LRCK
JP6: Don't care.
n Other jumper pins set up
[JP12](VCRRC): Input Jack selection for the VCRRC pin of AK4702 When the VCRC pin of AK4702 outputs 0V by setting CIO bit to "1", the signal can be fed through the J27 (VCRCOUT) to VCRRC pin. "I": The signal is fed through the J18(VCRRC) to VCRRC pin. (Default) "I/O": The signal is fed through the J27(VCRCOUT) to VCRRC pin. The CIO bit of AK4702 should be set to "1".
[JP7](GND): Analog ground and digital ground Open: separated. (Default) Short: connected. (The jack "DGND" can be open.) JP7
DGND AGND
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ASAHI KASEI
[AKD4702]
n DIP-switch (S1) List
No. 1 2 3 4 5 Switch Name CM0 DIF0 DIF2 Default OFF OFF OFF OFF OFF Function Refer the "n Evaluation mode"
(Reserved) (Reserved) Table 4. DIP-switch list
n Jumper List No. 1 2,3, 4,5 6 Jumper Name MCLK source set-up when CM0="H". EXT MCLK, BICK, LRCK, SDTI RX
Short: X'tal (default). Open: External clock via BNC (J1). Remove the on-board X'tal.
Function
Clock source set-up
Short: Connect the DIR (AK4112B). (default) Open: Separate the DIR. Supply clocks via Port1.
S/PDIF's port set-up when CM0="L".
TORX: Optical connector PORT2. (default) BNC: BNC connector J2.
Analog ground and digital ground 7 GND
Open: separated (default). Short: connected (The connector "DGND" can be open.).
Power supply source set-up for digital section of AKD4702. 8 D-A
Open: from the "D5V" Jack. (default) Short: from the regulator or the "+5V" Jack. Don't connect anything to the "D5V" Jack.(default)
Power supply source set-up for VD of AK4702. 9 REG
Open: from the "+5V" Jack. Short: from the regulator. Don't connect anything the "+5V" Jack. (default)
Power supply source set-up for VVD1 of AK4702. 10 VVD1
Open: from the "VVD1" Jack. Short: from the regulator or the "+5V" Jack. Don't connect anything to the "VVD1" Jack. (default)
Power supply source set-up for VVD1 of AK4702. 11 VVD2
Open: from the "VVD2" Jack. Short: from the regulator or the "+5V" Jack. Don't connect anything to the "VVD2" Jack. (default)
Input Selection for VCRRC 12 VCRRC
"I" side: Input to VCRRC from VCRRC jack. "I/O" side: Input to VCRC from VCRC jack. (Note: Refer CIO bit of AK4702)
Table 5. Jumper list
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ASAHI KASEI
[AKD4702]
n Serial Control
The AK4702 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3 (P-IF) with PC by 10 wire flat cable packed with the AKD4702. Be careful connector direction. Flat cable should be connected 10-pin header, red line put on 10pin header 5 and 6 pin.
1 10
Connect PC
SCL SDA SDA(ACK) AKD4702
RED 10 wire flat cable 5 10 pin Connector PORT3 6
P-IF
10 pin Header
Figure 2. Connection of 10 pin flat cable for PORT3
n Input/Output port List
Table 6. Input/Output port List Signal Name J5 (VCRINL), J3 (VCRINR), J9 (TVINL), J8 (TVINR) J11 (MONOIN) J12 (VCROUTL), J10 (VCROUTR), J6 (TVOUTL), J7 (TVOUTR), J4 (MONOOUT) Port2 (TORX176) or J2 BNC (RX) J13 (ENCB), J15 (ENCG), J17 (ENCRC), J19 (ENCC), J21 (ENCV), J23(ENCY), J25(TVVIN), J14(VCRVIN), J18(VCRRC; Note), J20(VCRG), J22(VCRB) J27 (VCRCOUT; Note), J29 (TVVOUT), J30 (TVRC), J31 (TVG), J32 (TVB), J33 (RFV), J34 (VCRVOUT) J24 (VCRSB) J24 (VCRSB) , J28 (TVSB) J16 (VCRFB) J26 (TVFB) Notes Max: 2Vrms Max: 1Vrm Max: 3Vrm Max: D5V+0.3V Max: 1.5Vp-p Max: 3Vp-p Max: VP+0.3V Max: VP Max: VVD1+0.3V Max: VVD2
Input Audio Output Digital Input Input Video Output Slow Blanking Fast Blanking Input Output Input Output
Note: Refer JP12 and CIO bit of AK4702.
n The indication content for LED
LED turns on during each output is "H". [LE1] (Unlock and Parity Error on S/P DIF): ERF of DIR (AK4112B). Normally off. [LE2] (Validity Flag): V of DIR (AK4112B). Normally off.
n Toggle switch (SW1 on board) operation
"H": AK4702 is Active. "L": AK4702 is Powered Down . (Note; When the power of AKD4702 is ON at first, SW1 should be switched from "L" to "H".)
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2002/12
ASAHI KASEI
[AKD4702]
MEASUREMENT RESULTS n Audio
[Measurement condition] * Measurement unit : Audio Precision System two Cascade * MCLK : 256fs * BICK : 64fs : 48kHz * fs : 10Hz20kHz * BW : 18bit * Bit * Power Supply : VD=5V, VDD1=5V, VDD2=5V, VP=12V * Interface : DIR * Temperature : Room * Volume#0=Volume#1=0dB * Measurement signal line path: DAC Volume#0 Volume#1 TVOUTL/R Parameter S/(N+D) at 2Vrms Output DR S/N Input signal 1kHz, 0dBFS 1kHz, -60dBFS "0" data Measurement filter 20kLPF 22kLPF, A-weighted 22kLPF, A-weighted Results [dB] 91.5 96.0 96.0
Plots
Figure 1-1. FFT (1kHz, 0dBFS input) at 2Vrms output Figure 1-2. FFT (1kHz, -60dBFS input) Figure 1-3. FFT (Noise floor) Figure 1-4. FFT (Out-of band noise) Figure 1-5. THD+N vs. Input Level (fin=1kHz) Figure 1-6. THD+N vs. fin (Input Level=0dBFS) Figure 1-7. Linearity (fin=1kHz) Figure 1-8. Frequency Response (Input Level=0dBFS) Figure 1-9. Crosstalk (Input Level=0dBFS)
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ASAHI KASEI
[AKD4702]
n Video
[Measurement condition] * Signal Generator : Sony Tectonics TG2000 * Measurement unit : Sony Tectonics VM700T : VD=5V, VDD1=5V, VDD2=5V, VP=12V * Power Supply : BNC * Interface : Room * Temperature * Measurement signal line path: ENCV TVVOUT, ENCRC TVRC Parameter S/N Measurement conditions Input = 0% flat field Filter = Uni-weighted, BW= 15kHz to 5MHz Input = 100%red(ENCRC), Measured at TVVOUT Input = Modulated Lamp Input = Modulated Lamp Results 75.8 Unit dB
Crosstalk DG DP
-52 -0.1 to +0.24 0 to +0.40
dB % deg.
Plots
Figure 2-1. Noise spectrum (Input=0%flat field, BW=15kHz to 5MHz, uni weighted) Figure 2-2. Frequency Response (Input= Multi Burst) Figure 2-3 Crosstalk (Input= 100% red (ENCRC), measured at TVVOUT) Figure 2-4 DG, DP (Input= Modulated Lamp)
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2002/12
ASAHI KASEI
[AKD4702]
Plots (Audio)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -90 -100 -110 -120 -130 -140 -150 20 -70 -80
AK4702 FFT (DAC->TVOUT: fs=48kHz, sigal = 1kHz/0dB)
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure1-1. FFT (fin=1kHz Input Level=0dBFS)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -90 -100 -110 -120 -130 -140 -150 20 -70 -80
AK4702 FFT (DAC->TVOUT: fs=48kHz, sigal = 1kHz/-60dB)
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure-1-2. FFT (fin=1kHz Input Level=-60dBFS)
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2002/12
ASAHI KASEI
[AKD4702]
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -90 -100 -110 -120 -130 -140 -150 20 -70 -80
AK4702 FFT (DAC->TVOUT: fs=48kHz, no sigal)
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure1-3. FFT (Noise Floor)
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -90 -100 -110 -120 -130 -140 -150 100 -70 -80
AK4702 FFT (DAC->TVOUT: fs=48kHz, no sigal, out of band)
200
500
1k
2k Hz
5k
10k
20k
50k
100k
Figure1-4. FFT (Outband Noise)
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2002/12
ASAHI KASEI
[AKD4702]
AKM
-80
AK4702 THD+N vs. Level (DAC->TVOUT: fs=48kHz, signal= 1kHz )
-82
-84
-86
-88 d B r A -92
-90
-94
-96
-98
-100 -110
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Figure1-5. THD+N vs. Input level (fin=1kHz)
AKM
-80
AK4702 THD+N vs. Input Frequency (DAC->TVOUT: fs=48kHz, signal= 0dB )
-82
-84
-86
-88 d B r A -92
-90
-94
-96
-98
-100 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure1-6. THD+N vs. Input Frequency (Input level=0dBFS)
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2002/12
ASAHI KASEI
[AKD4702]
AKM
+0
AK4702 Linearity (D A C ->TVOUT: fs=48kHz, signal= 1kHz )
-10
-20
-30
-40 d B r A -70
-50
-60
-80
-90
-100
-110 -110
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Figure1-7.Linearity (fin=1kHz)
AKM
+0.5
AK4702 Frequency response (DAC->TVOUT: fs=48kHz, signal= 0dB )
+0.4
+0.3
+0.2
+0.1 d B r A -0.1
+0
-0.2
-0.3
-0.4
-0.5 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k
Figure1-8. Frequency Response (Input level=0dBFS)
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ASAHI KASEI
[AKD4702]
AKM
-60 -65 -70
AK4702 Crosstalk (DAC->TVOUT: fs=48kHz, signal= 0dB )
-75 -80 -85 -90 -95 -100
d B r A
-105 -110 -115
-120 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure1-9. Crosstalk (Input level=0dBFS)
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ASAHI KASEI
[AKD4702]
Plots(Video)
Figure 2-1. Noise spectrum (Input=0%flat field, BW=15kHz to 5MHz, uni weighted)
Figure 2-2. Frequency Response (Input= Multi Burst)
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ASAHI KASEI
[AKD4702]
Figure 2-3 Crosstalk (Input= 100% red (ENCRC), measured at TVVOUT)
Figure 2-4 DG, DP (Input= Modulated Lamp)
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ASAHI KASEI
[AKD4702]
CONTROL SOFTWARE MANUAL n Introduction
This is a manual of software that controls the AK4702, 2ch DAC with AV SCART switch. The enclosed software AKD4702.exe can control the registers of AK4702 using I2C control I/F.
n System Requirements
To use this software, the followings are required for PC.: * Windows 95/98/ME/2000/XP. (This software does not operate on Windows NT.) * Printer port
n Set-up of evaluation board and control software
1. 2. Set up the AKD4702. Insert Connect IBM-AT compatible PC with AKD4702 by 10-line type flat cable (packed with AKD4702). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM disk when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) The CD-ROM disk labeled "AKD4702 Control Program ver 1.0" into the CD-ROM disk drive.
3.
n Operations
[1] Execute the AKD4702.exe. Then the following window opens. The function of each button is shown below. Clicking the button does each operation in the alone.
Write defalt to all resisters.
Read all resisters.
Close this window.
" "means "1". Write each byte.
Space means "0".
Read the address in this box.
Read 08H.
Write the DATA to the address in this box.
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ASAHI KASEI
[AKD4702]
[2] Write/Read Register There are two ways to Write/Read register. (1) Check box After checking each box of each bit, click the "Write" or "Read" button in the right end. " " in each check box means "1" and no check means "0". Each check mark toggles by clicking. The address 08H is Read-only. (2) Edit box There is an edit box in the left bottom. All register can be written and read using the edit box. When writing register, input the DATA and the Address in the box and click "Write" button. When reading register, input the Address in the box and click "Read" button.
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ASAHI KASEI
[AKD4702]
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
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ASAHI KASEI
[AKD4702]
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2002/12
5
4
3
2
1
R1 4112B_3.3V 5.1
C1 + C2
10u
C3
D
0.1u
CM0
MCLK BICK LRCK SDATA Logic
1 2 3 4 5
PORT1 10 9 8 7 6
R2 10k Logic
D
Logic
U2A 1 2
JP1
EXT 74HCU04 22p C5 J1 BNC R3 75
(OPEN) C6 2 X1
22p
1
(OPEN)
C
PDN R6 18k 4112B_3.3V
C7 + C8
B
Logic
L1
PORT2 6 5 6 5 GND VCC GND OUT 4 3 2 1 R-PACK5R 13
TORX176
R7 J2
A
470
C11 R8
BNC(RX)
75
0.1u
Size A Date:
5 4 3 2
+
10u
C4
0.1u
1 2 3 4 5 6 7 8 9 10 11 12 13 14
U1
EXT
12.288MHz
DVDD DVSS TVDD V/TX XTI XTO PDN R AVDD AVSS RX1 DIF0/RX2 DIF1/RX3 DIF2/RX4
CM0/CDTO CM1/CDTI OCKS1/CCLK OCKS0/CSN MCK01 MCK02 DAUX BICK SDTO LRCK ERF FS96 P/S AUTO
28 27 26 25 24 23 22 21 20 19 18 17 16 15
R82 10k R83 INTRUPT
JP2 MCLK
300
MCLK BICK SDTI LRCK Logic
JP3 JP4 JP5
BICK SDTI LRCK
U2B
R4 4
LE1
C
AK4112BVF
3
74HCU04
1k
R5 6
ERF
LE2
DIF0 DIF2 CM0 DIF0 DIF2
1 2 3 4 5
U2C S1
AK4112B
10 9 8 7 6 SW DIP-5
5
74HCU04
1k
V
Logic
U2D 9 8 74HCU04
10u
0.1u
RP1 5 4 3 2 1
CM0 DIF0 DIF2
U2E 11 10 74HCU04 U2F 12 74HCU04
B
47u
C9
C10 +
0.1u
10u
JP6 RX TORX
A
BNC Title Document Number
AKD4702
AK4112B
Sheet
Rev
A
1
1
of
6
5
4
3
2
1
JP7 GND SCL
Resister Contorol
VVD2
SDA Analog Ground PDN Digital Ground R10 R11 R12 R9
LRCK SDTI BICK MCLK
C12 DAC input
+C13
0.1u
10u
+5V
(VVSS) +C16
D
D
C17
100
100
100
100
0.1u
10u
C18
+C19
C22
+C23
0.1u
10u
0.1u
10u
48 47 46 45 44 43 42 41 40 39 38 37 (VVSS) (VVSS)
+12V
C20 +C21
VCRVOUT
MCLK
RFV
TVFB
LRCK
BICK
PDN
SCL
SDA
VD
1 2
C
SDTI
VSS
(VVSS2)
VCRC VVSS2 TVVOUT VVD2 TVRC TVG TVB VVD1 ENCB ENCG ENCRC
PVCOM DVCOM VP MONOOUT
36 35
0.1u
10u
C
3
34 33 32 31 30 29 28 27 26 25
(VVSS)
VVD1
4 5 6 7 8
U3
TVOUTL TVOUTR VCROUTL VCROUTR MONOIN TVINL TVINR INTRUPT VCRINR
AK 4702
MONOOUT TVOUTL TVOUTR VCROUTL VCROUTR
B
Analog output
C14
+C15
0.1u
10u
9 10
B
(VVSS2) Video Block output
VCRC TVVOUT TVRC TVG TVB RFV VCRVOUT TVFB TVSB VCRSB ENCB ENCG ENCRC ENCC ENCV ENCY TVVIN VCRVIN VCRFB VCRRC VCRG VCRB
5 4
11 12
MONOIN TVINL TVINR VCRINL VCRINR
Analog input
VCRVIN
VCRRC
VCRSB
VCRFB
ENCC TVVIN ENCV ENCY
VCRINL
VCRG
VCRB
13
14
15
16
17
18
19
20
21
22
23
TVSB
Video Block input/output
A
Video Block input
INTRUPT
24
A
Title Size A Date: Document Number
AKD4702
AK4702
Sheet
Rev
A
2
1
of
6
3
2
5
4
3
2
1
D
VCRINR R17 0.47u (open)
(VVSS)
MONOOUT 10k
R18
300
+
J3 VCRINR
C24
+
R15
C25
R16
J4
10u
300
MONOOUT
D
(VVSS) (VVSS)
(VVSS) J6
VCRINL R21 0.47u (open) J8 TVINR
(VVSS)
TVOUTL 10k
R22
300
+
J5 VCRINL
C26
+ (VVSS)
R19
C27
R20
10u
300
TVOUTL
(VVSS)
(VVSS) J7
From Analog output
TVINR R26 0.47u (open)
(VVSS) (VVSS)
TVOUTR 10k
R25
300
+
C
C29
+
R24
C28
R23
10u
300
TVOUTR
C
FOR Analog input
(VVSS) C31 R28
(VVSS) J10
TVINL R29 0.47u (open)
B
VCROUTL 10k
R30
300
+
J9 TVINL
C30
+ (VVSS)
R27
10u
300
VCROUTL
(VVSS)
(VVSS)
(VVSS) R32 J12
B
MONOIN R33 0.47u (open)
(VVSS) (VVSS)
VCROUTR 10k
R34
300
+
J11 MONOIN
C32
+
R31
C33
10u
300
VCROUTR
(VVSS)
(VVSS)
A
A
Title Size A Date:
5 4 3 2
Document Number
AKD4702
Sheet
Rev
Friday, April 11, 2003
Analog Input/Output Circuit
3
of
1
A
6
5
4
3
2
1
R35
R36
U4 2 3 4 5 6 7 8 9 1 19 A1 A2 A3 A4 A5 A6 A7 A8 G1 G2 74HCT541 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11
Logic 10k
R39
D
R37
100 SCL Logic
D1 R38
470
R40
10k
U5A 1 2 74HCT14 C34 SW1 3 U5B 4 74HCT14 PDN
D
PORT3 1 2 3 4 5 10 9 8 7 6
10k SCL SDA SDA(ACK)
R41
470
H
L
51 uP-I/F
PDN
0.1u
U5C 5 6 74HCT14 1
U6A 2 74LS07 U6B 4 74LS07 U6D 8 74LS07 U6E 10 74LS07 U6F 12 74LS07
R42 U6C 6 74LS07
U5D
3 8 9
10k
R43
Logic SDA
9
5
C
(short)
74HCT14 U5E 11 10 74HCT14 U5F 13 12 74HCT14
C
SDA(ACK)
11
13
D5V JP8 Logic D-A
B
+5V
L2
T1 NJM78M05FA
+12V R44
1 C35 + C36
JP9
GND 3 OUT IN
10u
+C39
REG
C37
+12V Short
B
+
C38
2
0.1u
0.1u
47u
47u R45 +5V Short VVD1 JP10 VDD1 VVD2
47u Logic
T2 LP2950A 4112B_3.3V C49 C46 GND 1 OUT IN 3 C47 + C48
C41 0.1u Logic 47u 0.1u
C42 0.1u
C43 0.1u
C44 0.1u
C45 + C40 0.1u 47u
VVD1
A
R14 5.1
2
0.1u
47u
+
for 74HCT14, 74HCU04, 74LS07, 74HCT541
A
Title
R13 VVD2 short
5
JP11 VDD2
4 3
Size A Date:
Document Number
AKD4702
Sheet
Rev
POWER SUPPLY
2
A
of
1
4
6
5
4
3
2
1
J13 ENCB
R70 (short)
R46 75
C50
J14 VCRVIN ENCB R47 75
(VVSS2) (VVSS2)
R77 (short)
C51 VCRVIN 0.1u
D
0.1u
D
(VVSS2)
J15 ENCG
(VVSS2)
R71 R48 75 (short)
C52
J16 VCRFB ENCG R49 75
(VVSS2) (VVSS2)
R78 VCRFB 300
0.1u
(VVSS2)
(VVSS2) R72
J17 ENCRC R50 75
C
C53 ENCRC 0.1u
J18 VCRRC R51 75
(VVSS2) (VVSS2)
JP12 I
R79 (short)
C54 VCRRC 0.1u VCRCOUT
C
(short)
I/O VCRRC
(VVSS2)
(VVSS2)
J19 ENCC R52 75
(VVSS2) (VVSS2)
R73 (short)
C55 ENCC 0.1u
J20 VCRG R53 75
(VVSS2) (VVSS2)
R80 (short)
C56 VCRG 0.1u
J21 ENCV
B
R74 R54 75 (short)
C57 ENCV 0.1u
J22 VCRB R55 75
(VVSS2) (VVSS2)
R81 (short)
C58 VCRB 0.1u
B
(VVSS2)
(VVSS2)
J23 ENCY R57 75
(VVSS2) (VVSS2)
R75 (short)
C59 ENCY 0.1u
J24 VCRSB R58 10K
(VVSS) (VVSS)
R56 VCRSB 300
A
J25 TVVIN R59 75
(VVSS2)
5
R76 (short)
C60 TVVIN 0.1u
Size A Date:
4 3 2
A
Title Document Number
AKD4702
Sheet
Rev
(VVSS2)
Video Block Input Circuit
A
5
1
of
6
5
4
3
2
1
R61
J27
75 VCRC
VCRCOUT RFV
R67
J33
300
RFV
D
VCRCOUT
R63 J29
D
(VVSS2)
(VVSS2)
75 TVVOUT
TVVOUT
R60 J26
75 TVFB
(VVSS2) R64 J30
TVFB
75 TVRC
TVRC
R62 J28
(VVSS2)
300 TVSB
TVSB
C
C
(VVSS2) R65 J31
75 TVG
TVG
(VVSS2)
(VVSS2) R66 J32
75 TVB
B
TVB
B
(VVSS2) R68 J34
75 VCRVOUT
VCRVOUT
(VVSS2)
A
A
Title Size A Date:
5 4 3 2
Document Number
AKD4702
Sheet
Rev
Video Block Output Circuit
6
of
1
A
6

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