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AT9933 Hysteretic Boost-Buck (uk) LED Driver IC
Features
Constant current LED Driver Steps input voltage Up or Down Low EMI Variable frequency operation Internal 8 to 100V linear regulator Input and output current sensing Input current limit Enable & PWM dimming Ambient temperature rating up to 125C Meets AEC-Q100 requirements
General Description
The AT9933 is a variable frequency PWM controller IC, designed to control an LED lamp driver using a low-noise boost-buck (uk) topology. The AT9933 uses patent-pending hysteretic current-mode control to regulate both the input and the output currents. This enables superior input surge immunity without the necessity for complex loop compensation. Input current control enables current limiting during startup, input under-voltage and output overload conditions. The AT9933 provides a low-frequency PWM dimming input that can accept an external control signal with a duty cycle of 0 - 100% and a high dimming ratio. The AT9933 based LED driver is ideal for automotive LED lamps. The part is rated for up to 125C ambient temperatures and is AEC-Q100-Compliant.
Applications
Automotive LED Lighting
Reference Documents
AEC-Q100 Rev. F, 7/18/2003 SAE J1752-3
Typical Application Circuit
D2 (optional) L1 RD VDC Q1 RCS1 RCS2 RS1 C2 VIN GATE CS1 GND VDD PWMD CS2 REF C3 RS2 CD D1 + C1 L2 -
D3
VO
RREF1
RREF2
AT9933
AT9933 Ordering Information
DEVICE AT9933 Package Option 8-Lead SOIC AT9933LG-G
CS1
2 7
Pin Configuration
VIN
1 8
REF
CS2
-G indicates package is RoHS compliant (`Green')
GND
3
6
VDD
Absolute Maximum Ratings
Parameter VIN to GND CS1, CS2 PWMD to GND GATE to GND VDDMAX Continuous Power Dissipation (TA = +25C) 8-Pin SOIC Junction to ambient thermal impedance (typical); using standard footprint Junction temperature Storage temperature range 700mW 128OC/W +150C -65C to +150C Value -0.5V to +100V -0.3V to (VDD + 0.3V) -0.3V to (VDD + 0.3V) -0.3V to (VDD + 0.3V) 12V
GATE
4
(top view)
5
PWMD
8-Lead SOIC
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Characteristics
(The * denotes the specifications which apply over the full operating ambient temperature range of -40C < TA < +125C, otherwise the specifications are at TA = 25C. VIN = 12V, unless otherwise noted)
Symbol Input VINDC IINSD
Parameter
Min
Typ
Max
Units
Conditions
Input DC supply voltage range1 Shut-down mode supply current1
* -
(2)
0.5
100 1.0
V mA
DC input voltage PWMD connected to GND, VIN = 12V VIN = 8 - 100V, IDD(ext) = 0, 500pF capacitor at GATE, PWMD = GND VIN rising ---
-
Internal Regulator VDD UVLO UVLO Internally regulated voltage VDD undervoltage lockout threshold VDD undervoltage lockout hysteresis * * 7.0 6.45 7.5 6.70 500 9.0 6.95 V V mV
2
AT9933
Symbol Reference REF pin voltage -40C < TA < +85C REF pin voltage -40C < TA < +125C Line regulation of reference voltage 1.212 1.187 1.25 1.25 1.288 V 1.312 REF bypassed with a 0.1F capacitor to GND, IREF= 0, PWMD = 5.0V REF bypassed with a 0.1F capacitor to GND, IREF = 0, VDD = 7.0 - 9.0V, PWMD = 5.0V REF bypassed with a 0.1F capacitor to GND, IREF = 0; VDD = 7.0 - 9.0V, PWMD = 5.0V REF bypassed with a 0.1F capacitor to GND, IREF = 0 - 500A, PWMD = 5.0V VDD = 7.0V - 9.0V VDD = 7.0V - 9.0V VPWMD = 5.0V --VGATE = 0V VGATE = VDD CGATE = 500pF CGATE = 500pF CS2 = 200mV; CS1 increasing; GATE goes LOW to HIGH CS2 = 200mV; CS1 decreasing; GATE goes HIGH to LOW CS2 = 200mV; CS1 = 50mV to +200mV step CS2 = 200mV; CS1 = 50mV to -100mV step Description Min Typ Max Units Conditions
VREF
VREFLINE
-
0
-
20
mV
IREF
Reference output current range
-
-0.01
500
A
VREFLOAD
Load regulation of reference voltage
-
0
-
10
mV
PWM Dimming PWMD input low voltage VPWMD(hi) RPWMD IPWMD GATE ISOURCE ISINK TRISE TFALL GATE short circuit current GATE sinking current GATE output rise time GATE output fall time 0.165 0.165 30 30
-
* * -
2.0 50 -
100 -
0.8 150 5
V V k mA A A ns ns
PWMD input high voltage PWMD pull-down resistance Maximum current into PWMD pin
50 50
Input Current Sense Comparator VTURNON1 VTURNOFF1 TD1,ON TD1,OFF Voltage required to turn GATE on Voltage required to turn GATE off Delay to output (turn on) Delay to output (turn off) * * 85 -15 100 0 150 150 115 15 250 250 mV mV ns ns
Output Current Sense Comparator VTURNON2 VTURNOFF2 TD2,ON TD2,OFF Voltage required to turn GATE on Voltage required to turn GATE off Delay to output (turn on) Delay to output (turn off) * * 85 -15 100 0 150 150 115 15 250 250 mV mV ns ns CS1 = 200mV; CS2 increasing; GATE goes LOW to HIGH CS1 = 200mV; CS2 decreasing; GATE goes HIGH to LOW CS1 = 200mV; CS2 = 50mV to +200mV step CS1 = 200mV; CS2 = 50mV to -100mV step
1 Also limited by package power dissipation limit, whichever is lower. 2 Depends on the current drawn by the part - see application section. 3
AT9933 Pin Description
Pin Number 1 2 7 3 4 5 6 8 Pin VIN CS1 CS2 GND GATE PWMD VDD REF Description This pin is the input of a 8 - 100V voltage regulator. These pins are used to sense the input and output currents of the boost-buck converter. They are the non-inverting inputs of the internal comparators. Ground return for all the internal circuitry. This pin must be electrically connected to the ground of the power train. This pin is the output gate driver for an external N-channel power MOSFET. When this pin is left open or pulled to GND, the gate driver is disabled. Pulling the pin to a voltage greater than 2V will enable the gate drive output. This is a power supply pin for all internal circuits. It must be bypassed to GND with a low ESR capacitor greater than 0.1F. This pin provides accurate reference voltage. It must be bypassed with a 0.01 - 0.1F capacitor to GND.
Block Diagram
VIN
Regulator
Input Comparator
7.5V
VDD
CS1
100mV
GATE
0mV
CS2
Output Comparator
1.25V
REF
PWMD GND
AT9933
4
AT9933 Functional Description
Power Topology
The AT9933 is optimized to drive a continuous conduction mode (CCM) boost-buck DC/DC converter topology commonly referred to as "uk converter" (see Circuit Diagram on page 1). This power converter topology offers numerous advantages useful for driving high-brightness light emitting diodes (HB LED). These advantages include step-up or step-down voltage conversion ratio and low input and output current ripple. The output load is decoupled from the input voltage with a capacitor making the driver inherently failuresafe for the output load. The AT9933 offers a simple and effective control technique for use with a boost-buck LED driver. It uses two hysteretic mode controllers - one for the input and one for the output. The outputs of these two hysteretic comparators are ANDED and used to drive the external FET. This control scheme gives accurate current control and constant output current in the presence of input voltage transients without the need for complicated loop design. voltages at the VIN pin can be determined using the maximum voltage drop across the linear regulator as a function of the current drawn. This data is shown in Fig. 1 for ambient temperatures of 25C and 125C.
Voltage Drop vs. IIN
3.5 3
Voltage Drop (V)
2.5 2 1.5 1 0.5 0 0 1 2 3 4 5 6 7
125OC 25OC
IIN (mA)
Fig. 1. Maximum Voltage Drop vs. Input Current Assume an ambient temperature of 125C. Assuming the IC is driving a 15nC gate charge FET at 300kHz, the total input current is estimated to be 5.5mA (using Eqn. 1). At this input current, the maximum voltage drop from Fig. 1 can be approximately estimated to be VDROP = 2.7V. However, before the IC starts switching the current drawn will be 1mA. At this current level, the voltage drop is approximately VDROP1 = 0.5V. Thus, the start/stop VIN voltages can be computed to be: VINSTART = UVLOMAX + VDROP1 = 6.95V + 0.5V = 7.45V VINSTOP = UVLOMAX - UVLO + VDROP = 6.95 - 0.5V + 2.7V = 9.15V Note that in this case, since the gate drive draws too much current, VINSTART is less than VINSTOP. In such cases, the control IC will oscillate between ON and OFF if the input voltage is between the start and stop voltages. In these circumstances, it is recommended that the input voltage be kept higher than VINSTOP (in this case the IC will operate normally if the input voltage is kept higher than 9.2V). In case of input transients that reduce the input voltage below 8V (like cold crank condition in an automotive system), the VIN pin of the AT9933 can be connected to the drain of the MOSFET through a switching diode with a small (1nF) capacitor between VIN and GND (as long as the drain voltage does not exceed 100V). Since the drain of the FET is at a voltage equal to the sum of the input and output voltages, the IC will still be operational when the input goes below 8V. In these cases, a larger capacitor is needed to the VDD pin to supply power to the IC when the MOSFET is ON.
Input Voltage Regulator
The AT9933 can be powered directly from its VIN pin that takes a voltage from 8V to 100V. When a voltage is applied at the VIN pin, the AT9933 seeks to regulate a constant 7.5V (typ) at the VDD pin. The regulator also has a built in undervoltage lockout which shuts off the IC if the voltage at the VDD pin falls below the UVLO threshold. The VDD pin must be bypassed by a low ESR capacitor (0.1F) to provide a low impedance path for the high frequency current of the output gate driver. The input current drawn from the VIN pin is a sum of the 1mA current drawn by the internal circuit and the current drawn by the gate driver (which in turn depends on the switching frequency and the gate charge of the external FET). IIN = 1mA + QG*fS (1)
In the above equation, fS is the switching frequency and QG is the gate charge of the external FET (which can be obtained from the datasheet of the FET).
Minimum Input Voltage at VIN pin
The minimum input voltage at which the converter will start and stop depends on the minimum voltage drop required for the linear regulator. The internal linear regulator will regulate the voltage at the VDD pin when VIN is between 8 and 100V. However, when VIN is less than 8V, the converter will still function as long as VDD is greater than the under voltage lockout. Thus, under certain conditions, the converter will be able to start at VIN voltages of less than 8V. The start/stop
5
AT9933
In this case VDD UVLO cannot be relied upon to turn off the IC at low input voltages when input current levels can get too large. The input current limit must then be designed to limit the input current to safe levels during input undervoltage conditions. PWM Dimming frequency range is from 100Hz to a few kilo hertz. The flying capacitor in the uk converter (C1) is initially charged to the input Voltage VDC (through diodes D1 and D2). When the circuit is turned on and reaches steady state, the voltage across C1 will be VDC+VO. In the absence of diode D2, when the circuit is turned off, capacitor C1 will discharge through the LEDs and the input voltage source VDC. Thus, during PWM dimming, if capacitor C1 has to be charged and discharged each cycle, the transient response of the circuit will be limited. By adding diode D2, the voltage across capacitor C1 is held at VDC+VO even when the circuit is turned off enabling the circuit to return quickly to its steady state (and bypassing the start-up stage) upon being enabled.
Reference
An internally trimmed voltage reference of 1.25V is provided at the REF pin. The reference can supply a maximum output current of 500A to drive external resistor dividers. This reference can be used to set the current thresholds of the two comparators as shown in the Typical Application Circuit.
Current Comparators
The AT9933 features two identical comparators with a builtin 100mV hysteresis. When the GATE is low, the inverting terminal is connected to 100mV and when the GATE is high, it is connected to GND. One comparator is used for the input current control and the other for the output current control. The input side hysteretic controller is in operation during start-up, overload and input undervoltage conditions. This ensures that the input current never exceeds the designed value. During normal operation, the input current will be less than the programmed current and hence, the output of the input side comparator will be HIGH. The output of the AND gate will then be dictated by the output current controller. The output side hysteretic comparator will be in operation during the steady state operation of the circuit. This comparator turns the MOSFET on and off based on the LED current.
Application Information
Over-voltage Protection
Over-voltage protection can be added by splitting the output side resistor RS2 into two components and adding a zener diode D3 (see the Design Example Circuit on the following page). When there is an open LED condition, the diode D3 will clamp the output voltage and the zener diode current will be regulated by the sum of RS2A and RCS2.
Damping Circuit
The uk converter is inherently unstable when the output current is being controlled. An uncontrolled input current will lead to an un-damped oscillation between L1 and C1 causing excessively high voltages across C1. To prevent these oscillations, a damping circuit consisting of RD and CD is applied across the capacitor C1. This damping circuit will stabilize the circuit and help in the proper operation of the AT9933 based uk converter.
PWM Dimming
PWM Dimming can be achieved by applying a TTL-compatible square wave signal at the PWM pin. When the PWMD pin is pulled high, the gate driver is enabled and the circuit operates normally. When the PWMD pin is left open or connected to GND, the gate driver is disabled and the external MOSFET turns off. The IC is designed so that the signal at the PWMD pin inhibits the driver only and the IC need not go through the entire start-up cycle each time ensuring a quick response time for the output current. The recommended
Design and Operation of the Boost-Buck Converter
For details on the design for a Boost-Buck converter using the AT9933 and the calculation of the damping components, please refer to Application Note AN-H51.
6
AT9933 Design Example Circuit
D2 (optional) L1 RD VDC Q1 CD D1 RCS2 RCS1 RS2A C2 RS1 VIN GATE CS1 RREF1 GND VDD PWMD CS2 RREF2 REF C3 RS2B D3 C1 L2 -
CO
VO
+
AT9933
Design Example
The choice of the resistor dividers to set the input and output current levels is illustrated by means of the design example given below. The parameters of the power circuit are: VIN MIN = 9V VIN MAX = 16V VO = 28V IO = 0.35A fS MIN = 300kHz Using these parameters, the values of the power stage inductors and capacitor can be computed as (see Application Note AN-H51 for details): L1 = 82H L2 = 150H C1 = 0.22F The input and output currents for this design are: IIN MAX = 1.6A IIN = 0.21A IO = 350mA IO = 87.5mA
Current Limits
The current sense resistor (RCS2), combined with the other resistors (RS2 & RREF2), determines the output current limits. The current sense resistor (RCS1), combined with the other resistors (RS1 & RREF1), determines the input current limits. The resistors can be chosen using the following equations: RS RREF RS RREF (2) + 0.05V (3) + 0.1V
I X RCS = 1.2V X
I X RCS = 0.1V X
Where I is the current (either IO or IIN) and I is the peak-topeak ripple in the current (either IO or IIN). For the input side, the current level used in the equations should be larger than the maximum input current so that it does not interfere with the normal operation of the circuit. The peak input current can be computed as: I in 2 (4)
IIN,PK = IIN,MAX + = 1.706A
7
AT9933
Assuming a 30% peak-to-peak ripple when the converter is in input current limit mode, the minimum value of the input current will be: ILIM,MIN = 0.85 * IIN,LIM Setting ILIM,MIN = 1.05 * IIN,PK (6) (5) RCS2 + RS2A = 120 Choose the following values for the resistors: RCS2 = 1.65, 1/4W, 1% RREF2 = 10k, 1/8W, 1% RS2A = 100, 1/8W, 1% RS2B = 5.23k, 1/8W, 1% The current sense resistor needs to be at least a 1/4W, 1% resistor. Similarly, using IIN = 2.1A and IIN = 0.3xIIN = 0.63 in (1) and (2): RS1 = 0.442 RREF1 RCS1 = 0.228 PRCS1 = I2IN,LIM * RCS1 = 1W Choose the following values for the resistors: RCS1 = parallel combination of three 0.68, 1/2W, 5% RREF1 = 10k, 1/8W, 1% RS1 = 4.42k, 1/8W, 1% (8)
The current level to limit the converter can then be computed. IIN LIM = 1.05 * IIN PK 0.85 (7)
= 2.1A Using IO = 350mA and IO = 87.5mA in (1) and (2), RCS2 = 1.78 RS2 = 0.5625 RREF2 Before the design of the output side is complete, over voltage protection has to be included in the design. For this application, choose a 33V zener diode. This is the voltage at which the output will clamp in case of an open LED condition. For a 350mW diode, the maximum current rating at 33V works out to about 10mA. Using a 2.5mA current level during open LED conditions, and assuming the same RS2/RREF2 ratio,
8
AT9933 8-Lead SOIC (Narrow Body) Package Outline (LG)
4.90 0.10 8 6.00 0.20 3.90 0.10 Note 2
1
Top View
0.17 - 0.25 1.75 MAX 1.25 MIN
5 - 15 (4 PLCS) 45
0.25 - 0.50 Note 2
0 - 8 0.10 - 0.25 1.27BSC 0.40 - 1.27
0.31 - 0.51
Side View
Notes: 1. All dimensions in millimeters. Angles in degrees. 2. If the corner is not chamfered, then a Pin 1 identifier must be located within the area indicated.
End View
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-AT9933 NR112806
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