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| Multimedia ICs SYNC separator IC with AFC BA7046 / BA7046F The BA7046 and BA7046F separate the synchronization signals from a video signal and output the horizontal and vertical synchronization signals (HD and VD), and the composite synchronization signal (Sync-out). The HD and VD pulse phase difference is guaranteed. *Applications TVs and VCRs *FeaturesAFC circuit. 1) Built-in 2) HD and VD phase difference guaranteed. 3) Low power dissipation. (approx. 21mW) 4) Low external parts count. 5) 8-pin DIP / SOP package. 6) Horizontal free-run frequency does not require adjustment. *Absolute maximum ratings (Ta = 25C) BA7046 (DIP) Parameter Power supply voltage Power dissipation Operating temperature Storage temperature Symbol VCC Max. Pd Topr Tstg Limits 8.0 500 - 20 ~ + 75 - 55 ~ + 125 Unit V mV C C Reduced by 5mW for each increase in Ta of 1C over 25C. BA7046F (SOP) Parameter Power supply voltage Power dissipation Operating temperature Storage temperature over 25C. Symbol VCC Max. Pd Topr Tstg Limits 8.0 350 - 20 ~ + 75 - 55 ~ + 125 Unit V mW C C When mounted on a 50mm x 50mm PCB board, reduced by 3.5mW for each increase in Ta of 1C *Recommended operating conditions (Ta = 25C) Parameter Operating power supply voltage Symbol VCC Min. 4.5 Typ. -- Max. 5.5 Unit V 1 Multimedia ICs BA7046 / BA7046F *Block diagrams 1 H. OSC PHASE COMP 8 2 7 3 SYNC SEPA 6 4 V. SEPA 5 *Pin descriptions Pin No. 1 2 3 4 5 6 7 8 Function Horizontal oscillator resistor HD output SYNC output (open collector) VD output GND Video input Power supply Phase comparator output *Input / output circuits VCC VCC 12k 200 1k 1pin 100A 5k 2pin 200 3pin Fig. 1 Fig. 2 VCC Fig. 3 VCC 3k 3k 3k VCC 10k 200 1k 4pin 100 10A 3k 3k 3k 6pin 8pin Fig. 4 Fig. 5 Fig. 6 2 Multimedia ICs BA7046 / BA7046F *Electrical characteristics (unless otherwise noted Ta = 25C and VCC = 5.0V) Parameter Quiescent current Minimum synchronization separation level Pulse voltage, LOW Pulse voltage, HIGH (Horizontal) free-running frequency Capture range Lock-in phase difference HD, VD phase difference HD pulse width VD pulse width Not designed for radiation resistance. Symbol Min. IQ Vsyn-Min. VP-L VP-H fH-O 2.0 -- -- 4.7 13.9 Typ. 4.1 0.08 0.1 4.9 15.7 2.9 0 23.5 5.1 230 Max. 6.2 0.15 0.3 -- 17.5 -- + 1.0 30.0 5.6 270 Unit mA VP-P V V kHz kHz s s s s pin2 pin4 pin2 pin4 pin- 6 pin- 2 pin 3 open Conditions pin 6 terminated with 75 resistor pins 2, 4 pins 2, 4 No input signal, I1 = open fCAP 2.1 THPH - 1.0 THVD THD TVD 17.0 4.6 190 *Measurement circuit 1 2200p 0.022 47 Video In + 39k VCC 8 A 7 + 75 1 6 + 5 470k 1 2 3 4 II 100p 130k V T 10k V VCC T V T Fig. 7 *Circuit operation separation circuit (1) Synchronization Detects the charging current to a externally-connected capacitor, and performs synchronization separation. (2) Horizontal oscillation circuit When a video signal is input, it is synchronized with Hsync by the PLL. The horizontal free-running frequency is determined by external resistor R1. 2.05E6 [kHz] fH-O = R1 (3) Vertical synchronization separation circuit When a video signal is input, synchronization signal separation is done over the vertical synchronization pulse interval. 3 Multimedia ICs BA7046 / BA7046F *VIN, HD and VD timing charts Vertical synchronization pulse interval NTSC signal Odd field (IN) 1 / 2H NTSC signal Even field (IN) VD (OUT) HD, VD phase difference HD Odd field (OUT) HD Even field (OUT) Fig. 8 (1) The rise and fall positions for VD are basically the same for both odd and even fields. (2) HD shifts by 1 / 2H during the odd and even field interval. (3) Only the odd field is given for the specification. 4 Multimedia ICs BA7046 / BA7046F *Application example R2 470k C4 100p R1 130k VCC = 5V PHASE COMP 1 H. OSC 8 R3 10k C2 2200p VCC = 5V + C3 1 + C5 47 C6 0.022 10k HD 2 7 C1 SYNC SEPA V. SEPA R4 330 C7 Vsig SYNC 3 6 R5 + 470k 1 1000p VD 4 5 By configuring the circuit enclosed in the dotted line to that in the diagram on the right, you can decrease the lock-in time and increase the capture range. VCC R2 470k R3 10k 8 C2 2200p C3-1 0.47 C3-2 0.47 Fig.9 * When SYNC SEPA output only is used. HD and VD unused. VCC = 5V R1 120k 1 H. OSC PHASE COMP 8 VCC = 5V + C5 47 C6 0.022 10k HD 2 7 C1 SYNC SEPA V. SEPA R4 330 C7 Vsig SYNC 3 6 R5 + 470k 1 1000p VD 4 5 Fig. 10 (1) Connect pin 1 to GND via a 120k (approx.) resistor. Leave pins 2, 4 and 8 open. (2) SYNC output polarity (pin 3) is positive. (3) The delay time for rising edge of the SYNC output (pin 3) with respect to the falling edge of Sync for the Vsig input signal (pin 6) is 850ns (reference value). (4) The delay time for falling edge of the SYNC output (pin 3) with respect to the rising edge of Sync for the Vsig input signal (pin 6) is 450ns (reference value). *Attached components a tolerance of 2%, and a temperature coefficient of 100ppm or lower. Resistor R1 should have 5 Multimedia ICs BA7046 / BA7046F *Electrical characteristic curves 6 5 CURRENT : ICC (mA) 4 CURRENT : ICC (mA) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 0 4.0 5.0 6.0 - 25 0 25 50 75 100 4.5 5.0 5.5 HORIZONTAL FREQUENCY : f (kHz) VCC = 5.0V 16.4 16.2 16.0 15.8 15.6 15.4 15.2 3 2 1 POWER SUPPLY VOLTAGE (V) TEMPERATURE (C) POWER SUPPLY VOLTAGE (V) Fig. 11 Quiescent current vs. power supply voltage Fig. 12 Quiescent current vs. temperature Fig. 13 Horizontal free-running frequency vs. power supply voltage 16.6 HORIZONTAL FREQUENCY : f (kHz) VCC = 5.0V 16.4 16.2 16.0 15.8 15.6 15.4 15.2 - 25 0 25 50 75 100 HD PULSE WIDTH : HD (s) 5.8 5.6 5.4 5.2 5.0 4.8 4.6 4.4 - 25 0 25 50 NTSC VCC = 5.0V VD PULSE WIDTH : VD (s) 250 240 230 220 210 200 190 180 NTSC VCC = 5.0V 75 100 - 25 0 25 50 75 100 TEMPERATURE (C) TEMPERATURE (C) TEMPERATURE (C) Fig. 14 Horizontal free-running frequency vs. temperature Fig. 15 HD pulse width vs. temperature Fig. 16 VD pulse width vs. temperature 70 60 NTSC VCC = 5.0V FREQUENCY : f (csp. lock) (kHz) 20 + lock (kHz) VCC = 5.0V + lock 20 + cap HD * VD PULSE TIMING (s) + cap 40 30 20 10 0 15 - cap - lock 10 FREQUENCY : f (csp.lock) 50 15 - cap - lock 10 - 25 0 25 50 75 100 4.5 5.0 5.5 - 25 0 25 50 75 100 TEMPERATURE (C) POWER SUPPLY VOLTAGE (V) TEMPERATURE (C) Fig. 17 HD, VD phase difference vs. temperature Fig. 18 Capture range / lock range vs. power supply voltage Fig. 19 Capture range charging / lock range vs. temperature 6 Multimedia ICs BA7046 / BA7046F 300 VCC = 5.0V fLOCK = 15.734kHz SIGNAL - LOCK IN TIME (ms) POWER LOCK IN TIME (ms) 700 600 500 400 300 200 100 VCC = 5.0V fLOCK = 15.734kHz 200 100 0 13 14 15 16 17 18 19 20 FREQUENCY (kHz) 0 13 14 15 16 17 18 19 20 FREQUENCY (kHz) Fig. 20 Time from no signal to pull in Fig. 21 Time from power on to pull in notes *Operation ground line as thick as possible. * Make the * Keep power supply noise to a minimum. *External dimensions (Units: mm) BA7046 BA7046F 9.3 0.3 6.5 0.3 8 5 5.0 0.2 8 6.2 0.3 4.4 0.2 5 0.51Min. 3.2 0.2 3.4 0.3 1.5 0.1 7.62 1 4 0.11 0.3 0.1 1.27 0.4 0.1 0.3Min. 0.15 2.54 0.5 0.1 0 ~ 15 DIP8 SOP8 0.15 0.1 1 4 7 |
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