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BH2222FV
Standard ICs
8bit 20ch D/A converter
BH2222FV
BH2222FV is an 8bit D/A converter for electronic adjustment. The 20-channel output voltage can be independently controlled by three-wire serial interface from micro-controller. The built-in power on reset circuit keeps the output state Low after the power is on. 4-channel have data register function. Two kinds of set voltage can be retained, and output voltage can be switched by SEL pin.
!Applications The voltage adjustment for DVC, DSC etc.
!Features 1) 8bit 20-channel D/A converters adopting R-2R system. 2) 3-wire + 1-wire 16-bit serial interface. 3) POWER ON RESET circuit. 4) The full scale output voltage range : 2.7 ~ 5.5V. 5) It is possible to set the two output full scale level independently. 6) 4-channel date Register extension function. 7) SSOP-B28 package.
!Absolute maximum ratings (Ta=25C)
Parameter Power supply voltage Maximum output voltage Storage temperature Power dissipation Symbol VCC VIN Tstg Pd Limits -0.3~+7.0 -0.3~VCC -55~+125 640 Unit V V C mW
Reduced by 6.4mW for each increase in Ta of 1C over 25C. This product is not designed for protection against radioactive rays.
!Recommended operating conditions (Ta=25C)
Parameter VCC supply voltage VDD1 supply voltage VDD2 supply voltage Analog output source current Analog output sink current Operating temperature range Clock frequency Limit load capacitance
Please set to VCC VDD1, VDD2.
Symbol VCC VDD1 VDD2 IOL IOH Topr FSCLK CL
Min. 4.5 2.7 2.7 - - -20 - -
Typ. - - - - - - 1.0 -
Max. 5.5 VCC VCC 1.0 1.0 85 - 0.47
Unit V V V mA mA C MHz F
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BH2222FV
Standard ICs
!Block diagram
VCC
1
VCC
POWER_ON RESET VDD2
VDD2
Serial interface
28 CLK 27 DI
R-2R DAC
EX1
3 4 5 6 7 8 9
VCC
R-2R DAC
EXD 8bitREG + DEC EXD 8bitREG + DEC 8bitREG + DEC 8bitREG + DEC 8bitREG + DEC 8bitREG + DEC 8bitREG + DEC 8bitREG + DEC 8bitREG + DEC 8bitREG + DEC
EXD 8bitREG + DEC EXD 8bitREG + DEC 8bitREG + DEC 8bitREG + DEC 8bitREG + DEC 8bitREG + DEC 8bitREG + DEC 8bitREG + DEC 8bitREG + DEC 8bitREG + DEC
VDD2
VDD2
2
26 EX4 25 EX3 24 AO16 23 AO15 22 AO14 21 AO13 20 AO12
VCC
EX2
R-2R DAC
R-2R DAC
AO1
R-2R DAC
R-2R DAC
AO2
R-2R DAC R-2R DAC
R-2R DAC R-2R DAC
AO3
AO4
VDD1
AO5
VCC
VCC
R-2R DAC
VDD1
R-2R DAC
R-2R DAC R-2R DAC
AO6
10 11 12 13 14
R-2R DAC R-2R DAC R-2R DAC VDD1
R-2R DAC R-2R DAC R-2R DAC
19 AO11 18 AO10 17 AO9 16 SEL 15 LD
AO7
AO8
VDD1
GND
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BH2222FV
Standard ICs
!Pin descriptions
Pin No. Pin name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VCC VDD2 EX1 EX2 AO1 AO2 AO3 AO4 AO5 AO6 AO7 AO8 VDD1 GND LD SEL AO9 AO10 AO11 AO12 AO13 AO14 AO15 AO16 EX3 EX4 DI CLK In / Out - - OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT - - IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN IN Power supply - - VDD2 VDD2 VDD2 VDD2 VDD2 VDD1 VDD1 VDD1 VDD1 VDD1 - - - - VDD1 VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 VDD2 - - Serial Data input pin Serial Clock input pin Analog output pins (Register extension) Analog output pins Power supply pin Common GND pin Serial Load input pin Select extended data register pin Analog output pins Power supply pin Power supply pin Analog output pins (Register extension) Functions
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BH2222FV
Standard ICs
!Electrical characteristics (unless otherwise noted, Ta=25C, VCC=VDD2=5.0V, VDD1=3.0V, RL=OPEN, CL=0pF)
Parameter (80H set) VCC system VDD1 system VDD2 system Input low voltage Input high voltage Input low current Input high current ZS1 Minimum output voltage ZS2 ZS3 FS1 Maximum output voltage FS2 FS3 Resolution Differential nonlinearity error Nonlinearity error RES DNL INL - -1.0 -1.5 8 - - - 1.0 1.5 bit LSB LSB Input code 02H~FDH Input code 02H~FDH GND GND GND VCC -0.1 VCC -0.2 VCC -0.3 - - - - - - 0.1 0.2 0.3 VCC VCC VCC V V V V V V 00H set IOH=0.0mA 00H set IOH=0.5mA 00H set IOH=1.0mA FFH set IOL=0.0mA FFH set IOL=0.5mA FFH set IOL=1.0mA VIL VIH IIL IIH GND 2.4 - - - - - - 0.6 VCC 10 10 V V A A ICC IDD1 IDD2 - - - 1.1 1.0 1.5 2.5 2.0 3.0 mA mA mA CLK=1MHz Symbol Min. Typ. Max. Unit Conditions
!Circuit operation (1) Power on reset This LSI has a power on reset circuit that sets an analog output to low level in VCC power stand-up. Please be sure that the time constant meets below condition, because the output is undefined when VCC power stand up too rapidly.
Parameter VCC supply voltage rise time Power on reset voltage Symbol trVCC VPOR Min. 10 - Typ. - 2.1 Max. - - Unit ms V VCC=04.5V Conditions
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BH2222FV
Standard ICs
(2) Conditions of operating timing (unless otherwise noted,Ta=25C, VCC=5.0V, VDD1=3.0V, VDD2=5.0V)
Parameter CLK L level pulse width CLK H level pulse width DI setup time DI hold time LD setup time LD hold time LD "H" level pulse width Analog output delay time Symbol tCLKL tCLKH tsDI thDI tsLD thLD tLDH tOUT Min. 200 200 30 60 200 100 100 - Typ. - - - - - - - - Max. - - - - - - - 200 Unit ns ns ns ns ns ns ns s CL=50pF, RL=10k Conditions
tCLKL
tCLKH
CLK
DI
LAST DATA
tsDI
thDI
tLDH tsLD
thLD
LD
OUTPUT
tOUT
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BH2222FV
Standard ICs
(3) Command sending Control command is 3+1wire 16bit serial interface. (LSB first) Data is taken in with the rise edge of the CLK and output data is fixed in the LD high section. Data is maintained in the LD low section. Please change SEL mode in the LD low section.
MSB (LAST) Data set D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 Channel select D4 D3 D2 D1 D0 LSB (FIRST)
*Data set D15 0 0 0 D14 0 0 0 D13 0 0 0 D12 0 0 0 D11 0 0 0 D10 0 0 0 D9 0 0 1 D8 0 1 0 GND (VDD1, 2-GND) / 256x1 (VDD1, 2-GND) / 256x2 Analog output voltage level
1 1
1 1
1 1
1 1
1 1
1 1
1 1
0 1
((VDD1, 2-GND) / 256x254 ((VDD1, 2-GND) / 256x255
*Channel select D7 x x x x x x x x x D6 x x x x x x x x x D5 x x x x x x x x x D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 1 Function Don't Care AO1 SEL x x x 0 Output pin x AO1
1 1
0 0
0 0
0 0
0 1
AO16 EX1_0
AO16 EX1
1 1
0 0
1 1
0 0
0 1
EX4_0 EX1_1
0 1
EX4 EX1
1 1
1 1
0 0
0 0
0 1
EX4_1 Don't Care
1 x x
EX4 x x
1
1
1
1
1
Don't Care
x : Don't Care
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BH2222FV
Standard ICs
!Operation notes (1) Regarding to the DNL & INL This item is guaranteed under below condition. Input code 02HFDH (2) Regarding to the early stage condition With the power on reset, the output is fixed to low level in power stand-up. But the output is undefined when only LD signal is inputted. Input the LD signal after setting data. (3) Regarding to the setting of the each voltage Set the VCC, VDD1, VDD2 to become the following condition. When not satisfied, unnecessary current flows. VCC VDD1, VDD2 (4) Regarding to the power on reset function This function operates detecting the voltage level of the VCC. So, if the voltage level of the VCC become less than power on reset voltage when working, it is a possibility that the outputs become reset condition. !External dimensions (Units : mm)
10.00.2
28 15
7.60.3 5.60.2
1
14
1.150.1 0.1
0.150.1 0.1
0.65
0.220.1
SSOP-B28
0.3Min.
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