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| * BR24L32-W/F-W/FJ-W/FV-W BR24L64-W/F-W Features * 32k bit serial EEPROM organized as 4k x 8bit (BR24L32) 64k bit serial EEPROM organized as 8k x 8bit (BR24L64) * 2 wire bus serial interface (2 byte Address) * Low operating voltage range (2V operating) Read : 1.8~5.5V Write : 1.8~5.5V * Low current consumption Active : 3mA MAX Standby : 2A MAX * Clock frequency : 100kHz MAX (1.8~5.5V) 400kHz MAX (2.5~5.5V) * Write cycle time : 5ms MAX * Address auto-increment function during read operation * Automatic erase-before-write function during write operation * Page write function : 32byte * Inadvertent write protection function Inadvertent write protection at low voltage (Vcc Lock-out function) WP (Write Protect) function * Schmitt trigger circuit and noise filter are built into SCL and SDA pins * 1,000,000 write cycle typical * 40 years data retention * Operating temperature range : -40~85C Pin Configurations A0 1 A1 2 A2 3 GND 4 8 Vcc 7 WP 6 SCL 5 SDA * DIP8/SOP8/SOP-J8/SSOP-B8 DIP8/SOP8 (Only BR24L64) Pin Functions Pin Names A0, A1, A2 GND SDA SCL WP Vcc Ground Serial Data Input/Output Serial Data Clock Write Protect Power Supply Functions Slave Address Inputs * Under development Block Diagram 32~64k bit EEPROM Array A0 A1 A2 12bit: BR24L32 13bit: BR24L64 8bit 12bit: BR24L32 13bit: BR24L64 WP SCL SDA Address Decoder Slave Words Address Register STOP Data Register START Control Logic ACK High Voltage Generation Voltage Detection 9 . 1.8V L opeow vo ratin ltag e g 1, Wri 0 0 0 , 0 0 te c 0 ycle Serial 2 Wire Interface (I2C BUS Type) Timing chart Byte write cycle S T A R T SLAVE ADDRESS 101 0 A2 A1 A0 RA /C WK W R I T E 1st WORD ADDRESS 2nd WORD ADDRESS WA0 DATA D7 A C K D0 A C K S T O P SDA LINE *1 WA12 A C K Page write cycle S T A R T SLAVE ADDRESS 101 0 A2 A1 A0 RA /C WK W R I T E 1st WORD ADDRESS(n) 2nd WORD ADDRESS(n) WA0 DATA(n) D7 A C K D0 A C K DATA(n+31) D0 A C K S T O P SDA LINE *1 WA12 A C K Current read cycle S T A R T SLAVE ADDRESS 101 0 A2 A1 A0 RA /C WK R E A D D7 S T O P D0 A C K DATA SDA LINE Random read cycle S T A R T SLAVE ADDRESS 1 0 1 0 A2 A1 A0 RA /C WK W R I T E 1st WORD ADDRESS(n) 2nd WORD ADDRESS(n) WA0 S T A R T SLAVE ADDRESS 1 0 1 0 A2 A1 A0 R E A D DATA(n) S T O P SDA LINE WA12 *1 D7 RA /C WK D0 A C K A C K A C K Sequential read cycle S T A R T SLAVE ADDRESS 1 0 1 0 A2 A1 A0 RA /C WK R E A D S T O P DATA(n) DATA(n+x) SDA LINE D7 D0 A C K A C K D7 D0 A C K *1: WA12...Don't Care (BR24L32) Note : BR24C32/F has no letter "-W", but it is a double-cell type. BR24C64/F is a single-cell type. Please be careful not to confuse w-cell type and single-cell type. ("-W" means double-cell type.) 10 |
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