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CS4461 Multi-Bit A/D for Class-D Real-Time PSR Feedback Features Advanced Multi-bit Delta-Sigma Architecture Real-time Feedback of Power Supply Conditions (AC and DC) Filterless Digital Output Resulting in Very Low Signal Delay 135 mW Power Consumption Supports Logic Levels Between 3.3 V and 5.0 V Differential Analog Architecture Modulator Overflow Detection Interfaces Directly to the CS44800/CS44600 Class-D PWM Modulator Multi-bit Conversion at up to 7.5 MHz Delivers Modulated Data Over 2-Wire Interface General Description The CS4461 is a complete analog-to-digital converter for class-D real-time power supply rejection (PSR) feedback. It performs sampling and analog-to-digital conversion, generating digital data for input to a class-D modulator with real-time PSR feedback capabilities. The CS4461 uses a 5th-order, multi-bit delta-sigma modulator followed by output data formatting. The ADC uses a differential architecture which provides excellent noise rejection. The CS4461 feeds back the AC and DC voltage components and is ideal for class-D audio systems requiring high power supply rejection. The CS4461 is available in a 24-pin TSSOP package in both Commercial (-10 to +70 C) and Automotive grade (-40 to +85 C). The CDB44800 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see "Ordering Information" on page 11 for complete details. VQ REFGND PSR_RESET PSR_EN FILT+ Voltage Reference OVERFLOW AIN+ AIN- + LP Filter PSR_MCLK Output Data Formatting PSR_SYNC PSR_DATA S/H DAC 5.0 V (VA) GND 3.3 V to 5.0 V (VDP) http://www.cirrus.com Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved) SEPTEMBER '05 DS650F1 CS4461 TABLE OF CONTENTS 1. 2. 3. 4. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 3 PIN DESCRIPTIONS ............................................................................................................................. 6 TYPICAL CONNECTION DIAGRAM .................................................................................................... 7 APPLICATIONS .................................................................................................................................... 8 4.1 Digital Connections ......................................................................................................................... 8 4.2 Analog Connections ....................................................................................................................... 8 4.3 Power-Up Sequence ...................................................................................................................... 9 4.4 Overflow Detection ......................................................................................................................... 9 4.5 Grounding and Power Supply Decoupling ...................................................................................... 9 5. PACKAGE DIMENSIONS ................................................................................................................. 10 6. ORDERING INFORMATION ............................................................................................................... 11 7. REVISION HISTORY ........................................................................................................................... 11 LIST OF FIGURES Figure 1. Typical Connection Diagram......................................................................................................... 7 Figure 2. CS4461 Recommended Analog Input Buffer................................................................................ 8 2 DS650F1 CS4461 1. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and TA = 25C.) SPECIFIED OPERATING CONDITIONS (GND = 0 V, all voltages with respect to 0 V.) Parameter DC Power Supplies: Ambient Operating Temperature Positive Analog Positive Digital Commercial (-CZZ) Automotive (-DZZ) Symbol VA VDP TAC TAA Min 4.75 3.1 -10 -40 Typ 5.0 3.3 - Max 5.25 5.25 +70 +85 Unit V V C C ABSOLUTE MAXIMUM RATINGS (GND = 0 V, All voltages with respect to ground.) (Note 1) Parameter DC Power Supplies: Input Current Analog Input Voltage Digital Input Voltage Ambient Operating Temperature (Power Applied) Storage Temperature Analog Digital (Note 2) (Note 3) (Note 3) Symbol VA VDP Iin VIN VIND TA Tstg Min -0.3 -0.3 GND - 0.7 -0.7 -50 -65 Max +6.0 +6.0 10 VA + 0.7 VDP + 0.7 +95 +150 Units V V mA V V C C Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current. DS650F1 3 CS4461 DC ELECTRICAL CHARACTERISTICS (GND = 0 V, all voltages with respect to ground. Parameter Power Supply Current (Normal Operation) Power Supply Current (Power-Down Mode) (Note 4) Power Consumption (Normal Operation) (Power-Down Mode) ADC Power Supply Rejection Ratio (1 kHz) VQ Nominal Voltage VA VDP = 5.0 V VDP = 3.3 V VA VDP = 5.0 V VDP = 5.0 V VDP = 3.3 V VDP = 5.0 V (Note 5) PSRR PSR_MCLK=12.288 MHz) Symbol IA ID ID IA ID Min - Typ 17.5 22 14.5 2 2 198 135 20 65 2.5 25 0.01 5 18 0.01 Max 21 26 17 235 161 - Unit mA mA mA mA mA mW mW mW mW dB V k mA V k mA Output Impedance Maximum allowable DC current source/sink FILT+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink Notes: 4. Power Down Mode is defined as PSR_RESET = Low with all clocks and data lines held static. 5. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram. DIGITAL CHARACTERISTICS Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at Io = 100 A Low-Level Output Voltage at Io = 100 A OVERFLOW Current Sink Input Leakage Current (% of VDP) (% of VDP) (% of VDP) (% of VDP) Symbol VIH VIL VOH VOL IOVERFLOW Iin Min 70% 70% - Typ - Max 30% 15% 4.0 10 Units V V V V mA A THERMAL CHARACTERISTICS Parameter Allowable Junction Temperature Junction to Ambient Thermal Impedance Symbol Min - Typ 70 Max 135 - Unit C C/W JA 4 DS650F1 CS4461 ANALOG CHARACTERISTICS (Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz.) Parameter DC Accuracy Gain Error Gain Drift -CZZ -DZZ -CZZ -DZZ (Note 6) CMRR 1.1 1.1 18 - Symbol Min Typ - Max Unit % ppm/C VPP VPP V V k dB 100 1.13*VA 1.13*VA 82 5 3.9 3.9 - Analog Input Characteristics Full-scale Differential Input Voltage AIN+/AIN- Input Range (VA = 5.0 V) Input Impedance (Differential) Common Mode Rejection Ratio Notes: 6. Measured between AIN+ and AIN- DS650F1 5 CS4461 2. PIN DESCRIPTIONS PSR_RESET GND PSR_SYNC PSR_DATA PSR_MCLK VDP GND VDP TEST GND PSR_EN GND Pin Name VDP VA 1 2 3 4 5 6 7 8 9 10 11 12 Top-Down View 24-pin TSSOP Package 24 23 22 21 20 19 18 17 16 15 14 13 Pin Descriprion FILT+ REFGND VQ GND GND VA GND AINAIN+ OVERFLOW VDP VDP # 6 8 13 14 19 2 7 10 12 18 20 21 1 22 23 24 16 17 5 3 4 11 15 9 Digital Logic Power (Input) - Digital core and input/output power supply. Nominally +3.3 V or +5.0 V. Supply decoupling should placed as close as possible to pin 6. Analog Power (Input) - Analog power supply. Nominally +5.0 V. GND Ground (Input) - Ground reference for both analog and digital. PSR_RESET VQ REFGND FILT+ AIN+ AINPSR_MCLK PSR_SYNC PSR_DATA PSR_EN OVERFLOW TEST Reset (Input) - When PSR_RESET is low, the CS4461 enters a low power mode and all internal states are reset. On initial power up, PSR_RESET must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. Reference Ground (Input) - Ground reference for the internal sampling circuits. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuit. Differential PSR Analog Input (Input) - Signals are presented differentially to the delta-sigma modulator via the AIN+/- pins. Master Clock (Input) - Clock source for the delta-sigma modulator and output data. Synchronization Data Output (Output) - Used to synchronize the serial data in the PWM modulator. PSR Serial Data Output (Output) - Power supply modulated and formatted serial data. PSR Enable (Input) - A high to low transition on this pin will enable the PSR feedback circuit. Overflow (Output, open drain) - Indicates a modulator overflow condition. Test (Output) - This pin may toggle during normal operation and should be pulled low through a 47 k resistor to GND in order to minimize noise. 6 DS650F1 CS4461 3. TYPICAL CONNECTION DIAGRAM +3.3 V or +5.0 V 0.1 F VDP +5.0 V VA 47 F 0.1 F PSR_MCLK PSR_SYNC PSR_DATA 22.1 22.1 22.1 PWM Modulator with PSR Processing VDP VDP VDP PSR_EN AIN+ PSR_RESET See "CS4461 Recommended Analog Input Buffer" on page 8. AIN- CS4461 OVERFLOW TEST VDP 47 k VQ 1 F 0.1 F 47 k GND GND GND FILT+ 47 F 0.1 F REFGND GND GND GND GND Figure 1. Typical Connection Diagram DS650F1 7 CS4461 4. APPLICATIONS 4.1 Digital Connections PSR_MCLK provides the system clock for the CS4461. PSR_SYNC and PSR_DATA provide the output of the modulator to the class-D modulator with feedback capabilities. Series damping resistors should be used on PSR_MCLK, PSR_SYNC, and PSR_DATA to minimize noise. These should be placed as close as possible to their signal source. The pin labeled TEST should also be pulled low to GND through a 47 k resistor to minimize noise coupling into the ADC modulator. 4.2 Analog Connections The analog modulator samples the input at PSR_MCLK/4 (6.144 MHz with PSR_MCLK=24.576 MHz). Figure 2 shows the suggested analog input filter. This filter topology will correctly buffer the power supply's AC and DC components for PSR processing by the class-D modulator. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. C0G dielectrics should be used wherever possible. R1 and R2 should be used to scale VP (class-D amplifier high voltage power supply) to less than the CS4461 maximum AIN+/AIN- input voltage (3.9 V). 2 k 2 k 120 pF VP +5.0 V R1 +5.0 V + R2 90.9 649 90.9 AIN+ 120 pF + 2200 pF C0G CS4461 649 AIN- Figure 2. CS4461 Recommended Analog Input Buffer The following equation can be used to scale R1 and R2: 2 * (VP * (1 + %VP_Ripple)) * (R2 / (R1 + R2)) < 3.9 V Example (VP = 40 V, %VP_Ripple = 4%): 2 * (40 * (1 + 0.04)) * (1.96 k / (40.2 k + 1.96 k) = 3.87 V 8 DS650F1 CS4461 4.3 Power-Up Sequence Reliable power-up can be accomplished by keeping the device in reset until the power supplies and clocks are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues. The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a delay between the release of reset and the generation of valid output, due to the finite output impedance of FILT+ and the presence of the external capacitance. 4.4 Overflow Detection The CS4461 includes modulator overflow detection, indicated on pin 15, OVERFLOW (open drain, active low). OVERFLOW will go to a logical low as soon as an overrange condition is detected. The data will remain low until the condition is cleared. 4.5 Grounding and Power Supply Decoupling As with any high resolution converter, the CS4461 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA and VDP connected to clean supplies. VDP, which powers the digital logic, may be run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no additional devices should be powered from VDP. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulator. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ to GND. The CDB44800 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs. DS650F1 9 CS4461 5. PACKAGE DIMENSIONS 24L TSSOP (4.4 mm BODY) PACKAGE DRAWING N D E11 A2 A1 SEATING PLANE A E b2 SIDE VIEW 123 L e END VIEW TOP VIEW INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.03346 0.00748 0.303 0.248 0.169 -0.020 0 NOM -0.004 0.0354 0.0096 0.307 0.2519 0.1732 0.026 BSC 0.024 4 MAX 0.043 0.006 0.037 0.012 0.311 0.256 0.177 -0.028 8 MIN -0.05 0.85 0.19 7.70 6.30 4.30 -0.50 0 MILLIMETERS NOM --0.90 0.245 7.80 6.40 4.40 0.65 BSC 0.60 4 MAX 1.10 0.15 0.95 0.30 7.90 6.50 4.50 -0.70 8 NOTE 2,3 1 1 JEDEC #: MO-153 Controlling Dimension is Millimeters. Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. 10 DS650F1 CS4461 6. ORDERING INFORMATION Product CS4461 Description Multi-bit A/D for Class-D Real-time PSR Feedback Evaluation board for the CS44800/600 and the CS4461 Package Pb-Free 24-TSSOP YES Grade Commercial Automotive Temp Range -10 to +70 C -40 to +85 C - Container Rail Tape & Reel Rail Tape & Reel - Order # CS4461-CZZ CS4461-CZZR CS4461-DZZ CS4461-DZZR CDB44800 CDB44800 - - - 7. REVISION HISTORY Release A1 F1 Date May 2004 September 2005 1st Advance Release Updated ordering information Changes Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. DS650F1 11 |
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