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SONY RAMTM
Description
CXK79M36C162GB
33/4/5
Preliminary
18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36)
The CXK79M36C162GB is a high speed CMOS synchronous static RAM with common I/O pins. It is manufactured in compliance with the JEDEC-standard 209 pin BGA package pinout defined for SigmaRAMTM devices. It integrates input registers, high speed RAM, output registers, and a two-deep write buffer onto a single monolithic IC. Double Data Rate (DDR) Pipelined (PL) read operations and Late Write (LW) write operations are supported, providing a high-performance user interface. Positive and negative output clocks are provided for applications requiring source-synchronous operation. All address and control input signals are registered on the rising edge of the CK differential input clock. During read operations, output data is driven valid twice, from both the rising and falling edges of CK, beginning one full cycle after the address and control signals are registered. During write operations, input data is registered twice, on both the rising and falling edges of CK, beginning one full cycle after the address and control signals are registered. Because two pieces of data are always transferred during read and write operations, the least significant address bit of the internal memory array is not available as an external address pin to this device. Consequently, the number of external address pins available to the device is one less than the specified depth of the device (i.e. the 512Kb x 36 device has 18, not 19, external address pins). And, the user cannot choose the order in which the two pieces of data are read. Read data is always provided in the same order in which it is written. Output drivers are series-terminated, and output impedance is programmable via the ZQ control pin. When an external resistor RQ is connected between ZQ and VSS, the impedance of the SRAM's output drivers is set to ~RQ/5. 300 MHz operation (600 Mbps) is obtained from a single 1.8V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
Features
* 3 Speed Bins -33 -4 -5 Cycle Time / Data Access Time 3.3ns / 1.8ns 4.0ns / 2.1ns 5.0ns / 2.3ns
* Single 1.8V power supply (VDD): 1.7V (min) to 1.95V (max) * Dedicated output supply voltage (VDDQ): 1.4V (min) to VDD (max) * HSTL-compatible I/O interface with dedicated input reference voltage (VREF): VDDQ/2 typical * Common I/O * Double Data Rate (DDR) data transfers * Pipelined (PL) read operations * Late Write (LW) write operations * Burst capability with internally controlled Linear Burst address sequencing * Burst length of two or four, with automatic address wrap * Full read/write data coherency * Differential input clocks (CK and CK) * Data-referenced output clocks (CQ1, CQ1, CQ2, CQ2) * Programmable output driver impedance via dedicated control pin (ZQ) * Depth expansion capability (2 or 4 banks) via programmable chip enables (E2, E3, EP2, EP3) * JTAG boundary scan (subset of IEEE standard 1149.1) * 209 pin (11x19), 1mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
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SONY(R) RAM
CXK79M36C162GB 512Kb x 36 Pin Assignment (Top View)
Preliminary
1 A B C D E F G H J K L M N P R T U V W Notes: NC NC NC NC NC DQ DQ DQ DQ CQ2 NC NC NC NC DQ DQ DQ DQ DQ
2 NC NC NC NC DQ DQ DQ DQ DQ CQ2 NC NC NC NC NC DQ DQ DQ DQ
3 A MCL (2) NC VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS NC A TMS
4 E2 NC MCL (2) VREF VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VREF A A TDI
5 A A (x36) NC (144M) NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC (72M) A A
6 ADV W E1 MCL VDD ZQ EP2 EP3 MCH MCL MCL MCH MCH MCL VDD MCL A A1 MCL (1)
7 A A NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC (36M) A A
8 E3 MCL (2) NC VREF VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VREF A A TDO
9 A NC MCL (2) VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A TCK
10 DQ DQ DQ DQ NC NC NC NC NC CQ1 DQ DQ DQ DQ DQ NC NC NC NC
11 DQ DQ DQ DQ DQ NC NC NC NC CQ1 DQ DQ DQ DQ NC NC NC NC NC
1: Pin 6W is defined as Address Pin A0 in Single Data Rate (SDR) Common I/O SigmaRAMs. However, it must be tied "low" in this device. The least significant address bit of the internal memory array is not available as an externally controlled address pin in Double Data Rate (DDR) Common I/O SigmaRAMs. 2. Pins 3B, 4C, 8B, and 9C are defined as Byte Write Enable Pins Bx in x36 Single Data Rate (SDR) Common I/O SigmaRAMs. However, they must be tied "low" in this device. Byte Write functionality is not supported in Double Data Rate (DDR) Common I/O SigmaRAMs.
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SONY(R) RAM
CXK79M36C162GB Pin Description
Preliminary
Symbol A A1 DQ CK, CK CQ1, CQ1 CQ2, CQ2 E1
Type Input Input I/O Input Output Input
Quantity 17 1 36 2 4 1
Description Address Inputs - Registered on the rising edge of CK. Address Input 1 - Registered on the rising edge of CK. Initializes burst counter. Data Inputs / Outputs - Registered on the rising and falling edges of CK during write operations. Driven from the rising and falling edges of CK during read operations. Differential Input Clocks Output Clocks Chip Enable Control Input - Registered on the rising edge of CK. E1 = 0 enables the device to accept read and write commands. E1 = 1 disables the device. See the Clock Truth Table section for further information. Programmable Chip Enable Control Inputs - Registered on the rising edge of CK. See the Clock Truth Table and Depth Expansion sections for further information. Programmable Chip Enable Active-Level Select Inputs - These pins must be tied "high" or "low" at power-up. See the Clock Truth Table and Depth Expansion sections for further information. Address Advance Control Input - Registered on the rising edge of CK. ADV = 0 loads a new address and begins a new operation when the device is enabled. ADV = 1 increments the address and continues the previous operation when the device is enabled. See the Clock Truth Table section for further information. Write Enable Control Input - Registered on the rising edge of CK. W = 0 specifies a write operation when ADV = 0 and the device is enabled. W = 1 specifies a read operation when ADV = 0 and the device is enabled. See the Clock Truth Table section for further information. Output Impedance Control Resistor Input - This pin must be tied to VSS through an external resistor RQ at power-up. Output driver impedance is set to one-fifth the value of RQ, nominally. See the Output Driver Impedance Control section for further information. 1.8V Core Power Supply - Core supply voltage. Output Power Supply - Output buffer supply voltage. Input Reference Voltage - Input buffer threshold voltage. Ground JTAG Clock JTAG Mode Select - Weakly pulled "high" internally. JTAG Data In - Weakly pulled "high" internally. JTAG Data Out Must Connect "Low" - May not be actual input pins. Must Connect "High" - May not be actual input pins. No Connect - These pins are true no-connects, i.e. there is no internal chip connection to these pins. They can be left unconnected or tied directly to VSS.
E2, E3 EP2, EP3
Input Input
2 2
ADV
Input
1
W
Input
1
ZQ
Input
1
VDD VDDQ VREF VSS TCK TMS TDI TDO MCL MCH NC Input Input Input Output *Input* *Input*
14 24 4 30 1 1 1 1 10 3 52
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SONY(R) RAM
CXK79M36C162GB Clock Truth Table
Preliminary
CK
E1 E ADV W (tn) (tn) (tn) (tn) X X 1 X 0 X 0 X F X T X T X T X 0 1 0 1 0 1 0 1 X X X X 0 X 1 X
Previous Operation X Bank Deselect X Deselect X Write X Read
Current Operation Bank Deselect Bank Deselect (Continue) Deselect Deselect (Continue) Write Loads new address Write Continue Increments address by 2 Read Loads new address Read Continue Increments address by 2
DQ/CQ (tn)
DQ/CQ (tn+1/2)
DQ/CQ (tn+1)
DQ/CQ (tn+11/2)
*** Hi-Z *** Hi-Z/CQ *** D1/CQ *** Q1/CQ *** D2/CQ *** Q2/CQ
Hi-Z Hi-Z Hi-Z/CQ Hi-Z/CQ D1/CQ D3/CQ Q1/CQ Q3/CQ D2/CQ D4/CQ Q2/CQ Q4/CQ
Notes: 1. "1" = input "high"; "0" = input "low"; "X" = input "don't care"; "T" = input "true"; "F" = input "false". 2. "***" indicates that the DQ input requirement or output state and the CQ output state are determined by the previous operation. 3. If E2 = EP2 and E3 = EP3 then E = "T" else E = "F". 4. DQs are tri-stated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled. 5. CQs are tri-stated in response to Bank Deselect commands only, one full cycle after the command is sampled. 6. One (1) Continue operation may be initiated after a Read or Write operation is initiated to burst transfer four (4) distinct pieces of data per single external address input. If a second (2nd) Continue operation is initiated, the internal address wraps back to the initial external (base) address.
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SONY(R) RAM
CXK79M36C162GB State Diagram
X,F,0,X or X,X,1,X
Preliminary
0,T,0,1
Bank Deselect
1,T,0,X
0,T,0,0
X,F,0,X
Deselect
0,T,0,1 0,T,0,0
1,T,0,X or X,X,1,X
1,T,0,X 0,T,0,0
1,T,0,X
Read
X,F,0,X 0,T,0,1 X,X,1,X 0,T,0,1
Write
X,F,0,X 0,T,0,0 X,X,1,X
0,T,0,1 1,T,0,X X,F,0,X
0,T,0,0 0,T,0,0 0,T,0,1
Read Continue
X,X,1,X
Write Continue
X,X,1,X
1,T,0,X X,F,0,X
Notes: 1. The notation "X,X,X,X" controlling the state transitions above indicate the states of inputs E1, E, ADV, and W respectively. 2. "1" = input "high"; "0" = input "low"; "X" = input "don't care"; "T" = input "true"; "F" = input "false". 3. If E2 = EP2 and E3 = EP3 then E = "T" else E = "F".
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SONY(R) RAM *Burst (Continue) Operations
CXK79M36C162GB
Preliminary
Because two pieces of data are always transferred during read and write operations, the least significant address bit (A0) of the internal memory array is not available as an external address pin to these devices. Rather, the address bit is set to "0" internally prior to the first data transfer and set to "1" internally prior to the second data transfer. Consequently, the two pieces of data transferred during read and write operations are always read in the same address sequence in which they are written. Burst operations follow the simple address sequence depicted in the table below: A1 1st (Base) Address 2nd Address 0 1 A1 1 0 Sequence Key A1 A1
One (1) Continue operation may be initiated after a Read or Write operation is initiated to burst transfer four (4) distinct pieces of data per single external address input. If a second (2nd) Continue operation is initiated, the internal address wraps back to the initial external (base) address.
*Depth Expansion
Depth expansion in these devices is supported via programmable chip enables E2 and E3. The active levels of E2 and E3 are programmable through the static inputs EP2 and EP3 respectively. When EP2 is tied "high", E2 functions as an active-high input. When EP2 is tied "low", E2 functions as an active-low input. Similarly, when EP3 is tied "high", E3 functions as an active-high input. And, when EP3 is tied "low", E3 functions as an active-low input. The programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming E2 and E3 of four devices in a binary sequence (00, 01, 10, 11), and by driving E2 and E3 with external address signals, the four devices can be made to look like one larger device. When these devices are deselected via chip enable E1, the output clocks continue to toggle. However, when these devices are deselected via programmable chip enables E2 or E3, the output clocks are forced to a Hi-Z state. See the Clock Truth Table for further information.
*Output Driver Impedance Control
The impedance of the data and clock output drivers in these devices can be controlled via the static input ZQ. When an external impedance matching resistor (RQ) is connected between ZQ and VSS, output driver impedance is set to one-fifth the value of the resistor, nominally. See the DC Electrical Characteristics section for further information. Output driver impedance is updated whenever the data output drivers are in an inactive (High-Z) state. See the Clock Truth Table section for information concerning which commands deactivate the data output drivers. At power up, 8192 clock cycles followed by any command that deactivates the data output drivers are required to ensure that the output impedance has reached the desired value. Note: The impedance of the output drivers will drift somewhat due to changes in temperature and voltage. Consequently, during operation, the output drivers should be deactivated periodically in order to update the output impedance and ensure that it remains within specified tolerances.
*Power-Up Sequence
For reliability purposes, Sony recommends that power supplies power up in the following sequence: VSS, VDD, VDDQ, VREF, and Inputs. VDDQ should never exceed VDD. If this power supply sequence cannot be met, a large bypass diode may be required between VDD and VDDQ. Please contact Sony Memory Application Department for further information.
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SONY(R) RAM *Absolute Maximum Ratings
Parameter Supply Voltage Output Supply Voltage Input Voltage (Address, Control, Data, Clock) (MCL pins 3B, 8B, 4C, 9C, 6W) Input Voltage (EP2, EP3) (MCH pins 6J, 6M, 6N) (MCL pins 6D, 6K, 6L, 6P, 6T) Input Voltage (TCK, TMS, TDI) Operating Temperature Junction Temperature Storage Temperature
CXK79M36C162GB
Preliminary
Symbol VDD VDDQ VIN
Rating -0.5 to +2.5 -0.5 to +2.3 -0.5 to VDDQ+0.5 (2.3V max)
Units V V V
VMIN VTIN TA TJ TSTG
-0.5 to VDD+0.5 (2.5V max) -0.5 to VDD+0.5 (2.5V max) 0 to 85 0 to 110 -55 to 150
V V C C C
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
*BGA Package Thermal Characteristics
Parameter Junction to Case Temperature Symbol JC Rating 3.6 Units C/W
*I/O Capacitance
Parameter Address Input Capacitance Control CK Clock Data Output Capacitance CQ Clock Symbol CIN CIN CKIN COUT COUT Test conditions VIN = 0V VIN = 0V VKIN = 0V VOUT = 0V VOUT = 0V Min -----------
(TA = 25oC, f = 1 MHz) Max 3.5 3.5 4.0 4.5 4.5 Units pF pF pF pF pF
Note: These parameters are sampled and are not 100% tested.
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SONY(R) RAM
CXK79M36C162GB
Preliminary
(VSS = 0V, TA = 0 to 85oC)
*DC Recommended Operating Conditions
Parameter Supply Voltage Output Supply Voltage Input Reference Voltage Input High Voltage (Address, Control, Data) Input Low Voltage (Address, Control, Data) Input High Voltage (EP2, EP3, MCH) Input Low Voltage (EP2, EP3, MCL) Clock Input Signal Voltage Clock Input Differential Voltage Clock Input Common Mode Voltage Symbol VDD VDDQ VREF VIH VIL VMIH VMIL VKIN VDIF VCM Min 1.7 1.4 VDDQ/2 - 0.1 VREF + 0.2 -0.3 VREF + 0.3 -0.3 -0.3 0.4 VDDQ/2 - 0.1 Typ 1.8 --VDDQ/2 ------------VDDQ/2
Max 1.95 VDD VDDQ/2 + 0.1 VDDQ + 0.3 VREF - 0.2 VDD + 0.3 VREF - 0.3 VDDQ + 0.3 VDDQ + 0.6 VDDQ/2 + 0.1
Units V V V V V V V V V V
Notes
1 2 3
2,3
1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component. 2. VIH (max) AC = VDDQ + 0.9V for pulse widths less than one-quarter of the cycle time (tCYC/4). 3. VIL (min) AC = -0.9V for pulse widths less than one-quarter of the cycle time (tCYC/4).
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SONY(R) RAM *DC Electrical Characteristics
Parameter Input Leakage Current (Address, Control, Clock) Input Leakage Current (EP2, EP3) Input Leakage Current (MCH) Input Leakage Current (MCL) Output Leakage Current Average Power Supply Operating Current Power Supply Deselect Operating Current Output High Voltage Output Low Voltage Symbol ILI IMLI1 IMLI2 IMLI3 ILO IDD-33 IDD-4 IDD-5 IDD2 VOH VOL
CXK79M36C162GB
Preliminary
(VDD = 1.8V 0.1V, VSS = 0V, TA = 0 to 85oC) Test Conditions VIN = VSS to VDDQ VMIN = VSS to VDD VMIN = VMIH (min) to VDD VMIN = VSS to VMIL (max) VOUT = VSS to VDDQ IOUT = 0 mA VIN = VIH or VIL IOUT = 0 mA VIN = VIH or VIL IOH = -7.0 mA RQ = 250 IOL = 7.0 mA RQ = 250 VOH, VOL = VDDQ/2 RQ < 150 VOH, VOL = VDDQ/2 150 RQ 300 VOH, VOL = VDDQ/2 RQ > 300 Min -5 -10 -10 -10 -10 --------VDDQ - 0.4 ----(RQ/5)* 0.85 51 (60*0.85) Typ ------------------------RQ/5 --Max 5 10 10 10 10 750 650 550 250 --0.4 35 (30*1.15) (RQ/5)* 1.15 --Units uA uA uA uA uA mA Notes
mA V V 2 1
Output Driver Impedance
ROUT
1. For maximum output drive (i.e. minimum impedance), the ZQ pin can be tied directly to VSS. 2. For minimum output drive (i.e. maximum impedance), the ZQ pin can be left unconnected or tied directly to VDDQ.
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SONY(R) RAM *AC Electrical Characteristics
CXK79M36C162GB
Preliminary (VDD = 1.8V 0.1V, VSS = 0V, TA = 0 to 85oC)
-33 Parameter Symbol Min Input Clock Cycle Time Input Clock High Pulse Width Input Clock Low Pulse Width Address Input Setup Time Address Input Hold Time Control Input Setup Time Control Input Hold Time Data Input Setup Time Data Input Hold Time Input Clock High to Output Data Valid Input Clock Low to Output Data Valid Input Clock High to Output Data Hold Input Clock Low to Output Data Hold Input Clock High to Output Data Low-Z Input Clock High to Output Data High-Z Input Clock High to Output Clock High Input Clock Low to Output Clock Low Input Clock High to Output Clock Low-Z Input Clock High to Output Clock High-Z Output Clock High to Output Data Valid Output Clock Low to Output Data Valid Output Clock High to Output Data Hold Output Clock Low to Output Data Hold tKHKH tKHKL tKLKH tAVKH tKHAX tBVKH tKHBX tDVKH tDVKL tKHDX tKLDX tKHQV tKLQV tKHQX tKLQX tKHQX1 tKHQZ tKHCH tKLCL tKHCX1 tKHCZ tCHQV tCLQV tCHQX tCLQX 3.3 1.3 1.3 0.7 0.4 0.7 0.4 0.35 0.3 --Max ------------------1.8 Min 4.0 1.5 1.5 0.8 0.5 0.8 0.5 0.4 0.35 ---
-4 Max ------------------2.1 Min 5.0 2.0 2.0 1.0 0.5 1.0 0.5 0.45 0.4 ---
-5 Units Notes Max ------------------2.3 ns ns ns ns ns ns ns ns ns ns 1 1
0.5 0.5 --0.5 0.5 -----0.25
----1.8 1.8 --1.8 0.25 ---
0.5 0.5 --0.5 0.5 -----0.25
----2.1 2.1 --2.1 0.25 ---
0.5 0.5 --0.5 0.5 -----0.3
----2.3 2.3 --2.3 0.3 ---
ns ns ns ns ns ns ns ns
2 2,3 2,3
2,3 2,3 2 2
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal, unless otherwise noted. 1. These parameters apply to control inputs E1, E2, E3, ADV, and W. 2. These parameters are guaranteed by design through extensive corner lot characterization. 3. These parameters are measured at 50mV from steady state voltage.
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SONY(R) RAM *AC Electrical Characteristics (Note)
CXK79M36C162GB
Preliminary
The four AC timing parameters listed below are tested according to specific combinations of Output Clocks (CQs) and Output Data (DQs): 1. tCHQV 2. tCLQV 3. tCHQX 4. tCLQX Output Clock High to Output Data Valid (max) Output Clock Low to Output Data Valid (max) Output Clock High to Output Data Hold (min) Output Clock Low to Output Data Hold (min)
The specific CQ / DQ combinations are defined as follows: 512Kb x 36 CQs 1K, 2K DQs 2E, 1F, 2F, 1G, 2G, 1H, 2H, 1J, 2J, 1R, 1T, 2T, 1U, 2U, 1V, 2V, 1W, 2W
10K, 11K 10A, 11A, 10B, 11B, 10C, 11C, 10D, 11D, 11E, 10L, 11L, 10M, 11M, 10N, 11N, 10P, 11P, 10R
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SONY(R) RAM *AC Test Conditions (VDDQ = 1.8V)
Parameter Input Reference Voltage Input High Level Input Low Level Input Rise & Fall Time Input Reference Level Clock Input High Voltage Clock Input Low Voltage Clock Input Common Mode Voltage Clock Input Rise & Fall Time Clock Input Reference Level Output Reference Level Output Load Conditions
CXK79M36C162GB
Preliminary
(VDD = 1.8V 0.1V, VDDQ = 1.8V 0.1V, TA = 0 to 85C) Symbol VREF VIH VIL Conditions 0.9 1.4 0.4 2.0 0.9 VKIH VKIL VCM 1.4 0.4 0.9 2.0 CK/CK cross 0.9 RQ = 250 Units V V V V/ns V V V V V/ns V V See Figure 1 below VDIF = 1.0V VDIF = 1.0V Notes
Figure 1: AC Test Output Load (VDDQ = 1.8V)
0.9 V 16.7 50 50 5 pF DQ 16.7 0.9 V 16.7 50 50 5 pF
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SONY(R) RAM *AC Test Conditions (VDDQ = 1.5V)
Parameter Input Reference Voltage Input High Level Input Low Level Input Rise & Fall Time Input Reference Level Clock Input High Voltage Clock Input Low Voltage Clock Input Common Mode Voltage Clock Input Rise & Fall Time Clock Input Reference Level Output Reference Level Output Load Conditions
CXK79M36C162GB
Preliminary
(VDD = 1.8V 0.1V, VDDQ = 1.5V 0.1V, TA = 0 to 85C) Symbol VREF VIH VIL Conditions 0.75 1.25 0.25 2.0 0.75 VKIH VKIL VCM 1.25 0.25 0.75 2.0 CK/CK cross 0.75 RQ = 250 Units V V V V/ns V V V V V/ns V V See Figure 2 below VDIF = 1.0V VDIF = 1.0V Notes
Figure 2: AC Test Output Load (VDDQ = 1.5V)
0.75 V 16.7 50 50 5 pF DQ 16.7 0.75 V 16.7 50 50 5 pF
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SONY(R) RAM
CXK79M36C162GB One Bank Read-Write-Read Timing Diagram
Figure 3
Preliminary
Read
Read Continue
Read
Deselect
Deselect
Write
Write Continue
Write
Read
Deselect
Deselect (Continue)
CK
CK
tAVKH tKHAX tKHKH tKHKL tKLKH
A A1
A2
A3
tBVKH tKHBX
A4
A5
E1
ADV
W
tKLQV tKLQX
tKHQV tKHQX
tKHQZ tKHQX1 tDVKH tKHDX tDVKL tKLDX
Q11 Q12 Q13 Q14 Q21 Q22 DQ
tCLQX tCLQV tCHQX
Q51 Q52
D31 D32 D33 D34 D41 D42
tKHCH tCHQV
tKLCL
CQ
CQ
Note: In the diagram above, two Deselect operations are inserted between Read and Write operations to control the data bus transition
from output to input. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, one Deselect operation may be sufficient.
Note: E1 = EP1 and E2 = EP2 in this example (not shown).
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SONY(R) RAM
CXK79M36C162GB Two Bank Read-Write-Read Timing Diagram
Figure 4
Preliminary
B1: B2:
Read Write B-Deselect B-Deselect B-Deselect R-Continue B-Deselect Deselect B-Deselect B-Deselect B-Deselect B-Deselect B-Deselect Read B-Deselect Deselect Write W-Continue B-Deselect Read Deselect Deselect
CK
CK
A A1
A2
A3
A4
A5
E2
E1
ADV
W Q11 Q12 Q13 Q14 DQ (B1) Q21 Q22 DQ (B2)
tKHCZ tKHCX1
D41 D42 Q51 Q52 D31 D32 D33 D34
CQ (B1)
CQ (B1)
CQ (B2)
CQ (B2)
Note: In the diagram above, two Deselect operations are inserted between Read and Write operations to control the data bus transition
from output to input. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, one Deselect operation may be sufficient.
Note: Bank 1 EP1 = "low", Bank 2 EP1 "high", and Bank 1 and Bank 2 E2 = EP2 in this example (not shown).
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SONY(R) RAM *Test Mode Description
CXK79M36C162GB
Preliminary
These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1 functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), SRAMs, other components, and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, these devices contain a TAP Controller and four TAP Registers. The TAP Registers consist of one Instruction Register and three Data Registers (ID, Bypass, and Boundary Scan Registers). The TAP consists of the following four signals: TCK: TMS: TDI: TDO: Test Clock Test Mode Select Test Data In Test Data Out Induces (clocks) TAP Controller state transitions. Inputs commands to the TAP Controller. Sampled on the rising edge of TCK. Inputs data serially to the TAP Registers. Sampled on the rising edge of TCK. Outputs data serially from the TAP Registers. Driven from the falling edge of TCK.
Disabling the TAP
When JTAG is not used, TCK should be tied "low" to prevent clocking the SRAM. TMS and TDI should either be tied "high" through a pull-up resistor or left unconnected. TDO should be left unconnected. Note: Operation of the TAP does not disrupt normal SRAM operation except when the EXTEST-A or SAMPLE-Z instruction is selected. Consequently, TCK, TMS, and TDI can be controlled any number of ways without adversely affecting the functionality of the device.
JTAG DC Recommended Operating Conditions
Parameter JTAG Input High Voltage (TCK, TMS, TDI) JTAG Input Low Voltage (TCK, TMS, TDI) JTAG Output High Voltage (TDO) JTAG Output Low Voltage (TDO) JTAG Output High Voltage (TDO) JTAG Output Low Voltage (TDO) JTAG Input Leakage Current JTAG Output Leakage Current Symbol VTIH VTIL VTOH VTOL VTOH VTOL ITLI ITLO Test Conditions ----ITOH = -100uA ITOL = 100uA ITOH = -8mA ITOL = 8mA VTIN = VSS to VDD VTOUT = VSS to VDD
(VDD = 1.8V 0.1V, TA = 0 to 85C) Min VDD/2 + 0.3 -0.3 VDD - 0.1 --VDD - 0.4 ---20 -10 Max VDD + 0.3 VDD/2 - 0.3 --0.1 --0.4 10 10 Units V V V V V V uA uA
JTAG AC Test Conditions
Parameter JTAG Input High Level JTAG Input Low Level JTAG Input Rise & Fall Time JTAG Input Reference Level JTAG Output Reference Level JTAG Output Load Condition Symbol VTIH VTIL Conditions 1.8 0.0 1.0 0.9 0.9
(VDD = 1.8V 0.1V, TA = 0 to 85C) Units V V V/ns V V See Fig. 1 (page 12) Notes
18Mb 1x2Lp, HSTL, rev 1.1
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SONY(R) RAM
JTAG AC Electrical Characteristics
Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Setup Time TMS Hold Time TDI Setup Time TDI Hold Time
CXK79M36C162GB
Preliminary
Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tDVTH tTHDX tCS tCH tTLQV tTLQX
Min 50 20 20 5 5 5 5 5 8
Max
Units ns ns ns ns ns ns ns ns ns
Notes
Capture Setup Time (Address, Control, Data, Clock) Capture Hold Time (Address, Control, Data, Clock) TCK Low to TDO Valid TCK Low to TDO Hold
1 1
10 0
ns ns
1. These parameters are guaranteed by design through extensive corner lot characterization.
JTAG Timing Diagram
Figure 5
tTHTL
tTLTH
tTHTH
TCK
tMVTH
tTHMX
TMS
tDVTH tTHDX
TDI
tTLQV tTLQX
TDO
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SONY(R) RAM
TAP Controller
CXK79M36C162GB
Preliminary
The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the operations associated with each TAP Instruction. State transitions are controlled by TMS and occur on the rising edge of TCK. The TAP Controller enters the "Test-Logic Reset" state in one of two ways: 1. At power up. 2. When a logic "1" is applied to TMS for at least 5 consecutive rising edges of TCK. The TDI input receiver is sampled only when the TAP Controller is in either the "Shift-IR" state or the "Shift-DR" state. The TDO output driver is active only when the TAP Controller is in either the "Shift-IR" state or the "Shift-DR" state. TAP Controller State Diagram
Figure 6 1
Test-Logic Reset
0 0
Run-Test / Idle
1
Select DR-Scan
1
Select IR-Scan
1
0 1
Capture-DR
0 1
Capture-IR
0
Shift-DR
0 0
Shift-IR
0
1 1
Exit1-DR
1 1
Exit1-IR
0
Pause-DR
0 0
Pause-IR
0
1
Exit2-DR
1 0
Exit2-IR
0
1
Update-DR
1
Update-IR
1
0
1
0
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SONY(R) RAM
TAP Registers
CXK79M36C162GB
Preliminary
TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial output data (to TDO) on the subsequent falling edge of TCK. They are divided into two groups: "Instruction Registers" (IR), which are manipulated via the "IR" states in the TAP Controller, and "Data Registers" (DR), which are manipulated via the "DR" states in the TAP Controller. Instruction Register (IR - 3 bits) The Instruction Register stores the various TAP Instructions supported by these devices. It is loaded with the IDCODE instruction at power-up, and when the TAP Controller is in the "Test-Logic Reset" and "Capture-IR" states. It is inserted between TDI and TDO when the TAP Controller is in the "Shift-IR" state, at which time it can be loaded with a new instruction. However, newly loaded instructions are not executed until the TAP Controller has reached the "Update-IR" state. The Instruction Register is 3 bits wide, and is encoded as follows: Code (2:0) 000
Instruction EXTEST-A
Description Loads the individual logic states of all signals composing the SRAM's I/O ring into the Boundary Scan Register when the TAP Controller is in the "Capture-DR" state, and inserts the B-Scan Register between TDI and TDO when the TAP Controller is in the "Shift-DR" state. Also enables the SRAM's data and clock output drivers, and moves the contents of the B-Scan Register associated with the data and clock output signals to the input side of the SRAM's output register. The SRAM's input clock can then be used to transfer the B-Scan Register contents directly to the data and clock output pins (the input clock controls the SRAM's output register). Note that newly captured and/or shifted B-Scan Register contents do not appear at the input side of the SRAM's output register until the TAP Controller has reached the "UpdateDR" state. See the Boundary Scan Register description for more information. Loads a predefined device- and manufacturer-specific identification code into the ID Register when the TAP Controller is in the "Capture-DR" state, and inserts the ID Register between TDI and TDO when the TAP Controller is in the "Shift-DR" state. See the ID Register description for more information. Loads the individual logic states of all signals composing the SRAM's I/O ring into the Boundary Scan Register when the TAP Controller is in the "Capture-DR" state, and inserts the B-Scan Register between TDI and TDO when the TAP Controller is in the "Shift-DR" state. Also disables the SRAM's data and clock output drivers. See the Boundary Scan Register description for more information. Do not use. Reserved for manufacturer use only. Loads the individual logic states of all signals composing the SRAM's I/O ring into the Boundary Scan Register when the TAP Controller is in the "Capture-DR" state, and inserts the B-Scan Register between TDI and TDO when the TAP Controller is in the "Shift-DR" state. See the Boundary Scan Register description for more information. Do not use. Reserved for manufacturer use only. Do not use. Reserved for manufacturer use only. Loads a logic "0" into the Bypass Register when the TAP Controller is in the "Capture-DR" state, and inserts the Bypass Register between TDI and TDO when the TAP Controller is in the "Shift-DR" state. See the Bypass Register description for more information.
001
IDCODE
010
SAMPLE-Z
011 100
PRIVATE SAMPLE
101 110 111
PRIVATE PRIVATE BYPASS
Bit 0 is the LSB of the Instruction Register, and Bit 2 is the MSB. When the Instruction Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO.
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SONY(R) RAM
Bypass Register (DR - 1 bit)
CXK79M36C162GB
Preliminary
The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with a logic "0" when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the "Capture-DR" state. It is inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Register and the TAP Controller is in the "Shift-DR" state. ID Register (DR - 32 bits) The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the "Capture-DR" state. It is inserted between TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the "Shift-DR" state. The ID Register is 32 bits wide, and is encoded as follows: Revision Number (31:28) xxxx Part Number (27:12) 0000 0000 0101 1011 Sony ID (11:1) 0000 1110 001 Start Bit (0) 1
Device 512Kb x 36
Bit 0 is the LSB of the ID Register, and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO. Boundary Scan Register (DR - 84 bits) The Boundary Scan Register is equal in length to the number of active signal connections to the SRAM (excluding the TAP pins) plus a number of place holder locations reserved for functional and/or density upgrades. It is loaded with the individual logic states of all signals composing the SRAM's I/O ring when the EXTEST-A, SAMPLE, or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the "Capture-DR" state. It is inserted between TDI and TDO when the EXTEST-A, SAMPLE, or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the "Shift-DR" state. The Boundary Scan Register contains the following bits: 512Kb x 36 DQx A, A1 CK, CK CQ1, CQ2, CQ1, CQ2 E1, ADV, W E2, E3, EP2, EP3 ZQ Place Holder 36 18 2 4 3 4 1 16
Note: CK and CK are connected to a differential input receiver that generates a single-ended input clock to these devices. Therefore, in order to capture deterministic values for these signals in the Boundary Scan Register, they must be at opposite logic levels when sampled. Note: When an external resistor RQ is connected between the ZQ pin and VSS, the value of the ZQ signal captured in the Boundary Scan Register is non-deterministic.
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SONY(R) RAM
CXK79M36C162GB
Preliminary
Boundary Scan Register Bit Order Assignments The tables below depict the order in which the bits are arranged in the Boundary Scan Register. Bit 1 is the LSB and bit 84 is the MSB. When the Boundary Scan Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO. 512Kb x 36 Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 22 24 25 26 27 28 29 30 31 32 33 34 35 Signal NC NC NC
(1) (1) (1) (1)
Pad 5C 5U 7U 6D 6K 6P 6T 6N 6M 6L 10R 11P 10P 11N 10N 11M 10M 11L 10L 11K 10K 11E 10D 11D 10C 11C 10B 11B 11A 10A 9C 8B 6H 6G 9A
Bit 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
Signal E3 A A W ADV E1 A A E2 A ZQ MCL MCL DQ DQ DQ DQ DQ DQ DQ DQ DQ CQ2 CK CK CQ2 DQ DQ DQ DQ DQ DQ DQ DQ DQ
Pad 8A 7B 7A 6B 6A 6C 5A 5B 4A 3A 6F 4C 3B 2E 1F 2F 1G 2G 1H 2H 1J 2J 1K 3K 4K 2K 1R 2T 1T 2U 1U 2V 1V 1W 2W
Bit 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Signal MCH A A A A A A MCL A1 A A A A A
Pad 6J 3V 4V 4U 5V 6U 5W 6W 6V 7V 8V 7W 8U 9V
MCL
MCL (1) MCL (1) MCL MCH
(1) (2)
MCH MCL DQ DQ DQ DQ DQ DQ DQ DQ DQ CQ1 CQ1 DQ DQ DQ DQ DQ DQ DQ DQ DQ MCL MCL EP3 EP2 A
Note 1: These NC and MCL pins are connected to VSS internally, regardless of pin connection externally. Note 2: This MCH pin is connected to VDD internally, regardless of pin connection externally.
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SONY(R) RAM *Ordering Information
Part Number CXK79M36C162GB-33 CXK79M36C162GB-4 CXK79M36C162GB-5 VDD 1.8V 1.8V 1.8V
CXK79M36C162GB
Preliminary
I/O Type HSTL HSTL HSTL
Configuration 512Kb x 36 512Kb x 36 512Kb x 36
Speed (Cycle Time / Data Access Time) 3.3ns / 1.8ns 4.0ns / 2.1ns 5.0ns / 2.3ns
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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SONY(R) RAM
CXK79M36C162GB
Preliminary
*(11x19) 209 Pin BGA Package Dimensions
209PIN BGA (PLASTIC)
14.0
2.0 0.3 0.30 S A X 0.5 0.1
1.0
2.0
13.0
1.0
A
W V U T R P N M L K J H G F E D C B A
0.30 S B
PIN 1 INDEX
22.0
21.0
1 2 3 4 5 6 7 8 9 10 11
.0 C1 3-
x4
C1
0.20
.5
S
209 - 0.6 0.1
0.10 M
2.0
PRELIMINARY
SONY CODE JEITA CODE JEDEC CODE BGA-209P-01 P-BGA209-14X22-1.0
18Mb 1x2Lp, HSTL, rev 1.1
4C 1. 7
0.35 S 0.15 S DETAIL X
B
S
AB
PACKAGE STRUCTURE
PACKAGE MATERIAL TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS EPOXY RESIN COPPER-CLAD LAMINATE SOLDER 1.1g
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SONY(R) RAM *Revision History
Rev. # rev 0.0 rev 0.1 Rev. Date 02/23/01 07/06/01 Initial Version.
CXK79M36C162GB
Preliminary
Description of Modifications
1. Modified DC Electrical Characteristics section (p. 9). Added IDD-33 and IDD-44 Average Power Supply Operating Current specifications. 2. Added 209 Pin BGA Package Dimensions (p. 24). 1. Added BGA Package Thermal Characteristics (p. 8). 2. Modified AC Electrical Characteristics section (p. 11). Removed "-44" bin. Added "-5" bin. -4 tCHCL tKHKL 0.12 to tKHKL 0.1 tCLCH tKLKH 0.12 to tKLKH 0.1 3. Added JTAG ID Codes (p. 21). 4. Added JTAG Boundary Scan Register Bit Order Assignments (pp. 22-23). 1. Modified Pin Assignment section (p. 2-4). Pin 1K CQ to CQ2 Pin 2K CQ to CQ2 Pin 10K CQ to CQ1 Pin 11K CQ to CQ1 Pin 6J M4 to MCH Pin 6L M2 to MCL Pin 6M M3 to MCH 2. Modified I/O Capacitance section (p. 8). CKIN 3.5pF to 4.0pF 3. Modified DC Recommended Operating Conditions section (p. 9). Combined -1.8 and -1.5 line items into one for VDDQ, VREF, and VCM. VREF (min) 0.65V to VDDQ/2 - 0.1V VREF (max) 1.0V to VDDQ/2 + 0.1V VCM (min) 0.65V to VDDQ/2 - 0.1V VCM (max) 1.0V to VDDQ/2 + 0.1V Removed notes 1 and 2. 4. Modified DC Electrical Characteristics section (p. 10). Added MCH and MCL Input Leakage Current specifications. Reduced x36 Average Power Supply Operating Currents by 100mA. Reduced x18 Average Power Supply Operating Currents by 50mA. 5. Modified AC Electrical Characteristics section (p. 11). -33 tKHCH (max), tKLCL (max), tKHCZ 1.7ns to 1.8ns -4 tKHCH (max), tKLCL (max), tKHCZ 2.0ns to 2.1ns -5 tKHCH (max), tKLCL (max), tKHCZ 2.2ns to 2.3ns 6. Modified JTAG DC Recommended Operating Conditions section (p. 17). VTIH (min) 1.2V to VDD/2 + 0.3V VTIL (max) 0.6V to VDD/2 - 0.3V ITLI (min) -10uA to -20uA 7. Modified JTAG AC Electrical Characteristics section (p. 18). tTHTH 20ns to 50ns tTHTL, tTLTH 8ns to 20ns Added tCS Capture Setup and tCH Capture Hold specifications. 8. Modified TAP Registers section (p. 20). Instruction Register Codes 011, 110 Bypass to Private 9. Modified Boundary Scan Register Bit Order Assignments section (p. 22). x36 Bit 29 10A to 11A x36 Bit 30 11A to 10A
rev 0.2
02/22/02
rev 1.0
07/19/02
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SONY(R) RAM
Rev. # rev 1.1 Rev. Date 11/08/02
CXK79M36C162GB
Description of Modifications
Preliminary
1. Removed x18 organization and all related references. 2. Modified Pin Description section (p. 3). For NC pins, removed reference to VDD and VDDQ. 3. Modified AC Electrical Characteristics section (p. 10). -33 tCHQV, tCLQV 0.2ns to 0.25ns tCHQX, tCLQX -0.2ns to -0.25ns Removed tCHCL and tCLCH Output Clock High and Low Pulse Width specifications. 4. Modified JTAG AC Electrical Characteristics section (p. 17). tCH 5ns to 8ns Added Note 1 for tCS and tCH specifications.
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