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Design Example Report
Title Specification Application Author Document Number Date Revision 21.7 W Power Supply using TOP246P Input: 85 - 265 VAC Output: 48 V / 450 mA PoE AC Adapter Power Integrations Applications Department DER-97 September 12, 2005 1.0
Summary and Features * * * * * * * * * Single Sided PC board Reduced cost and component count Eliminates two y-capacitors to ground Eliminates secondary side common mode choke Eliminates ground wire differential choke High Efficiency (~ 80 %) Lower Cost Transformer Construction - no sleeving termination required Low EMI signature (both radiated and conducted emissions) Built-in output short circuit protection
The products and applications illustrated herein (including circuits external to the products and transformer construction) may be covered by one or more U.S. and foreign patents or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations' patents may be found at www.powerint.com.
Power Integrations 5245 Hellyer Avenue, San Jose, CA 95138 USA. Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com
DER-97
21.7 W PoE Adapter
September 12, 2005
Table Of Contents
Introduction................................................................................................................. 3 Power Supply Specification ........................................................................................ 4 Schematic................................................................................................................... 5 Circuit Operation ........................................................................................................ 6 4.1 General ............................................................................................................... 6 4.2 Description .......................................................................................................... 6 5 Bill of Materials ........................................................................................................... 7 6 Layout......................................................................................................................... 9 7 Transformer Design Spreadsheet ............................................................................ 10 8 Transformer Specification......................................................................................... 13 9 Performance............................................................................................................. 17 9.1 Efficiency........................................................................................................... 17 9.2 Regulation vs. Load........................................................................................... 18 9.3 Regulation vs. Line............................................................................................ 19 9.4 Raw Performance Data ..................................................................................... 20 10 Waveforms............................................................................................................ 21 10.1 Drain Current and Voltage................................................................................. 21 10.2 Output Transient Load Response ..................................................................... 22 10.3 Output Ripple Voltage ....................................................................................... 23 10.4 Switching Ripple................................................................................................ 23 10.5 Line Frequency Ripple ...................................................................................... 24 10.6 Output Voltage Shutdown Profile ...................................................................... 26 11 Thermal Test......................................................................................................... 27 11.1 Thermal Performance........................................................................................ 27 12 Conducted EMI ..................................................................................................... 29 12.1 Conducted EMI Performance ............................................................................ 29 13 Revision History.................................................................................................... 30 1 2 3 4
Important Notes: Although this board is designed to satisfy safety isolation requirements, the engineering prototype has not been agency approved. Therefore, all testing should be performed using an isolated source to provide power to the prototype board. Design Reports contain a power supply design specification, schematic, bill of materials, and transformer documentation. Performance data and typical operation characteristics are included. Typically only a single prototype has been built.
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Page 2 of 31
DER-97
21.7 W PoE Adapter
September 12, 2005
1 Introduction
This document is an engineering report describing a Power over Ethernet (PoE) power supply utilizing TOP246P. The power supply delivers 21.7 W continuous from an input of 85 to 265 VAC. This document provides complete design information including specification, schematic, bill of material and transformer design and construction information. The document also provides performance information.
Figure 1 - Circuit Board - Top View
Figure 2 - Circuit Board - Bottom View
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DER-97
21.7 W PoE Adapter
September 12, 2005
2 Power Supply Specification
Description Input Voltage Output Output Voltage 1 Output Ripple Voltage 1 Output Current 1 Power Down Holdup 115 VAC 230 VAC Total Output Power Average Output Power Full Load Efficiency Environmental Conducted EMI Safety Ambient Temperature TAMB
Meets CISPR22B / EN55022B Designed to meet IEC950, UL1950 Class II
Symbol VIN
Min 85
Typ
Max 265
Units VAC
Comment
VOUT1 VRIPPLE1 IOUT1 TH(115VAC) TH(230VAC)
47.52 0 18 60
48
48.48 480 450
V mVp-p mA ms ms
1% 20 MHz bandwidth
POUT1
21.7 80
W %
0
40
o
C
Forced airflow
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DER-97
21.7 W PoE Adapter
September 12, 2005
3
Schematic
Figure 3 - Schematic
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DER-97
21.7 W PoE Adapter
September 12, 2005
4 Circuit Operation
4.1 General The power supply uses a TOP246P device (U2), with integrated MOSFET and controller, in an isolated flyback configuration. The circuit also uses the x-pin programmable current limit feature control the overload power of the power supply and also to minimize transformer size. 4.2 Description The input fuse F1 protects the supply against catastrophic failure. Thermistor RT1 limits the in-rush current during power-up. Diodes D5 - D8 implement a bridge rectifier to rectify the input mains voltage. Capacitor C22 attenuates the EMI generated by the input bridge diodes D5-D8. Inductor L1 is used to attenuate both differential and common mode EMI noise from the power supply. A large value is used to also prevent any noise filtering through from networks connector to the power supply output. Capacitor C2 forms part of the EMI solution by shunting EMI signals generated across the transformer T2. Capacitor C4 decouples the rectified input voltage providing a DC-bus. Resistor R14 programs the current limit of the TOPSwitch-GX (U2). Resistors R6 and R9 modified this current limit with input voltage, to maintain a relatively flat output overload profile. Diode D2, R2, C1 and R1 implement an RCD clamp circuit to limit the leakage inductance spike on the TOPSwitch-GX Drain pin. Diode D3 and C8 implement a bias voltage supply to provide operating power to the TOPSwitch-GX with integrated PWM, controller and main switching MOSFET. Capacitors C13 and C14 provide device decoupling with C14 also programming the startup and auto-restart period of the device. Resistor R13 provides feedback compensation in conjunction with C14. The inductance of transformer T2 provides the energy storage and conversion component of the circuit. Resistor R41 feeds current to an indicator LED U6, which is illuminated during normal operation. The 48 V output is rectified and filtered by diodes D1 and D4 and capacitors C5 with C7 provided output decoupling. Resistor R18 and C21 snub high frequency ringing on these diodes. Resistors R8 and R15 sense the output voltage providing the input signal for the TL431 (U3) reference. Resistor R41 provides DC bias current (approx. 1 mA) to the U3. Components R12 and C12 provide compensation for U3, to make sure that it's frequency response is limited only to low-frequency signals. Resistor R10 programs the highfrequency gain of the control loop and with opto-diode U5A transmits the feedback signal. Resistor R42 and C15 provide increase the high frequency gain of the feedback circuit to improve output ripple rejection. Zener diode VR1 is used due to the high 48 V output voltage and drops approximately 30 V, to bring the TL431 collector voltage comfortably within safe levels (i.e. less than 30 V). Opto-transistor U5B feeds the control signal back to the TOPSwitch-GX.
Page 6 of 31
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DER-97
21.7 W PoE Adapter
September 12, 2005
5 Bill of Materials
Item Qty. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 1 C1 1 C2 1 C4 1 C5 1 C7 1 C8 2 C12 C15 1 C13 1 C14 1 C21 1 C22 2 D1 D4 1 D2 1 D3 2 D5 D6 2 D7 D8 1 F1 1 J4 2 J5 J6 1 L1 1 L2 1 R1 1 R2 1 R6 1 R8 1 R9 1 R10 2 R12 R40 1 R13 Ref. Description 4.7 nF, 1 kV, Thru Hole, Disc Ceramic 2.2 nF, Ceramic, Y1 47 uF, 400 V, Electrolytic, Low ESR, 730 mOhm, (16 x 25) 180 uF, 63, Electrolytic, Low ESR, 145 mOhm, (10 x 20) 68 uF, 63, Electrolytic, Low ESR, 340 mOhm, (8 x 12) 10 uF, 50 V, Electrolytic, Gen. Purpose, (5 x 11) 1.0 uF, 50 V, Ceramic, Z5U 100 nF, 50 V, Ceramic, X7R 47 uF, 16 V, Electrolytic, Low ESR, 500 mOhm, (5 x 11.5) 100 pF, 1 kV, Disc Ceramic 47 nF, 275 VAC, Film, X2 Mfg Part Number 5GAD47 Mfg Vishay/Sprague
440LD22 Vishay KMX400VB47RM16X 25LL United Chemi-Con LXZ63VB181MJ20LL United Chemi-Con LXZ63VB68RMH15LL United Chemi-Con KME50VB10RM5X11 LL United Chemi-Con ECU-S1H105MEB ECU-S1H104KBB Panasonic Panasonic
LXZ16VB47RME11LL United Chemi-Con NIC Components NCD101K1KVY5F Corp ECQU2A473ML Panasonic Fairchild Vishay Vishay Vishay Vishay Wickman Kobiconn Amphenol Canada Panasonic Toko Yageo Yageo Yageo Yageo Yageo Yageo Yageo Yageo
100 V, 1 A, Schottky, DO-41 SB1100 1000 V, 1 A, Rectifier, Glass Passivated, 2 us, DO-41 1N4007GP 75 V, 300 mA, Fast Switching, DO-35 1N4148 600 V, 1 A, Ultrafast Recovery, 75 ns, DO41 UF4005 600 V, 1 A, Rectifier, DO-41 1 A, 250V, Slow, TR5 AC Input Receptacle and Accessory Plug, PCBM R/A, RJ45 Nonshielded, PCBM 19 mH, 0.5 A, Common Mode Choke 3.3 uH, 2.66 A 100 k, 5%, 1 W, Metal Oxide 47 R, 5%, 1/2 W, Carbon Film 3 M, 5%, 1/8 W, Carbon Film 182 k, 1%, 1/4 W, Metal Film 2.7 M, 5%, 1/8 W, Carbon Film 3.3 k, 5%, 1/8 W, Carbon Film 1 k, 5%, 1/8 W, Carbon Film 6.8 R, 5%, 1/8 W, Carbon Film 1N4005 3,721,100,041 161-R301SN13 RJHS-5080 ELF15N005A 822LY-3R3M RSF100JB-100K CFR-50JB-47R CFR-12JB-3M0 MFR-25FBF-182K CFR-12JB-2M7 CFR-12JB-3K3 CFR-12JB-1K0 CFR-12JB-6R8
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DER-97
21.7 W PoE Adapter
September 12, 2005
30 31 32 33 34 35 36 37 38 39 40 41
1 R14 1 R15 1 R18 1 R41 1 R42 1 RT1 1 T2 1 U2 1 U3 1 U5 1 U6 1 VR1 47 Total
9.09 k, 1%, 1/4 W, Metal Film 10 k, 1%, 1/4 W, Metal Film 10 R, 5%, 1/4 W, Carbon Film 2 k, 5%, 1/8 W, Carbon Film 330 R, 5%, 1/8 W, Carbon Film NTC Thermistor, 30 Ohms, 1.5 A Bobbin, EEL25.4, Horizontal, 10 pins
MFR-25FBF-9K09 MFR-25FBF-10K0 CFR-25JB-10R CFR-12JB-2K0 CFR-12JB-330R CL210 YW-236-03B
Yageo Yageo Yageo Yageo Yageo Thermometrics Yih-Hwa Enterprises Power Integrations Texas Instruments Isocom, Sharp Lumex Opto Microsemi
TOPSwitch-GX, TOP246P, DIP-8B TOP246P 2.495 V Shunt Regulator IC, 2%, 0 to 70C, TO-92 TL431CLP Opto coupler, 35 V, CTR 300-600%, 4-DIP ISP817D, PC817X4 LED, Green, 5 mm, 565 nm, 30 mcd 30 V, 5%, 500 mW, DO-35 SSL-LX5093GD 1N5256B
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DER-97
21.7 W PoE Adapter
September 12, 2005
6 Layout
Figure 4 - PC Board Layout
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DER-97
21.7 W PoE Adapter
September 12, 2005
7 Transformer Design Spreadsheet
ACDC_TOPSwitchGX_020 INPUT 105; Rev.2.5; Copyright Power Integrations 2005 ENTER APPLICATION VARIABLES VACMIN 85 VACMAX 265 fL 50 VO 48 PO 21.7 n 0.86 Z 0.44 VB 12 tC 2.66 CIN 47 ENTER TOPSWITCH-GX VARIABLES TOP-GX top246p Chosen Device KI ILIMITMIN ILIMITMAX Frequency (F)=132kHz, (H)=66kHz fS fSmin fSmax VOR VDS VD VDB KP 0.78 0.948 1.158 F 132000 124000 140000 90 2 1 0.7 0.68 Hertz Hertz Hertz Volts Volts Volts Volts Amps Amps INFO OUTPUT UNIT TOP_GX_FX_020105.xls: TOPSwitch-GX/FX Continuous/Discontinuous Flyback Transformer Design Spreadsheet Customer Maximum AC Input Voltage AC Mains Frequency Output Voltage (main) Output Power Efficiency Estimate Loss Allocation Factor Bias Voltage Bridge Rectifier Conduction Time Estimate Input Filter Capacitor
Volts Volts Hertz Volts Watts
Volts mSeconds uFarads
TOP246P
Power Out
Universal 26W
115 Doubled/230V 34W External Ilimit reduction factor (KI=1.0 for default ILIMIT, KI <1.0 for lower ILIMIT) Use 1% resistor in setting external ILIMIT. Assumes 0.85 derating at 100 degrees Celsius Use 1% resistor in setting external ILIMIT Full (F) frequency option - 132kHz TOPSwitch-GX Switching Frequency: Choose between 132 kHz and 66 kHz TOPSwitch-GX Minimum Switching Frequency TOPSwitch-GX Maximum Switching Frequency Reflected Output Voltage TOPSwitch on-state Drain to Source Voltage Output Winding Diode Forward Voltage Drop Bias Winding Diode Forward Voltage Drop Ripple to Peak Current Ratio (0.4 < KRP < 1.0 : 1.0< KDP<6.0)
ENTER TRANSFORMER CORE/CONSTRUCTION VARIABLES Core Type eel25 Core EEL25 Bobbin EEL25_B OBBIN AE 0.404 LE 7.34 AL 1420 BW 22.3 M 3 L NS DC INPUT VOLTAGE PARAMETERS VMIN VMAX CURRENT WAVEFORM SHAPE PARAMETERS DMAX IAVG IP IR IRMS 1 21
P/N: P/N: cm^2 cm nH/T^2 mm mm
PC40EE25.4/32/6.4-Z * Core Effective Cross Sectional Area Core Effective Path Length Ungapped Core Effective Inductance Bobbin Physical Winding Width Safety Margin Width (Half the Primary to Secondary Creepage Distance) Number of Primary Layers Number of Secondary Turns
81 375
Volts Volts
Minimum DC Input Voltage Maximum DC Input Voltage
0.53 0.31 0.89 0.60 0.45
Amps Amps Amps Amps
Maximum Duty Cycle Average Primary Current Peak Primary Current Primary Ripple Current Primary RMS Current
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DER-97
21.7 W PoE Adapter
September 12, 2005
TRANSFORMER PRIMARY DESIGN PARAMETERS LP NP NB ALG BM BP BAC ur LG BWE OD INS DIA AWG CM CMA
532 39 5 358 3027 3957 1029 2053 0.11 16.3 0.42 0.06 0.36 28 161 362
uHenries
nH/T^2 Gauss Gauss Gauss
mm mm mm mm mm AWG Cmils Cmils/Amp
Primary Inductance Primary Winding Number of Turns Bias Winding Number of Turns Gapped Core Effective Inductance Maximum Flux Density at PO, VMIN (BM<3000) Peak Flux Density (BP<4200) AC Flux Density for Core Loss Curves (0.5 X Peak to Peak) Relative Permeability of Ungapped Core Gap Length (Lg > 0.1 mm) Effective Bobbin Width Maximum Primary Wire Diameter including insulation Estimated Total Insulation Thickness (= 2 * film thickness) Bare conductor diameter Primary Wire Gauge (Rounded to next smaller standard AWG value) Bare conductor effective area in circular mils Primary Winding Current Capacity (200 < CMA < 500)
TRANSFORMER SECONDARY DESIGN PARAMETERS (SINGLE OUTPUT EQUIVALENT) Lumped parameters ISP 1.63 Amps Peak Secondary Current ISRMS 0.77 Amps Secondary RMS Current IO 0.45 Amps Power Supply Output Current IRIPPLE 0.62 Amps Output Capacitor RMS Ripple Current CMS AWGS DIAS ODS INSS VOLTAGE STRESS PARAMETERS VDRAIN PIVS PIVB 153 28 0.32 0.78 0.23 Cmils AWG mm mm mm Secondary Bare Conductor minimum circular mils Secondary Wire Gauge (Rounded up to next larger standard AWG value) Secondary Minimum Bare Conductor Diameter Secondary Maximum Outside Diameter for Triple Insulated Wire Maximum Secondary Insulation Wall Thickness
584 252 65
Volts Volts Volts
Maximum Drain Voltage Estimate (Includes Effect of Leakage Inductance) Output Rectifier Maximum Peak Inverse Voltage Bias Rectifier Maximum Peak Inverse Voltage
TRANSFORMER SECONDARY DESIGN PARAMETERS (MULTIPLE OUTPUTS) 1st output VO1 48 Volts IO1 0.452083 Amps 3333 PO1 21.70 Watts VD1 1 Volts NS1 21.00 ISRMS1 0.766 Amps IRIPPLE1 0.62 Amps PIVS1 252 Volts
Output Voltage Output DC Current Output Power Output Diode Forward Voltage Drop Output Winding Number of Turns Output Winding RMS Current Output Capacitor RMS Ripple Current Output Rectifier Maximum Peak Inverse Voltage Output Winding Bare Conductor minimum circular mils
CMS1
153
Cmils
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DER-97
AWGS1 DIAS1 ODS1
21.7 W PoE Adapter
28 0.32 0.78 AWG mm mm
September 12, 2005
Wire Gauge (Rounded up to next larger standard AWG value) Minimum Bare Conductor Diameter Maximum Outside Diameter for Triple Insulated Wire
2nd output VO2 IO2 PO2 VD2 NS2 ISRMS2 IRIPPLE2 PIVS2
0.00 0.00 0.000 0.00 0
Volts Amps Watts Volts Amps Amps Volts
Output Voltage Output DC Current Output Power Output Diode Forward Voltage Drop Output Winding Number of Turns Output Winding RMS Current Output Capacitor RMS Ripple Current Output Rectifier Maximum Peak Inverse Voltage Output Winding Bare Conductor minimum circular mils Wire Gauge (Rounded up to next larger standard AWG value) Minimum Bare Conductor Diameter Maximum Outside Diameter for Triple Insulated Wire
CMS2 AWGS2 DIAS2 ODS2 N/A N/A N/A
0
Cmils AWG mm mm
3rd output VO3 IO3 PO3 VD3 NS3 ISRMS3 IRIPPLE3 PIVS3
0.00 0.00 0.000 0.00 0
Volts Amps Watts Volts Amps Amps Volts
Output Voltage Output DC Current Output Power Output Diode Forward Voltage Drop Output Winding Number of Turns Output Winding RMS Current Output Capacitor RMS Ripple Current Output Rectifier Maximum Peak Inverse Voltage Output Winding Bare Conductor minimum circular mils Wire Gauge (Rounded up to next larger standard AWG value) Minimum Bare Conductor Diameter Maximum Outside Diameter for Triple Insulated Wire Total Power for Multi-output section If negative output exists enter Output number; eg: If VO2 is negative output, enter 2
CMS3 AWGS3 DIAS3 ODS3 N/A N/A N/A
0
Cmils AWG mm mm
Total power Negative Output N/A
21.7
Watts
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DER-97
21.7 W PoE Adapter
September 12, 2005
8 Transformer Specification
Transformer Construction
Electrical Diagram
Winding Order
Core Information Core Type Core Material Estimated Gap length, mm Gapped Effective Inductance, nH/t^2 Primary Inductance, uH
eel25 NC-2H or Equivalent 0.110 358 532
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Page 13 of 31
DER-97
21.7 W PoE Adapter
September 12, 2005
Bobbin Information (Manual Input) Bobbin Reference Bobbin Orientation Number of Primary pins Number of Secondary pins Margin on Left, mm Margin on Right, mm Primary Winding (Manual Input) Parameter Number of Turns Wire Size, AWG Filar Layers Start Pin(s) Termination Pin(s) BIAS Winding (Manual Input) Parameter Number of Turns Wire Size, AWG Filar Layers Start Pin(s) Termination Pin(s) Shield Information Parameter Number of Turns Wire Size, AWG Filar Layers Start Pin(s) Termination Pin(s)
Generic, 5 pri. + 5 sec. Horizontal 5 5 3.0 3.0
Section 1 39 28 1 0.88 5 3
Value 6 28 1 0.13 1 2
Primary 20 28 2 0.90 NC 3,4 22 28 2 0.99 3,4 NC
Cancellation
Secondary Winding (Manual Input) Parameter Spec Voltage, V Spec Current, A Actual Voltage, V Number of Turns Wire Size, AWG Filar Layers Start Pin(s) Termination Pin(s)
Output 1 48.00 0.45 48.00 21 28 2 0.94 6 7
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DER-97
21.7 W PoE Adapter
September 12, 2005
Winding Instruction Use 3.0 mm margin (item [3]) on the left side. Use 3.0 mm margin (item [3]) on the right side. Cancellation Shield Winding Start on pin(s) 3,4 and wind 22 turns (x 2 filar) of item [6]. in exactly 1 layer. Leave this end of cancellation shield winding not connected. Bend the end 90 deg and cut the wire in the middle of the bobbin. Add 1 layer of tape, item [4], to secure the winding in place. Primary Winding Start on pin(s) 5 and wind 39 turns of item [6] in 1.00 layer(s) from left to right. Finish winding on pin(s) 3. Add 1 layer of tape, item [4], for insulation. Bias Winding Start on pin(s) 1 and wind 6.0 turns (x 1 filar) of item [6]. Spread the winding evenly across entire bobbin. Finish on pin(s) 2. Add 1 layer of tape, item [4], for insulation. Primary Balanced Shield Winding Start on any (temp) pin on the secondary side and wind 20 turns (x 2 filar) of item [6]. Spread the winding evenly across entire bobbin. Finish this winding on pin(s) 3,4. Cut out wire connected to temp pin on secondary side. Leave this end of primary shield winding not connected. Bend the end 90 deg and cut the wire in the middle of the bobbin. Add 3 layers of tape, item [4], for insulation. Secondary Winding Start on pin(s) 6 and wind 21 turns (x 2 filar) of item [6]. Spread the winding evenly across entire bobbin. Finish on pin(s) 7. Add 2 layers of tape, item [4], for insulation. Core Assembly Assemble and secure core halves. Item [1]. Varnish Dip varnish uniformly in item [5]. Do not vacuum impregnate.
Comments 1. Pins 8 through 10 on the secondary side are not connected to any electrical node. 2. Pins 3 and 4 should be electrically connected Materials Item [1] [2] [3] [4] [5] [6] Description Core: eel25, NC-2H or Equivalent, gapped for ALG of 358 nH/t^2 Bobbin: Generic, 5 pri. + 5 sec. Tape: Polyester web 3.0 mm wide Barrier Tape: Polyester film 22.30 mm wide Varnish Magnet Wire: 28 AWG, Solderable Double Coated
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DER-97
21.7 W PoE Adapter
September 12, 2005
Electrical Test Specifications Parameter Condition Electrical Strength, VAC 60 Hz 1 minute, from pins 3 - 5 to pins 6 - 10. Nominal Primary Inductance, Measured at 1 V pk-pk, uH typical switching frequency, between pin 3 to pin 5, with all other Windings open. Primary Leakage, uH Measured between Pin 3 to Pin 5, with all other Windings shorted.
Spec 3000 586 +/- 10%
17.57 Goal
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DER-97
21.7 W PoE Adapter
September 12, 2005
9 Performance
9.1 Efficiency
E fficiency vs Line/Load
90%
80% Efficiency (%)
70% 85 VAC 60% 115 VAC 230 VAC 265 VAC 50%
40% 0 5 10 15 Pout (W) 20 25
Figure 5 - Efficiency vs. Input Voltage and Output Load, Room Temperature
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DER-97 9.2 Regulation vs. Load
21.7 W PoE Adapter
September 12, 2005
R e g u la tio n v s L o a d
101. 0%
85 V A C 1 15 V A C
100. 5%
2 30 V A C 2 65 V A C
Regulation (%)
100. 0%
99. 5%
99. 0% 0 5 10 15 20 25
P o u t (W )
Figure 6 - Output Regulation vs. Output Load, Room Temperature
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DER-97 9.3 Regulation vs. Line
21.7 W PoE Adapter
September 12, 2005
Regulation vs Line
101.0%
Regulation (%)
100.5%
Full Load No Load
100.0%
99.5%
99.0% 50 100 150 200 250 300
Vin (VAC)
Figure 7 - Output Regulation vs. Input Line Voltage, Room Temperature
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DER-97
21.7 W PoE Adapter
September 12, 2005
9.4 Raw Performance Data Load was applied at the end of a 1 ft long Ethernet cable connected to the connector J6. The load was applied using an electronic load. The output voltage was measurement at the end of this cable.
Vin (DC) 86.79 86.42 86.8 86.39 85.95 85.46 85.22 115.83 115.74 115.13 114.31 113.9 113.81 113.54 230.56 230.1 230 229.41 229.71 229.39 228.87 265 265.46 265.67 264.92 264.66 264.4 263.88 Pin (A) 0.828 3.802 6.432 12.573 18.42 24.24 27.03 0.7734 3.2452 6.629 12.346 17.985 23.794 26.831 0.9012 3.878 6.78 12.405 18.825 23.478 26.994 0.9906 4.317 7.205 12.731 19.287 24.105 26.931 Max Min Delta Vout1 (V) 48 48 48 48 48 47.9 47.9 48 48 48 48 48 47.9 47.9 48 48 48 48 48 47.9 47.9 48 48 48 48 48 47.9 47.9 48 47.9 0.1 Iout1 (A) 0 0.05 0.1 0.2 0.3 0.4 0.45 0 0.05 0.1 0.2 0.3 0.4 0.45 0 0.05 0.1 0.2 0.3 0.4 0.45 0 0.05 0.1 0.2 0.3 0.4 0.45 0.0% -0.2% 0.2% %Vout1 (%) 100.0% 100.0% 100.0% 100.0% 100.0% 99.8% 99.8% 100.0% 100.0% 100.0% 100.0% 100.0% 99.8% 99.8% 100.0% 100.0% 100.0% 100.0% 100.0% 99.8% 99.8% 100.0% 100.0% 100.0% 100.0% 100.0% 99.8% 99.8% 100.0% 99.8% 0.2% Iin (A) 0.010 0.044 0.074 0.146 0.214 0.284 0.317 0.007 0.028 0.058 0.108 0.158 0.209 0.236 0.004 0.017 0.029 0.054 0.082 0.102 0.118 0.004 0.016 0.027 0.048 0.073 0.091 0.102 0.317 0.004 0.313 Eff (%) 0.0% 63.1% 74.6% 76.4% 78.2% 79.0% 79.7% 0.0% 74.0% 72.4% 77.8% 80.1% 80.5% 80.3% 0.0% 61.9% 70.8% 77.4% 76.5% 81.6% 79.9% 0.0% 55.6% 66.6% 75.4% 74.7% 79.5% 80.0% 81.6% 0.0% 81.6% Iin (A) 0.000 0.001 0.001 0.002 0.002 0.003 0.004 0.000 0.000 0.001 0.001 0.001 0.002 0.002 0.000 0.000 0.000 0.000 0.000 0.000 0.001 0.000 0.000 0.000 0.000 0.000 0.000 0.000 Pout (W) 0.0 2.4 4.8 9.6 14.4 19.2 21.6 0.0 2.4 4.8 9.6 14.4 19.2 21.6 0.0 2.4 4.8 9.6 14.4 19.2 21.6 0.0 2.4 4.8 9.6 14.4 19.2 21.6 21.6 2.4
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DER-97
21.7 W PoE Adapter
September 12, 2005
10 Waveforms
10.1 Drain Current and Voltage
Figure 8 - 85 VAC, full load Upper Ch3: Drain Voltage 100 V, Lowr Ch4: Drain Current 0.5 A / Div, 2 s / div
Figure 9 - 115 VAC, full load Upper Ch3: Drain Voltage 100 V, Lowr Ch4: Drain Current 0.5 A / Div, 2 s / div
Figure 10 - 230 VAC, full load Upper Ch3: Drain Voltage 200 V, Lowr Ch4: Drain Current 0.5 A / Div, 2 s / div
Figure 11 - 265 VAC, full load Upper Ch3: Drain Voltage 200 V, Lowr Ch4: Drain Current 0.5 A / Div, 2 s / div
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DER-97
21.7 W PoE Adapter
September 12, 2005
10.2 Output Transient Load Response
Figure 12 - 115 VAC, (48 V 0.23 A to 0.45 A step) 48 V Output Voltage 200 mV / Div, 5 ms / div
Figure 13 - 230 VAC, (48 V 0.23 A to 0.45 A step) 48 V Output Voltage 200 mV / Div, 5 ms / div
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DER-97
21.7 W PoE Adapter
September 12, 2005
10.3 Output Ripple Voltage It can be seen from the waveforms below that the power supply comfortably meets the output ripple specifications. This is possible even without the need for an output inductor. Measurements made at the end of an Ethernet cable connected to J6. The voltage measurement included a 0.1 uF ceramic capacitor in parallel with a 1 uF / 50 V electrolytic capacitor, at point of measurement (end of the cable). 10.4 Switching Ripple
Figure 14 - 85 VAC, Full Load CH1: 48 V Output Ripple, 200 mV, CH3: Drain Voltage, 200 V, 5 s / div
Figure 15 - 115 VAC, Full Load CH1: 48 V Output Ripple, 200 mV, CH3: Drain Voltage, 200 V, 5 s / div
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DER-97
21.7 W PoE Adapter
September 12, 2005
Figure 16 - 230 VAC, Full Load CH1: 48 V Output Ripple, 200 mV, CH3: Drain Voltage, 200 V, 5 s / div
Figure 17 - 265 VAC, Full Load CH1: 48 V Output Ripple, 200 mV, CH3: Drain Voltage, 200 V, 5 s / div
10.5 Line Frequency Ripple
Figure 18 - 85 VAC, Full Load CH1: 48 V Output Ripple, 200 mV, CH3: Drain Voltage, 200 V, 5 ms / div
Figure 19 - 115 VAC, Full Load CH1: 48 V Output Ripple, 200 mV, CH3: Drain Voltage, 200 V, 5 ms / div
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DER-97
21.7 W PoE Adapter
September 12, 2005
Figure 20 - 230 VAC, Full Load CH1: 48 V Output Ripple, 200 mV, CH3: Drain Voltage, 200 V, 5 ms / div
Figure 21 - 265 VAC, Full Load CH1: 48 V Output Ripple, 200 mV, CH3: Drain Voltage, 200 V, 5 ms / div
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DER-97
21.7 W PoE Adapter
September 12, 2005
10.6 Output Voltage Shutdown Profile The results below show that the power supply comfortably meets the power-supply holdup requirements of the specification.
Figure 22 - Shutdown Profile at Full Load, 120 VAC Upper Ch1: 48 V output, 10 V / div, Lower Ch3: Bus Voltage 100 V / div, 20 ms / div.
Figure 23 - Shutdown Profile at Full Load, 120 VAC Upper Ch1: 48 V output, 10 V / div, Lower Ch3: Bus Voltage 100 V / div, 20 ms / div.
Page 26 of 31
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DER-97
21.7 W PoE Adapter
September 12, 2005
11 Thermal Test
The thermal measurements were made at 85 VAC (which corresponds to the worst case efficiency of the power supply). Ambient temperature of the oven was 40'C. The power supply was connected to an electronic load (external to the chamber). A cardboard box was used around the power supply to prevent significant airflow. The whole setup was saturated at 40'C for an hour before beginning measurements.
11.1 Thermal Performance
Temperature Vs Time
140 120
Temperature ('C)
100 80 60 40 20 0 1 10 100
Ch2 - Amb1 Ch3 - D1 Ch4 - TOP246P Ch5 - Case
Time (min)
Figure 24 - Thermal Performance of Key Power Supply Components
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DER-97
21.7 W PoE Adapter
September 12, 2005
Delta Time 0.1 0.9 1 2 4 8 16 32 64 128
Ch2 Amb1 40 40 40 40 40 41 42 43 43 43
Ch3 D1 40 52 57 61 65 72 82 83 85 85
Ch4 Ch5 TOP246P CASE 40 40 55 40 59 41 70 43 73 45 87 51 99 60 105 64 107 65 107 65
Figure 25 - Raw Test Data
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DER-97
21.7 W PoE Adapter
September 12, 2005
12 Conducted EMI
The EMI was tested with and without the output connected to earth-ground. Load was connected through an Ethernet cable to a resistive load (100 ohms). 12.1 Conducted EMI Performance
Figure 26 - 115 VAC - N1 - grounded output - fullload
Figure 27 - 115 VAC - L1 - grounded output - fullload
Figure 28 - 230 VAC - N1 - grounded output - fullload
Figure 29 - 230 VAC - L1 - grounded output - fullload
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DER-97
21.7 W PoE Adapter
September 12, 2005
13 Revision History
Date September 12, 2005 Author RM Revision 1.0 Description & changes First Release Reviewed VC / AM
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DER-97
21.7 W PoE Adapter
September 12, 2005
For the latest updates, visit our Web site: www.powerint.com Power Integrations may make changes to its products at any time. Power Integrations has no liability arising from your use of any information, device or circuit described herein nor does it convey any license under its patent rights or the rights of others. POWER INTEGRATIONS MAKES NO WARRANTIES HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. PATENT INFORMATION The products and applications illustrated herein (including circuits external to the products and transformer construction) may be covered by one or more U.S. and foreign patents or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations' patents may be found at www.powerint.com. The PI Logo, TOPSwitch, TinySwitch, LinkSwitch, and EcoSmart are registered trademarks of Power Integrations. PI Expert and DPA-Switch are trademarks of Power Integrations. (c) Copyright 2004, Power Integrations.
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ER or EPR template - Rev 3.6 - Single sided
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