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EL7520, EL7520A
Data Sheet July 12, 2005 FN7318.0
4-Channel DC/DC Controller
EL7520 and EL7520A are 4-channel DC/DC controllers that provide a complete power supply system for TFT-LCD applications. They consist of a 1MHz PWM boost controller, which generates the main voltage for the column driver, and three LDO controllers for VON, VOFF, and VLOGIC supplies. They also include integrated start-up sequence and start-up delay control. EL7520 and EL7520A operate from 3V to 5.5V. The boost controller can drive a wide range of output current depending on the external FET. It can be programmed to operate in either P-mode for fast transient response or PImode for improved load regulation. The EL7520 and EL7520A also integrate fault protection for all four output channels. When a fault is detected, the device is latched off until either the input supply voltage or enable is cycled. Therefore, they are ideal to use in any size of TFT-LCD panels. The EL7520 and EL7520A are available in a 20 Ld 4x4 QFN package with maximum height of 0.9mm and is specified for operation of the -40C to +85C temperature range.
Features
* Complete TFT-LCD supply controller - 1MHz PWM boost controller - VON LDO controller - VOFF LDO controller - Logic supply LDO controller * Integrated start-up sequence for VLOGIC/VBOOST, VOFF, VON or VLOGIC, VOFF, VBOOST, VON - VLOGIC permanently enabled in 'A version (EL7520A) * Programmable sequence delay * In-rush current control * Fully fault protected * Thermal shutdown * Internal soft-start * 3V to 5.5V VDD * 20 Ld 4x4 QFN package * Low cost * Pb-Free plus anneal available (RoHS compliant)
Ordering Information
PART NUMBER (NOTE) EL7520ILZ EL7520ILZ-T7 EL7520ILZ-T13 EL7520AILZ EL7520AILZ-T7 EL7520AILZ-T13 PACKAGE (Pb-FREE) 20 Ld 4x4 QFN 20 Ld 4x4 QFN 20 Ld 4x4 QFN 20 Ld 4x4 QFN 20 Ld 4x4 QFN 20 Ld 4x4 QFN TAPE & REEL 7" 13" 7" 13" PKG. DWG. # MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046
Applications
* LCD monitors (15"+) * LCD-TV (up to 40"+) * Notebook displays (up to 16") * Industrial/medical LCD displays
Pinout
EL7520 AND EL7520A (20 LD 4X4 QFN) TOP VIEW
16 DRVP 15 FBP 14 DRVL THERMAL PAD 13 FBL 12 DRVN 11 FBN DELB 6 SGND 7 VREF 10 FBB 8 CINT 9 19 VDDP 18 VDD 20 PG 17 EN
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
CDLY 1 DRVB 2 PGND 3 ISAD 4 ISIN 5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL7520, EL7520A
Absolute Maximum Ratings (TA = 25C)
VDELB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25V VDRVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V VDRVN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20V VDDP, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) JA (C/W) JC (C/W) QFN Package. . . . . . . . . . . . . . . . . . . . 40 7.5 VDRVL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Maximum Continuous Junction Temperature . . . . . . . . . . . . . 125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER SUPPLY VS IS Supply Voltage
VDD = 5V, VBOOST = 11V, ILOAD = 40mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, over temperature from 40C to 85C, unless otherwise specified. CONDITION MIN TYP MAX UNIT
DESCRIPTION
3 Enabled, LX not switching Disabled, EL7520 Disabled, EL7520A 1.6 5 640 900 1000
5.5 2.5 30 800 1100
V mA A A kHz
Quiescent Current
FOSC BOOST VREF CREF VFBB VF_FBB DMAX Eff I(VREF) VBOOST/ VIN VBOOST/ IBOOST VBOOST/ IBOOST VCINT_T VON LDO VFBP VF_FBP IFBP GMP
Oscillator Frequency
Reference Voltage
TA = 25C
1.19 1.187
1.215 1.215 100
1.235 1.238
V V nF
VREF Capacitor Feedback Reference Voltage TA = 25C VFBB falling 85 Test with 24m RDS(ON) MOSFET, ILOAD = 400mA PI mode, VFBB = 1.35V CINT = 2.2nF, IOUT = 200mA VIN = 3V to 5.5V CINT pin strapped to VDD IOUT = 10mA to 200mA 1.192 1.188 FBB Fault Trip Point Maximum Duty Cycle Boost Efficiency Feedback Input Bias Current Line Regulation Load Regulation - "P" Mode Load Regulation - "PI" Mode CINT Pl Mode Select Threshold
1.205 1.205 1
1.218 1.222
V V V %
90 50 0.05 3 0.1 4.7 4.8 500
% nA %/V % % V
FBP Regulation Voltage
IDRVP = 0.2mA, TA = 25C IDRVP = 0.2mA VFBP falling VFBP = 1.35V VDRVP = 25V, IDRVP = 0.2 to 2mA
1.181 1.177 0.95 -250
1.211 1.211 1
1.229 1.233 1.05 250
V V V nA mS
FBP Fault Trip Point FBP Input Bias Current FBP Effective Transconductance
50
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EL7520, EL7520A
Electrical Specifications
PARAMETER VON/I(VON) IDRVP IL_DRVP VOFF LDO VFBN VF_FBN IFBN GMN VOFF/ I(VOFF) IDRVN IL_DRVN VLOGIC LDO VFBL VF_FBL IFBL GML VLOGIC/ I(VLOGIC) IDRVL IL_DRVL SEQUENCING tON tSS tDEL1 tDEL2 tDEL3 IDELB CDEL TFAULT OT IPG LOGIC VHI VLO ILOW IHIGH Logic High Threshold Logic Low Threshold Logic Low bias Current Logic High bias Current -1 12 0.1 18 2.2 0.8 1 24 V V A A Turn On Delay Soft-start Time Delay Between AVDD and VOFF Delay Between VON and VOFF Delay Between VOFF and Delayed VBOOST DELB Pull-down Current CDLY = 0.1F CDLY = 0.1F CDLY = 0.1F CDLY = 0.1F CDLY = 0.1F VDELB > 0.6V VDELB < 0.6V Delay Capacitor FAULT DETECTION Fault Time Out Over-temperature Threshold PG Pull-down Current VPG > 0.6V VPG < 0.6V CDLY = 0.1F 50 140 15 1.7 ms C A mA 30 2 10 17 10 50 1.4 100 ms ms ms ms ms A mA nF FBL Regulation Voltage IDRVL = 1mA, TA = 25C IDRVL = 1mA FBL Fault Trip Point FBL Input Bias Current FBL Effective Transconductance VLOGIC Load Regulation DRVL Sink Current DRVL Leakage Current VFBL falling VFBL = 1.25V VDRVL = 2.5V, IDRVP = 1mA to 8mA I(VLOGIC) = 0mA to 500mA VFBL = 1.1V, VDRVL = 2.5V VFBL = 1.5V, VDRVL = 5.5V 5 1.176 1.174 0.90 -500 200 -0.5 16 0.1 5 1.2 1.2 1 1.224 1.226 1.05 500 V V V nA mS % mA A FBN Regulation Voltage IDRVN = 0.2mA, TA = 25C IDRVN = 0.2mA FBN Fault Trip Point FBN Input Bias Current FBN Effective Transconductance VOFF Load Regulation DRVN Source Current DRVN Leakage Current VFBN falling VFBN = 1.25V VDRVN = -6V, IDRVN = 0.2mA to 2mA I(VOFF) = 0mA to 20mA VFBN = 0.3V, VDRVN = -6V VFBN = 0V, VDRVN = -20V 2 0.173 0.171 0.38 -250 50 -0.15 4 0.1 5 0.203 0.203 0.4 0.233 0.235 0.48 250 V V V nA mS % mA A VDD = 5V, VBOOST = 11V, ILOAD = 40mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, over temperature from 40C to 85C, unless otherwise specified. (Continued) DESCRIPTION VON Load Regulation DRVP Sink Current DRVP Leakage Current CONDITION I(VON) = 0mA to 20mA VFBP = 1.1V, VDRVP = 25V VFBL = 1.5V, VDRVL = 35V 2 MIN TYP -0.5 4 0.1 5 MAX UNIT % mA A
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FN7318.0 July 12, 2005
EL7520, EL7520A Typical Performance Curves
100 VIN = 5V EFFICIENCY (%) EFFICIENCY (%) 90 VIN = 3V 80 90 VIN = 3V 80 100 VIN = 5V
70
70
60 0 500 1000 IOUT (mA) 1500
60
0
200
400
600 IOUT (mA)
800
1000
1200
FIGURE 1. VBOOST EFFICIENCY vs IOUT (PI MODE)
FIGURE 2. VBOOST EFFICIENCY vs IOUT (P MODE)
0 P MODE LINE REGULATION (%) -0.5 -1
0 LOAD REGULATION (%) -0.005 -0.01 -0.015
0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 0
VIN = 3V
VIN = 5V
-1.5 -0.02 -2 PI MODE -2.5 0 1 2 3 VIN (V) 4 5 6 -0.03 -0.025
500 IOUT (mA)
1000
1500
FIGURE 3. VBOOST LINE REGULATION
FIGURE 4. VBOOST LOAD REGULATION (PI MODE)
0 LOAD REGULATION (%) -1 -2 VIN = 5V -3 -4 -5 -6 0 200 400 600 IOUT (mA) 800 1000 1200 VIN = 3V LOAD REGULATION (%)
0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6
0
20
40 IOUT (mA)
60
80
FIGURE 5. VBOOST LOAD REGULATION (P MODE)
FIGURE 6. VON LOAD REGULATION
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EL7520, EL7520A Typical Performance Curves
0 LOAD REGULATION (%) LOAD REGULATION (%) -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 0 20 40 60 80 100
(Continued)
0 -0.2 -0.4 -0.6 -0.8 -1 -1.2
0
100
200
300
400
500
600
700
IOUT (mA)
IOUT (mA)
FIGURE 7. VOFF LOAD REGULATION
FIGURE 8. VLOGIC LOAD REGULATION
VCDLY
VCDLY
EN VLOGIC
VBOOST VLOGIC
VREF
CDLY=0.1F
VREF
CDLY=0.1F
TIME (20ms/DIV)
TIME (20ms/DIV)
FIGURE 9. EL7520 START-UP SEQUENCE
FIGURE 10. EL7520 START-UP SEQUENCE
VBOOST VLOGIC VOFF
VBOOST-DELAY VLOGIC VOFF
VON
CDLY=0.1F
VON
CDLY=0.1F
TIME (10ms/DIV)
TIME (20ms/DIV)
FIGURE 11. EL7520 START-UP SEQUENCE
FIGURE 12. EL7520 START-UP SEQUENCE
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EL7520, EL7520A Typical Performance Curves
(Continued)
VCDLY EN VLOGIC VREF CDLY=0.1F
VCDLY VBOOST VLOGIC VREF CDLY=0.1F
TIME (20ms/DIV)
TIME (20ms/DIV)
FIGURE 13. EL7520A START-UP SEQUENCE
FIGURE 14. EL7520A START-UP SEQUENCE
VBOOST
VBOOST-DELAY
VLOGIC VOFF VON CDLY=0.1F
VLOGIC VOFF VON CDLY=0.1F
TIME (20ms/DIV)
TIME (20ms/DIV)
FIGURE 15. EL7520A START-UP SEQUENCE
FIGURE 16. EL7520A START-UP SEQUENCE
0.5s/DIV
FIGURE 17. LX WAVEFORM-DISCONTINUOUS MODE
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EL7520, EL7520A Typical Performance Curves
(Continued)
0.5s/DIV
20mV/DIV
FIGURE 18. LX WAVEFORM-CONTINUOUS MODE
FIGURE 19. VBOOST OUTPUT VOLTAGE RIPPLE
CH1=VBOOST, 100mV/DIV CH4=LOAD CURRENT, 200mA/DIV
CH1=VLOGIC, 20mV/DIV CH4=LOAD CURRENT, 100mA/DIV
0.2ms/DIV
50s/DIV
FIGURE 20. VBOOST TRANSIENT RESPONSE
FIGURE 21. VLOGIC TRANSIENT RESPONSE
CH1=VON, 100mV/DIV CH4=LOAD CURRENT, 50mA/DIV
CH1=VOFF, 50mV/DIV CH4=LOAD CURRENT, 50mA/DIV
50s/DIV
50s/DIV
FIGURE 22. VON TRANSIENT RESPONSE
FIGURE 23. VOFF TRANSIENT RESPONSE
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FN7318.0 July 12, 2005
EL7520, EL7520A Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN NAME CDLY DRVB PGND ISAD ISIN DELB SGND FBB CINT VREF FBN DRVN FBL DRVL FBP DRVP EN VDD VDDP PG FUNCTION DESCRIPTION With a capacitor connected from this pin to GND sets the delay time for start-up sequence and sets the fault timeout time Gate driver output for the external N channel switch; the pulse voltage follows the input voltage Power GND With a resistor connected from this pin to GND sets the current limit of the external N channel FET Sense the drain voltage of the external N channel FET and connected to the internal current limit comparator Active low control output for optional delay control for external VBOOST P channel FET; when fault is detected, this pin goes to high Low noise signal ground Boost regulator voltage feedback input pin; regulates to 1.2V nominal VBOOST integrator output, connect 2.2nF to analog GND for PI mode or connect to VREF for P mode operation Bandgap voltage bypass terminal; bypass with a 0.1F to analog GND; can be used as charge pump reference Negative LDO voltage feedback input pin; regulates to 0.2V nominal Negative LDO base drive; open drain of an internal P channel MOSFET Logic LDO voltage feedback input pin; regulates to 1.2V nominal Logic LDO base drive; open drain of an internal N channel MOSFET Positive LDO voltage feedback input pin; regulates to 1.2V nominal Positive LDO base drive; open drain of an internal N channel MOSFET Enable pin for the chip; high enable; low disabled Positive supply for all internal circuitry except DRVB Positive supply for external N channel FET gate drive (DRVB) Output gate drive of the external fault protection P channel FET; when chip is disabled or when a fault has been detected, this pin is high
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FN7318.0 July 12, 2005
EL7520, EL7520A Typical Application
LX Q1 R0 500k C0 NODE 1 1000pF C1 L1 6.8H D1 C3 10F Q3 62.5K R2 R1 7.5K R9 C2 1M 10F C16 0.01F R8 10K C9 0.1F
VIN
10Fx2 Q2 PG ISIN DRVB FBB R20 200K C23 2.2nF R13
12V VBOOST
C10 0.1F R6 10 C6
C7 0.1F
VDDP
CDELAY DELB ISAD CINT VDD 4.7F R7 VREF 0.1F 10K 0.1F C22 EN VREF DRVP FBP 20K
LX C13 0.1F C11 0.1F
7K Q11 R12 230K R11 R23 3K DRVL DRVN FBN 20K SGND PGND R22 104K R21
R16 20K
C14 0.1F
D12
C12 0.1F 0.1F LX
D11 20V VON
C41 NODE 1
C15 1F
C24
R43 Q31 VLGC 2.5V C31 10F 500 R42 21.7K R41 FBL 20K
Q21
C25 0.1F
D21 -8V VOFF
C20 4.7F
VREF
Applications Information
The EL7520 and EL7520A provide a multiple output power supply solution for TFT-LCD applications. The system consists of a high efficiency boost controller and three low cost linear-regulator controllers (VON, VOFF, and VLOGIC). The block diagram of the whole part is shown in Figure 24. Table 1 lists the recommended components.
TABLE 1. RECOMMENDED COMPONENTS DESIGNATION C1, C2, C3, C31 C20 C15 D1 D11, D12, D21 L1 DESCRIPTION 10F, 16V, X7R ceramic capacitor (1206) TDK C3216X7R1C106M 4.7F, 16V X5R ceramic capacitor (1206) TDK C3216X5R1A475K 1F, 25V X7R ceramic capacitor (1206) TDK C3216X7R1E105K 1A 20V low leakage schottky rectifier (CASE 457-04) ON SEMI MBRM120ET3 200mA 30V schottky barrier diode (SOT-23) Fairchild BAT54S 6.8mH 1.3A inductor TDK SLF6025T-6R8M1R3-PF
TABLE 1. RECOMMENDED COMPONENTS (Continued) DESIGNATION Q1 DESCRIPTION -2.4 -20V P-channel 1.8V specified PowerTrench MOSFET (SuperSOT-3) Fairchild FDN304P 6.3A 30V single N-channel logic level PowerTrench MOSFET (SOT-23) Fairchild FDC655AN -2A -30V single P-channel logic level PowerTrench MOSFET (SuperSOT-3) Fairchild FDN360P 200mA 40V PNP amplifier (SOT-23) Fairchild MMBT3906 200mA 40V NPN amplifier (SOT-23) Fairchild MMBT3904 1A 30V PNP low saturation amplifier (SOT-23) Fairchild FMMT549
Q2
Q3
Q11 Q21 Q31
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FN7318.0 July 12, 2005
EL7520, EL7520A
VREF
REFERENCE GENERATOR
OSCILLATOR OSC LX
SLOPE COMPENSATION
FBB GM AMPLIFIER CINT VOLTAGE AMPLIFIER
PWM LOGIC CONTROLLER
BUFFER
DRVB
ISIN
CURRENT AMPLIFIER UVLO COMPARATOR CURRENT LIMIT COMPARATOR EN THERMAL SHUTDOWN UVLO COMPARATOR SS DRVN BUFFER FBN 0.4V UVLO COMPARATOR UVLO COMPARATOR + 0.2V VREF SS + SHUTDOWN & STARTUP CONTROL VREF
CURRENT LIMIT REF GENERATOR
ISAD
SS + BUFFER FBP DRVP
DRVL BUFFER
FBL
FIGURE 24. BLOCK DIAGRAM
Boost Converter
The main boost converter is a current mode PWM controller operating at a fixed frequency. The 1MHz switching frequency enables the use of low profile inductor and multilayer ceramic capacitors, which results in a compact, low-cost power system for LCD panel design. The boost converter can operate in continuous or discontinuous inductor current mode. The EL7520 and EL7520A are designed for continuous current mode, but they can also operate in discontinuous current mode at light load. In continuous current mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. The voltage conversion ratio in continuous current mode is given by:
V BOOST 1 ----------------------- = -----------1-D V IN
Figure 25 shows the function diagram of the boost controller. It uses a summing amplifier architecture consisting of GM stages for voltage feedback, current feedback and slope compensation. A comparator looks at the peak inductor current cycle by cycle and terminates the PWM cycle if the current limit is reached. An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 60k is recommended. The boost converter output voltage is determined by the following equation:
R1 + R2 V BOOST = -------------------- x V REF R1
Where D is the duty cycle of switching MOSFET. 10
FN7318.0 July 12, 2005
EL7520, EL7520A
VREF
REFERENCE GENERATOR
VIN OSCILLATOR OSC VBOOST
SLOPE COMPENSATION
VOLTAGE AMPLIFIER
PWM LOGIC CONTROLLER
BUFFER
DRVB
GM AMPLIFIER
ISIN
CURRENT AMPLIFIER SHUTDOWN & STARTUP CONTROL UVLO COMPARATOR CURRENT LIMIT COMPARATOR CURRENT LIMIT REF GENERATOR ISAD
FIGURE 25. FUNCTION DIAGRAM OF THE BOOST CONTROLLER
The internal current limit circuitry is shown in Figure 26. The circuit senses the voltage across the RDS(ON) when the MOSFET is on; then compare it to the internal voltage reference to realize the current limit. The internal voltage reference is generated by a 10A current and any additional current set at ISAD pin flowing through an 8k resistor. The voltage reference is based on the following equation:
V ISAD V THRESHOLD = ---------------- + 10A x 8K R1
VDD 10A VREF 1K 8K + ISIN
LX
LOGIC CONTROLLER
DRVB
ISAD R1
Where VISAD is the voltage at pin ISAD.
V ISAD = V REF - V BE - 1K x I SAD
FIGURE 26. CURRENT LIMIT BLOCK DIAGRAM V ISAD I SAD = ---------------R1
Hence the maximum output current is determined by the following equation:
V IN V THRESHOLD I L I OMAX = --------------------------------------- - -------- x --------R DSON 2 VO
Where VBE 0.7V The external resistor R1 should be chosen in the order of 100K to generate A of current.
Where IL is the peak to peak inductor ripple current, and is set by:
V IN D I L = --------- x ---L fS
fS is the switching frequency; D is the duty cycle.
V O - V IN D = ----------------------VO
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EL7520, EL7520A
Input Capacitor
The input capacitor is used to supply the current to the converter. It is recommended that CIN be larger than 10F. The reflected ripple voltage will be smaller with larger CIN. The voltage rating of input capacitor should be larger than maximum input voltage. For low ESR ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. The voltage rating of the output capacitor should be greater than the maximum output voltage.
Compensation
The EL7520 and EL7520A can operate in either P mode or PI mode. Connecting CINT pin directly to VIN will enable P mode. For better load regulation, use PI mode with a 2.2nF capacitor between CINT and ground.
Boost Inductor
A 3.3H inductor is recommended due to the fixed internal slope compensation. The inductor must be able to handle the following average and peak current:
IO I LAVG = -----------1-D I L I LPK = I LAVG + -------2
Linear-Regulator Controllers (VON, VLOGIC, and VOFF)
The EL7520, EL7520A include three independent linearregulator controllers, in which two are positive output voltage (VON and VLOGIC), and one is negative. The VON, VOFF, and VLOGIC linear-regulator controller functional diagrams, applications circuits are shown in Figures 27, 28, and 29 respectively.
Switching MOSFET
Due to the parasitic inductance of the trace, the MOSFET will experience spikes higher that the output voltage when the MOSFET turns off. Thus, a MOSFET with enough voltage margin is needed. The RDS(ON) of the MOSFET is critical for power dissipation and current limit. A MOSFET with low RDS(ON) is desired to get high efficiency and output current, but very low RDS(ON) will reduce the loop stability. A MOSFET with 20m to 50m RDS(ON) is recommended. Some recommended MOSFETs are shown in following table.
TABLE 2. RECOMMENDED MOSFETs PART NUMBER FDC655AN FDS4488 Si7844DP SI6928DQ MANUFACTURER Fairchild Semiconductor Fairchild Semiconductor Vishay Vishay FEATURE 6.3A, 30V, RDS(ON) = 23m 7.9A, 30V, RDS(ON) = 22m 10A, 30V, RDS(ON) = 22m 20A, 30V, RDS(ON) = 30m
Calculation of the Linear Regulator Base-Emitter Resistors (RBL, RBP and RBN)
For the pass transistor of the linear regulator, low frequency gain (Hfe) and unity gain freq. (fT) are usually specified in the datasheet. The pass transistor adds a pole to the loop transfer function at fp = fT/Hfe. Therefore, in order to maintain phase margin at low frequency, the best choice for a pass device is often a high frequency low gain switching transistor. Further improvement can be obtained by adding a base-emitter resistor RBE (RBP, RBL, RBN in the Functional Block Diagram), which increase the pole frequency to: fp = fT*(1+ Hfe *re/RBE)/Hfe, where re = KT/qIc. So choose the lowest value RBE in the design as long as there is still enough base current (IB) to support the maximum output current (IC). We will take as an example the VLOGIC linear regulator. If a Fairchild FMMT549 PNP transistor is used as the external pass transistor, Q31 in the application diagram, then for a maximum VLOGIC operating requirement of 500mA the data sheet indicates Hfe_min = 100. The base-emitter saturation voltage is: Vbe_max = 1.25V (note this is normally a Vbe ~ 0.7V, however, for the Q5 transistor an internal Darlington arrangement is used to increase it's current gain, giving a 'base-emitter' voltage of 2 x VBE). (Note that using a high current Darlington PNP transistor for Q5 requires that VIN > VLOGIC + 2V. Should a lower input voltage be required, then an ordinary high gain PNP transistor should be selected for Q5 so as to allow a lower collector-emitter saturation voltage). For the EL7520, EL7520A, the minimum drive current is: I_DRVL_min = 8mA
Rectifier Diode
A high-speed diode is desired due to the high switching frequency. Schottky diodes are recommended because of their fast recovery time and low forward voltage. The rectifier diode must meet the output current and peak inductor current requirements.
Output Capacitor
The output capacitor supplies the load directly and reduces the ripple voltage at the output. Output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the ESR of output capacitor, and the charging and discharging of the output capacitor.
IO V O - V IN 1 V RIPPLE = I LPK x ESR + ----------------------- x --------------- x ---f V C
O OUT
S
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The minimum base-emitter resistor, RBL, can now be calculated as: RBL_min = VBE_max/(I_DRVL_min - Ic/Hfe_min) = 1.25V/(8mA - 500mA/100) = 417 This is the minimum value that can be used - so, we now choose a convenient value greater than this minimum value; say 500. Larger values may be used to reduce quiescent current, however, regulation may be adversely affected, by supply noise if RBL is made too high in value.
VBOOST 0.1F 0.9V PG_LDOP + LDO_ON 1: N1 36V ESD CLAMP CP (TO 36V) RBP 7k DRVP FBP + GMP 1: Np RP1 RP2 20k 0.1F Q3 VON (TO 35V) CON LX 0.9V PG_LDOL + LDO_LOG RBL 500 Q5 DRVL RL1 FBL + GML RL2 20k VLOGIC (1.3V TO 3.6V) CLOG 10F VIN OR VPROT (3V TO 6V)
FIGURE 29. VLOGIC FUNCTIONAL BLOCK DIAGRAM
FIGURE 27. VON FUNCTIONAL BLOCK DIAGRAM
The VON power supply is used to power the positive supply of the row driver in the LCD panel. The DC/DC consists of an external diode-capacitor charge pump powered from the inductor (LX) of the boost converter, followed by a low dropout linear regulator (LDO_ON). The LDO_ON regulator uses an external PNP transistor as the pass element. The onboard LDO controller is a wide band (>10MHz) transconductance amplifier capable of 4mA drive current, which is sufficient for up to 40mA or more output current under the low dropout condition (forced beta of 10). Typical VON voltage supported by EL7520, EL7520A range from +15V to +36V. A fault comparator is also included for monitoring the output voltage. The under-voltage threshold is set at 25% below the 1.2V reference. The VOFF power supply is used to power the negative supply of the row driver in the LCD panel. The DC/DC consists of an external diode-capacitor charge pump powered from the inductor (LX) of the boost converter, followed by a low dropout linear regulator (LDO_OFF). The LDO_OFF regulator uses an external NPN transistor as the pass element. The onboard LDO controller is a wide band (>10MHz) transconductance amplifier capable of 4mA drive current, which is sufficient for up to 40mA or more output current under the low dropout condition (forced beta of 10). Typical VOFF voltage supported by EL7520, EL7520A range from -5V to -20V. A fault comparator is also included for monitoring the output voltage. The undervoltage threshold is set at 200mV above the 0.2V reference level. The VLOGIC power supply is used to power the logic circuitry within the LCD panel. The DC/DC may be powered directly from the low voltage input, 3.3V or 5.0V, or it may be powered through the fault protection switch. The LDO_LOGIC regulator uses an external PNP transistor as the pass element. The onboard LDO controller is a wide band (>10MHz) transconductance amplifier capable of 16mA drive current, which is sufficient for up to 160mA or more output current
LX 0.1F
CP (TO -26V) LDO_OFF PG_LDON 0.4V + FBN 1: Nn + GMN 36V ESD CLAMP VREF RN2 20k 0.1F
RN1 VOFF (TO -20V) DRVN RBN 3k Q2 COFF
FIGURE 28. VOFF FUNCTIONAL BLOCK DIAGRAM
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under the low dropout condition (forced beta of 10). Typical VLOGIC voltage supported by EL7520, EL7520A range from +1.3V to VDD-0.2V. A fault comparator is also included for monitoring the output voltage. The undervoltage threshold is set at 25% below the 1.2V reference.
Start-Up Sequence
Figures 30 and 31 show detailed start-up sequence waveforms, EL7520 and EL7520A, respectively. For a successful power-up, there should be six peaks at VCDLY. When a fault is detected, the device will latch off until either EN is toggled or the input supply is recycled. If EN is L, the device is powered down. If EN is H, and the input voltage (VDD) exceeds 2.5V, an internal current source starts to charge CDLY to an upper threshold using a fast ramp followed by a slow ramp. If EN is low at this point, the CDLY ramp will be delayed until EN goes high. The first four ramps on CDLY (two up, two down) are used to initialize the fault protection switch and to check whether there is a fault condition on CDLY or VREF. If a fault is detected, the outputs and the input protection will turn off and the chip will power down. For EL7520A, VREF will stay on. If no fault is found, CCDLY continues ramping up and down until the sequence is completed. During the second ramp, the device checks the status of VREF and over temperature. At the peak of the second ramp, PG output goes low and enables the input protection PMOS Q1. Q1 is a controlled FET used to prevent in-rush current into VBOOST before VBOOST is enabled internally. Its rate of turn on is controlled by Co. When a fault is detected, Q1 will turn off and disconnect the inductor from VIN. With the input protection FET on, NODE1 (See Typical Application Diagram) will rise to ~VIN. Initially the boost is not enabled so VBOOST rises to VIN-VDIODE through the output diode. Hence, there is a step at VBOOST during this part of the start-up sequence. If this step is not desirable, an external PMOS FET can be used to delay the output until the boost is enabled internally. The delayed output appears at AVDD. For EL7520, VBOOST and VLOGIC soft-start at the beginning of the third ramp. The soft-start ramp depends on the value of the CDLY capacitor. For CDLY of 220nF, the soft-start time is ~2ms. EL7520A is the same as EL7520 except that VREF and VLOGIC turn on once input voltage exceeds 2.5V. VOFF turns on at the start of the fourth peak. At the fifth peak, DELB gate goes low to turn on the external PMOS Q4 to generate a delayed VBOOST output. VON is enabled at the beginning of the sixth ramp. AVDD, PG, VOFF, DELB and VON are checked at end of this ramp.
Set-Up LDOs Output Voltage
Refer to Typical Application Diagram, the output voltages of VON, VOFF, and VLOGIC are determined by the following equations:
R 12 V ON = V REF x 1 + --------- R 11 R 22 V OFF = V REFN + --------- x ( V REFN - V REF ) R 21 R 42 V LOGIC = V REF x 1 + --------- R 41
Where VREF = 1.2V, VREFN = 0.2V.
Charge Pump
To generate an output voltage higher than VBOOST, single or multi stages of charge pumps are needed. The number of stage is determined by the input and output voltage. For positive charge pump stages:
V OUT + V CE - V INPUT N POSITIVE ------------------------------------------------------------V INPUT - 2 x V F
where VCE is the dropout voltage of the pass component of the linear regulator. It ranges from 0.3V to 1V depending on the transistor. VF is the forward-voltage of the charge pump rectifier diode. The number of negative charge pump stages is given by:
V OUTPUT + V CE N NEGATIVE -----------------------------------------------V INPUT - 2 x V F
To achieve high efficiency and low material cost, the lowest number of charge pump stages, which can meet the above requirements, is always preferred.
Charge Pump Output Capacitors
A ceramic capacitor with low ESR is recommended. With ceramic capacitors, the output ripple voltage is dominated by the capacitance value. The capacitance value can be chosen by the following equation:
I OUT C OUT -----------------------------------------------------2 x V RIPPLE x f OSC
Where fSOC is the switching frequency.
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EL7520, EL7520A
FAULT DETECTED NORMAL OPERATION
VON SOFT-START
VCDLY
EN
VREF
VBOOST tON tOS VLOGIC
VOFF
tDEL1 DELAYED VBOOST tDEL2 VON
START-UP SEQUENCE TIMED BY CDLY
FIGURE 30. EL7520 START-UP SEQUENCE
15
FAULT PRESENT
CHIP DISABLED
AVDD, VLOGIC SOFT-START
VREF ON
VOFF ON
DELB ON
PG ON
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EL7520, EL7520A
AVDD SOFT-START
FAULT DETECTED NORMAL OPERATION
VON SOFT-START
VREF, VLOGIC ON
VCDLY
VIN EN VREF
VBOOST tON tOS VLOGIC
VOFF
tDEL1 DELAYED VBOOST
VOFF ON
tDEL2 VON tDEL3
START-UP SEQUENCE TIMED BY CDLY
FIGURE 31. EL7520A START-UP SEQUENCE
16
FAULT PRESENT
CHIP DISABLED
PG ON
DELB ON
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EL7520, EL7520A
Over-Temperature Protection
An internal temperature sensor continuously monitor the die temperature. In the event that the die temperature exceeds the thermal trip point, the device will shut down. The upper and lower trigger points are typically set to 130C and -90C respectively.
Layout Recommendation
The device's performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the PCB layout. PCB layout is critical, especially at high switching frequency. There are some general guidelines for layout: 1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. Place VREF and VDD bypass capacitors close to the pins. 3. Reduce the loop with large AC amplitudes and fast slew rate. 4. The feedback network should sense the output voltage directly from the point of load, and be as far away from LX node as possible. 5. The power ground (PGND) and signal ground (SGND) pins should be connected at only one point. A demo board is available to illustrate the proper layout implementation.
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EL7520, EL7520A QFN Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 18
FN7318.0 July 12, 2005

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