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| EM MICROELECTRONIC - MARIN SA EM6604 Ultra Low Power Multi I/O Microcontroller Features * Low Power - typical 1.7A active mode - typical 0.3A standby mode @ 1.5V, 32kHz, 25C * Low Voltage - 1.2 to 1.7V * buzzer - 2kHz * ROM - 1536x16bit (Mask Programmed) * RAM - 72 x 4bit (User Read/Write) * 2 clocks per instruction cycle * RISC architecture * 3 software configurable 4-bit ports * 1 input port * 1 high current output port * 1 Input or Output port - bitwise * Up to 8 outputs (2 ports) * Voltage level detection (1.25V) * Timer watchdog * 8 bit timer * Power On Reset - POR * Internal interrupt sources (timer,prescaler) * External interrupt sources (portA) Figure 1 Architecture Description The EM6604 series is an advanced single chip, mask programmed low-power low-voltage CMOS 4-bit microcontroller. It contains ROM, RAM, timer, prescaler, watchdog timer, voltage level detector and stepper motor driver capability. Its low voltage and low power operation make it the most suitable controller for battery, stand alone and mobile equipment. The EM66XX series is manufactured using EM Microelectronic's Advanced Low Power (ALP) CMOS Process. Figure 2 Pin Configuration Typical * * * * * * * Applications sensor interfaces domestic appliances security systems detectors automotive control clocks measurement equipment 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 1 www.emmicroelectronic.com EM6604 EM6604 at a glance * Power Supply - Low Voltage, low power architecture - Switch between Vdd (output buffers supply) and VddCA (logic supply) - 1.2V ... 1.7V battery voltage - 1.7A in active mode typ. @ 1.5V, 25C - 0.3A in standby mode @ 1.5V, 25C - 32 kHz Oscillator * 4-Bit Input/Output PortC - separate input or output selection by metal mask - direct input read - Pull-up, Pull-down or none, selectable by metal mask if used as Input * RAM - 72 x 4 bit, direct addressable * Buzzer Output - separate buzzer output - 2kHz output or continuous High or Low * ROM - 1536 x 16 bit metal mask programmable * Prescaler - 15 stage system clock divider down to 1 Hz - 3 interrupt requests : 2Hz/8Hz/128Hz - Prescaler reset (from 8kHz to 1Hz) * CPU - 4 bit RISC architecture - 2 clock cycles per instruction - 72 basic instructions * 8-bit Timer - 8-bit auto-reload count-up timer - 4 timer clocks : 2Hz/8Hz/32Hz/256Hz - parallel load - interrupt request when comes to FF hex. * Main Operating Modes and Resets - Active mode (CPU is running) - Standby mode (CPU in Halt) - Initial reset on Power-On (POR) - External reset pin - Watchdog timer (time-out) reset * Supply Voltage Level Detector - Fixed level - 1.25V typical - Busy flag during measure - Active only on request to reduce power consumption * 4-Bit Input PortA - Direct input read - Interrupt request on input's rising or falling edge, selectable by metal mask. - Pull-up, Pull-down or none, selectable by metal mask - Software test variables for conditional jumps * 4-Bit Output PortB - High-current output buffers - min. 4.5mA at 0.15V voltage drop at Vdd=1.2V - differential motor driving capability (a motor with 180= between two pads of PortB is driven with at least 4.75mA * Interrupt Controller - 4 external interrupt sources from PortA - 2 internal interrupt sources, prescaler and timer - each interrupt request is individually maskable - interrupt request flag is cleared automatically on register read - general interrupt request to CPU can be disabled 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 2 www.emmicroelectronic.com EM6604 Table of Contents 1. 1.1 Operating modes ___________________5 STANDBY MODE _______________________5 Table of Figures 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. EM6604 Architecture --------------------Pin Configuration --------------------------Typical Configuration ---------------------EM6604 Mode Transition Diagram ----Reset Sources and Generation --------Port A ----------------------------------------Port B ----------------------------------------Example of using PortB for Motor driving PortC ------------------------------------------Timer ------------------------------------------Interrupt Sources and Generation -----1 1 4 5 5 8 10 10 10 12 13 2. Power Supply _______________________5 3. Reset ______________________________6 3.1 POWER-ON-RESET (POR) CIRCUIT _______________6 3.2 RESET PIN _________________________________6 3.3 WATCHDOG TIMER RESET _____________________6 3.4 CPU STATE AFTER RESET ____________________6 4. Oscillator ___________________________7 A BUILT-IN CRYSTAL OSCILLATOR CIRCUIT GENERATES THE SYSTEM OPERATING CLOCK FOR THE CPU AND PERIPHERAL CIRCUITS FROM AN EXTERNALLY CONNECTED CRYSTAL (TYP. 32.768KHZ). __________________________________7 4.1 PRESCALER ________________________________7 5. Watchdog Timer _____________________8 Table of Tables 6. Input / Output Ports ___________________8 1. 1.1 3.2 4.1 4.2 5.1 6.1 6.2 6.3 6.4 6.5 6.6 7.1 7.2 8.1 8.2 8.3 8.4 9.1 10.1 13.1 13.2 13.3 6.1 PORTA ___________________________________8 6.2 PORTA REGISTERS ___________________________9 6.3 PORTB __________________________________10 6.4 PORTB REGISTERS __________________________10 6.5 PORTC __________________________________10 6.6 PORTC REGISTER ___________________________11 7. Buzzer output ______________________11 7.1 BUZZER REGISTER __________________________12 8. Timer _____________________________12 8.1 TIMER REGISTERS ___________________________13 9. Interrupt controller __________________13 9.1 INTERNAL INTERRUPT SOURCES _________________14 9.2 EXTERNAL INTERRUPT SOURCES : SEE PORTA DESCRIPTION _________________________________14 10. Supply Voltage Level Detector ________14 11. STroBe/RESet ____________________15 12. Test at EM - Active Supply Current test _15 13. EM6604 Metal Mask Options _______16 PA0 input _______________________16 PA0 - IRQ _______________________16 WD timer________________________16 Buzzer __________________________16 15. Electrical specifications______________19 15.1 ABSOLUTE MAXIMUM RATINGS __________________19 15.2: STANDARD OPERATING CONDITIONS ____________19 15.3 HANDLING PROCEDURES _____________________19 15.4: DC CHARACTERISTICS - POWER SUPPLY PINS _____19 15.5: DC CHARACTERISTICS - INPUT/OUTPUT PINS ______20 15.6 OSCILLATOR ______________________________21 Pin Description -----------------------------StandBy Activities -------------------------Initial Value After Reset ------------------Prescaler Interrupt Source ---------- ----Prescaler control Register ------- --------Watchdog Register -------------------------Input/Output Ports Overview ------------PortA Input Status Register --------------PortA Interrupt Request Register -------PortA Interrupt Mask Register ----------PortB Output Register ---------------------PortC Input/Output Register -------------Buzzer frequency selection ---------------Buzzer Control Register ------------------Timer Clock Selection ---------------------Timer Control Register -------------------LOW Timer Load/Status Register -----HIGH Timer Load/Status Register -----Interrupt Control Register -----------------SVLD Control Register -------------------Input/Output ports option -----------------PortA interrupt edge option ------------------Watchdog timer metal option -------------- 4 5 6 7 7 7 8 9 9 9 9 10 11 11 12 12 12 13 14 14 15 15 15 16. Pad Location Diagram_______________22 17. Package and Ordering Information _____22 Dimensions of PDIP24 Package __________22 17.1 ORDERING INFORMATION _____________________24 17.2 PACKAGE MARKING _________________________24 17.3 CUSTOMER MARKING _______________________24 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 3 www.emmicroelectronic.com EM6604 Table 1. Pin Description Pin Pin Name 1 reset 2 Qout/ocs1 3 Qin/osc2 4 VddCA 5 port A, 0 6 port A, 1 7 port A, 2 8 port A, 3 9 STB/RST 10 Vss 11 port B, 0 12 port B, 1 13 port B, 2 14 port B, 3 15,16 NC 17 Vdd 18 port C, 0 19 port C, 1 20 port C, 2 21 port C, 3 22 Buzzer 23 test 24 Vss Function reset input terminal crystal terminal 1 crystal terminal 2 (input) Switched logic supply input 0 port A input 1 port A input 2 port A input 3 port A strobe/reset status output negative power supply terminal output 0 port B output 1 port B output 2 port B output 3 port B not connected positive power supply terminal input / output 0 port C input / output 1 port C input / output 2 port C input / output 3 port C buzzer output test input terminal negative power supply terminal Remarks interrupt request; tvar 1 interrupt request; tvar 2 interrupt request; tvar 3 interrupt request C reset state + port B & C write common with pin 24 (note1) High current output High current output High current output High current output for EM test purpose only common with pin 10 (note1) Note1: It is recommended that both Vss pins (10 and 24) are connected together. Figure 3 Typical configuration 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 4 www.emmicroelectronic.com EM6604 Figure 4 Mode transition diagram 1. Operating modes The EM6604 has a low power dissipation StandBy mode. 1.1 STANDBY Mode Executing a HALT instruction puts the EM6604 into the StandBy mode. The voltage regulator, oscillator, Watchdog timer, interrupts and timer are operating. However, the CPU stops since the clock related to instruction execution stops, registers, RAM, and I/O pins retain their states prior to StandBy mode. StandBy is canceled by a RESET or an Interrupt request, if enabled. Table 1.1 shows the state of the EM6604 functions mode. Table 1.1 STANDBY activities FUNCTION Oscillator Instruction Execution Registers and Flags Interrupt Functions RAM Timer Watchdog I/O pins Supply VLD Reset pin STANDBY Active Stopped Retained Active Retained Active Active Active Stopped Active 2. Power Supply Circuit is supplied by single external power supply between VDD and VSS. Circuit reference is at VSS (ground). To overcome problems with high power output buffers when they are active, internal logic VDDCA can be switched-off from main VDD (SW bit set to "1" in SwCtr register) and is maintained by an external capacitor. High power outputs are supplied directly from main VDD. 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 5 www.emmicroelectronic.com EM6604 Figure 5 Reset sources and generation 3. Reset To initialize the EM6604, a system RESET must be executed. This can be performed in three ways: (1) (2) (3) Initial RESET from the Power-On-Reset circuit. External RESET from the RESET PIN. Watchdog RESET (metal option). During any of these RESET's the STB/RES output pin is high. 3.1 Power-On-Reset (POR) circuit At power on, POR circuit with additional cold start delay resets the microcontroller. The cold start delay logic counts the first 32768 oscillator clocks after power-on and holds the system in RESET to guarantee oscillator stability and duty cycle. The system will consequently remain in RESET for at least one second after power up during which the STB/RES pin is driven high.. 3.2 Reset Pin During active or StandBy mode the RESET terminal has a debouncer to reject noise and therefore the signal must be active high for at least 2ms (CLK = 32kHz) . 3.3 Watchdog Timer RESET The Watchdog Timer will generate a RESET if it is not cleared. See section 5 for details. 3.4 CPU State After RESET RESET initializes the CPU as shown in the table 3.2 below. 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 6 www.emmicroelectronic.com EM6604 Table 3.2 Initial Value After RESET name bits program counter 0 program counter 1 program counter 2 stack pointer index register carry flag halt instruction register periphery register 12 12 12 2 7 1 1 16 4 symbol PC0 PC1 PC2 SP IX CY HALT IR undefined undefined SP(0) selected undefined undefined 0 JUMP 0 see peripheral memory map initial value $000 (as a result of JUMP 0) 4. Oscillator A built-in crystal oscillator circuit generates the system operating clock for the CPU and peripheral circuits from an externally connected crystal (typ. 32.768kHz). EM's special design techniques guarantee the low current consumption of this oscillator. The external impedance between the pads osc-in and osc-out must be greater than 10M. Connection of any other components to the two oscillator pads must be confirmed by EM Microelectronic-Marin SA. 4.1 Prescaler The input to the prescaler is the system clock signal. The prescaler consists of a fifteen element divider chain which delivers clock signals for the peripheral circuits such as the timer, buzzer, clocked pull-up/down resistors, watchdog timer, as well as generating prescaler interrupts. Prescaler interrupt request is generated on falling edge of the selected clock. The frequency of prescaler interrupts is software selectable, as shown in table 4.1. Table 4.2 Prescaler control register - PRESC Bit Name Reset 3 2 1 0 PRST PSF1 PSF0 0 0 0 Prescaler reset PRST resets dividers from 8kHz down to 1Hz. Table 4.1 Prescaler interrupt source Interrupt frequency PSF1 0 = no interrupt 2 Hz 8 Hz 128 Hz 0 0 1 1 PSF0 0 1 0 1 R/W R W (R=0) R/W R/W Description No function , R=0 Prescaler reset Prescaler Interrupt freq. select 1 Prescaler Interrupt freq. select 0 Note: The Prescaler and the Microprocessor clock's are usually non-synchronous, therefore timebases generated are max n, min n-1 clock long n being the selected timer start value in count up mode). However the prescaler clock can be synchronized with the P commands using the prescaler reset function). 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 7 www.emmicroelectronic.com EM6604 5. Watchdog Timer If for any reason the CPU crashes, then the watchdog timer can detect this situation and output a system reset signal. This function can be used to detect program overrun. For normal operation the watchdog timer must be reset periodically by software at least once every three seconds (CLK = 32kHz) or a system reset signal is generated to CPU and periphery. The watchdog reset function can be de-selected with a metal option. The watchdog is active during StandBy. In worst case, because of prescaler reset function, watchdog time-out can come down to 2 seconds. Table 5.1 Watchdog register - WD Bit Name Reset R/W 3 2 1 0 WDRST WD1 WD0 INTEN 0 0 0 W (R=0) R R R/W Description Watchdog timer reset WD Timer data 1/4 Hz WD Timer data 1/2 Hz General Interrupt mask 6. Input / Output Ports The EM6604 has three independent 4-bit ports as shown in Table 6.0 Table 6.1 Input / Output ports Overview port mode mask option PA(0:3) input clocked or fixed pull-up/down PB(0:3) PC(0:3) high current output input or output functions input interrupt on falling/rising edge software test variable input or output Input or Output clocked or fixed pull-up/down 6.1 PortA The EM6604 has one four bit general purpose input port. Each of the input port terminals PA3..PA0 has an internal pull-up/down resistor, which can be selected for each bit with mask options. Pull-up/down can be clocked R > 1MOhm or fixed R = 30 kOhm or 150 kOhm. Port information is read directly from the pin into a register. Input PortA terminals PA0, PA1 and PA2 are also used as input conditions for conditional software branches as shown below : PA0 is connected to CPU TestVar1 PA1 is connected to CPU TestVar2 PA2 is connected to CPU TestVar3 All four bits of the input port PA(0:3) can provide an interrupt, each pin with its own interrupt mask bit in the MPortA register. When a falling edge (for PA3, PA2 and PA1) or a rising edge (for PA0) is detected at the input terminal, the relative interrupt request flag IRQpax is set to "1" in the interrupt request register IRQPortA (only if the corresponding interrupt mask is at "1"). When an interrupt occurs inspection of the IRQPortA and the IntCtr registers allows the source of the interrupt to be identified. The IRQPortA register is automatically cleared by a RESET and by reading the register. At initial RESET the MPortA is set to 0, thus disabling any input interrupts. See also section 9 for further details about the interrupt controller. 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 8 www.emmicroelectronic.com EM6604 Figure 6 Port A 6.2 PortA Registers Table 6.2 PortA input status register - PortA Bit Name Reset 3 2 1 0 PA3 PA2 PA1 PA0 - R/W R R R R Description PA3 input status PA2 input status PA1 input status PA0 input status Table 6.3 PortA Interrupt request register - IRQPortA Bit Name Reset R/W 3 2 1 0 IRQpa3 IRQpa2 IRQpa1 IRQpa0 0 0 0 0 R R R R Description input PA3 interrupt request flag input PA2 interrupt request flag input PA1 interrupt request flag input PA0 interrupt request flag Table 6.4 PortA interrupt mask register - MportA Bit Name Reset R/W 3 2 1 0 MPA3 MPA2 MPA1 MPA0 0 0 0 0 R/W R/W R/W R/W Description interrupt mask for input PA3 interrupt mask for input PA2 interrupt mask for input PA1 interrupt mask for input PA0 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 9 www.emmicroelectronic.com EM6604 6.3 PortB The EM6604 has one four bit general High-power output port which can be used to drive LEDs or stepper motors etc.... Each output can be driven high or low. Output data is written to register PortB. At initial RESET the register is set to 1, thus setting the output port to high = Vdd. When not active driving outputs to high is recommended in order to reduce leakage currents. 6.4 PortB registers Table 6.5 PortB output register - PortB Bit Name Reset 3 2 1 0 PB3 PB2 PB1 PB0 1 1 1 1 R/W R/W R/W R/W R/W Description Output data PB3 Output data PB2 Output data PB1 Output data PB0 PB1 and PB2 can be shorted but in this case they must be driven identically. Figure 7 Port B Figure 8 Example of using port B for Motor driving 6.5 PortC The EM6604 has four individually selectable (metal option) Input/Output PC3..PC0 terminals. Each terminal can be only input or output. 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 10 www.emmicroelectronic.com EM6604 Figure 9 Port C 6.6 PortC register Table 6.6 PortC Input / Output register - PortC Bit Name Reset R/W 3 2 1 0 PC3 PC2 PC1 PC0 R/W R/W R/W R/W Description Input/Output data PC3 Input/Output data PC2 Input/Output data PC1 Input/Output data PC0 7. Buzzer output The EM6604 has one separate buzzer output which is controlled by the buzzer control register BEEP (BCF1 and BCF0 bits). Table 7.0 below shows how to select the output by writing to the BCF1 and BCF0 control flags in the BEEP register. Table 7.1 Buzzer frequency selection Tone frequency BCF1 continuous low continuous high 1024 / 2048 Hz option 2048 Hz 0 0 1 1 BCF0 0 1 0 1 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 11 www.emmicroelectronic.com EM6604 7.1 Buzzer Register Table 7.2 Buzzer control register - BEEP Bit Name Reset 3 2 1 0 BCF1 BCF0 0 0 0 0 R/W R R R/W R/W Description R=0 R=0 Buzzer Frequency control Buzzer Frequency control 8. Timer The EM6604 has a built-in 8 bit auto-reload count-up Timer with 256Hz/32Hz/8Hz/2Hz selectable clock inputs from the prescaler. It can be enabled or disabled by writing TimEn in TimCtr register. When the timer reaches $FF it generates an interrupt request and the flag TimIRQ is set. If the timer interrupt is enabled by setting the mask flag MTimC set to 1, then an interrupt request is generated to the CPU. See also section 9. The timer clock input is selected in the timer control register TimCtr (TEC1 and TEC0 bits). At any time during the count-up process, the timer can be initialized to the data written in the load timer registers LTimLS (low four bits) and HTimLS (high four bits). It starts to count up with the first rising edge of the selected timer clock input after the new LTimLS value was written ( the low four bits writing operation causes the parallel load of the timer ). To load the timer, it is important to first write TimCtr register or HTimLS and then LTimLS. During count up, the timer can always be loaded with a new value, but the high four bits will be accepted only during the write of the low four bits. If the auto reload function is selected in TimCtr register (TimAuto bit), the timer is automatically reloaded with the value contained in LTimLS and HTimLS when it reaches value $FF. Reload is made on the next rising 8kHz clock and is active during half a period of this 8kHz clock. TimAuto bit's value is internally taken into account only during low four bits timer load operation (writing TimAuto to 1 does not start the timer counting up with the last value in the timer load registers but it waits until a new LTimLS load). The timer counting to $FF generates a timer interrupt event TimIRQ and reloads the registers before starting to count up again. To stop the timer at any time, a write of $FF is made to the timer load registers, this sets the TimAuto flag to 0. If the timer is stopped by writing the TimEn bit to 0, the timer status can be read. The currenttimer status can be always obtained by reading the timer registers LTimLS and HTimLS. For proper operation read ordering should be respected such that the first read should be of the LTimLS register followed by the HTimLS register (which was stored on reading LTimLS). Table 8.1 shows the selection of inputs to the timer. Table 8.1 Timer clock selection TEC1 0 0 1 1 TEC0 0 1 0 1 Timer clock input 256 Hz 32 Hz 8 Hz 2 Hz At initial reset, the timer is disabled, the auto-reload function is not active and the timer input clock is 256Hz. 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 12 www.emmicroelectronic.com EM6604 Figure 10 Timer 8.1 Timer registers Table 8.2 Timer control register - TimCtr Bit Name Reset 3 2 1 0 TimAuto TimEn TEC1 TEC0 0 0 0 0 R/W R/W R/W R/W R/W Description Timer AUTO reload Timer enable - active high Timer Clock selection 1 Timer Clock selection 0 Table 8.3 LOW Timer Load/Status register - LTimLS (4 low bits) Bit Name Reset R/W Description 3 2 1 0 TL3/TS3 TL2/TS2 TL1/TS1 TL0/TS0 0 0 0 0 R/W R/W R/W R/W Timer load/status bit 3 Timer load/status bit 2 Timer load/status bit 1 Timer load/status bit 0 Table 8.4 HIGH Timer Load/Status register - HTimLS (4 high bits) Bit Name Reset R/W Description 3 2 1 0 TL7/TS7 TL6/TS6 TL5/TS5 TL4/TS4 0 0 0 0 R/W R/W R/W R/W Timer load/status bit 7 Timer load/status bit 6 Timer load/status bit 5 Timer load/status bit 4 9. Interrupt controller There are two internal and four external interrupt sources in EM6604 : 1) prescaler interrupt at 128Hz, 8Hz or 2Hz 2) timer interrupt when value changes from $FE to $FF 3) portA interrupt on falling edge (for PA3, PA2 and PA1) and rising edge (for PA0) A general interrupt mask is defined in the watchdog control register WD (INTEN bit). 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 13 www.emmicroelectronic.com EM6604 9.1 Internal interrupt sources The interrupt request flags and relative interrupt masks are defined in the interrupt control register INTctr (PrscIRQ and Mprsc bits for the prescaler - TimIRQ and Mtim bits for the timer). An interrupt mask set to "1" allows CPU interrupt. An interrupt request flag may be set to "1" even if the relative interrupt mask is at "0" ; but in this case, the CPU will not be interrupted. Interrupt request flags are cleared after INTctr reading operation. At initial reset, interrupt requests are disabled. Figure 11 Interrupt sources and generation Table 9.1 Interrupt control register INTctr Bit Name Reset 3 2 1 0 PrscIRQ Mprsc TimIRQ Mtim 0 0 0 0 R/W R R/W R R/W Description Prescaler Interrupt ReQuest Prescaler Interrupt mask Timer Interrupt ReQuest Timer Interrupt mask 9.2 External interrupt sources : see PortA description 10. Supply Voltage Level Detector SVLD detects if the supply voltage is lower/higher than 1,25V. It can be enabled or disabled by writing SLVDst bit in SLVD register. 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 14 www.emmicroelectronic.com EM6604 The measurement period lasts 1,923 ms (= 2 * 1024 Hz clock period), and the busy flag is cleared when measurement is finished to indicate a valid result. SVLDres bit at "0" means that power supply level is higher than 1,25V. SVLDres bit at "1" means that power supply level is lower than 1,25V. The result SVLDres of the last measurement remains until the new one is started. The start of a new SVLD measurement resets the result of the previous one (SVLDres => 0). When SVLD is activated power consumption increases by approximately 3A. Table 10.1 SVLD control register - SVLD Bit 3 2 1 0 Name SVLDres busy SVLDst Reset 0 0 0 0 R/W R R R=0 W/R=0 Description SVLD result (0=higher 1=lower) measurement in progress SVLD start measurement 11. STroBe/RESet The STB/RES output pin is used to indicate: 1.) The EM6604 write operations to ports B and C. For a PortB and PortC write operation the STROBE signal goes high for half of the system clock period. Write is effected on falling edge of the strobe signal and it can this be used to indicate when data changes at the output port pins. 2.) Any microcontroller EM6604 reset condition. Additionally, any EM6604 internal RESET condition is indicated by a continuous high level on STB/RES for the period of the RESET. 12. Test at EM - Active Supply Current test For this purpose, five instructions at the end of the ROM will be added. Testloop: STI LDR NXORX JPZ JMP 00H, 0AH 1BH Testloop 00H To stay in the testloop, these values must be written in the corresponding addresses before jumping in the loop: 1BH: 32H: 6EH: 6FH: 0101b 1010b 0010b 0011b Free space after last instruction: JMP 00H (0000) Remark: empty space within the program are filled with NOP (FOFF). 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 15 www.emmicroelectronic.com EM6604 13. EM6604 Metal Mask Options The following options can be selected at the time of programming the metal mask ROM. To select an option put a cross - X. Table 13.1 Input / Output ports option Output 0 Clocked Pull-Down R > 1M Clocked Pull-Up R > 1M Pull-Down R = 30k Pull-Down R = 150k Pull-Up R = 30k Pull-Up R = 150k No Input Pull-Up or PullDown 1 2 3 Pa0opt3 Pa1opt3 Pa2opt3 Pa3opt3 Pc0opt3 Pc1opt3 Pc2opt3 Pc3opt3 4 Pa0opt4 Pa1opt4 Pa2opt4 Pa3opt4 Pc0opt4 Pc1opt4 Pc2opt4 Pc3opt4 5 Pa0opt5 Pa1opt5 Pa2opt5 Pa3opt5 Pc0opt5 Pc1opt5 Pc2opt5 Pc3opt5 6 Pa0opt6 Pa1opt6 Pa2opt6 Pa3opt6 Pc0opt6 Pc1opt6 Pc2opt6 Pc3opt6 7 Pa0opt7 Pa1opt7 Pa2opt7 Pa3opt7 Pc0opt7 Pc1opt7 Pc2opt7 Pc3opt7 Pa0opt1 Pa0opt2 A0 PA0 input Pa1opt1 Pa1opt2 A1 PA1 input Pa2opt1 Pa2opt2 A2 PA2 input Pa3opt1 Pa3opt2 A3 PA3 input Pc0opt0 Pc0opt1 Pc0opt2 C0 PC0 In/Out Pc1opt0 Pc1opt1 Pc1opt2 C1 PC1 In/Out Pc2opt0 Pc2opt1 Pc2opt2 C2 PC2 In/Out Pc3opt0 Pc3opt1 Pc3opt2 C3 PC3 In/Out (ONE option in each line MUST be selected) Table 13.2 PortA interrupt edge option Interrupt on Input's rising edge 8 I0 I1 I2 I3 IrqPa0_R Interrupt on Input's falling edge 9 IrqPa0_F PA0 - IRQ IrqPa1_R IrqPa1_F PA1 - IRQ IrqPa2_R IrqPa2_F PA2 - IRQ IrqPa3_R IrqPa3_F PA3 - IRQ If not used the default is falling edge. However, an interrupt will not be generated if the corresponding bit in this register MPortA is 0. (ONE option in each line MUST be selected) Table 13.3 Watchdog timer metal option Watch-Dog timer ACTIVE W0 WD timer (ONE option MUST be selected) Wd_yes Watch-Dog timer INACTIVE Wd_no Table 13.4 Buzzer 1024 / 2048 Hz option when BCF1,BCF0 = 10 Buzzer freq. of 1k ( and 2k) Buzzer freq. of 2k only B1 Buzzer (ONE option MUST be selected) Buz_1k_2k Buz_2k The customer should specify the required options at the time of ordering. A copy of this sheet, as well as the Software ROM characteristic file generated by the assembler (*.STA) should be attached to the order. 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 16 www.emmicroelectronic.com EM6604 14. PERIPHERAL MEMORY MAP The following table shows the peripheral memory map of the EM6604. The address space is between $00 and $7F (Hex). Any addresses not shown can be considered to be reserved. Register name RAM add hex add dec reset value b'3210 xxxx write_bits read_bits Remarks 00- 0-71 47 SwCtr 6B 107 xxx0 SVLD 6C 108 0000 Read/Write_bits 0: D0 1: D1 2: D2 3: D3 0: SW 1: 2: 3: 0: SVLDst 0: 0 1: 1: 0 2: 2: busy 3: 3: SVLDres direct addressing Supply switch control voltage level detector control internally used for INDEX register internally used for INDEX register low nibble of 8bit timer load and status register high nibble of 8bit timer load and status register timer control register with frequency selector global interrupt enable watchdog timer control Prescaler control Index LOW Index HIGH LTimLS 6E 6F 70 110 111 112 xxxx xxxx 1111 0: TL0 1: TL1 2: TL2 3: TL3 0: TL4 1: TL5 2: TL6 3: TL7 0: TS0 1: TS1 2: TS2 3: TS3 0: TS4 1: TS5 2: TS6 3: TS7 0: TEC0 1: TEC1 2: TimEn 3:TimAuto 0: INTEN 1: WD0 2: WD1 3: 0 0: PSF0 1: PSF1 2: 0 3: 0 0: PA0 1: PA1 2: PA2 3: PA3 0: MPA0 1: MPA1 2: MPA2 3: MPA3 HTimLS 71 113 1111 TimCtr 72 114 0000 WD 73 115 0000 PRESC 74 116 0000 0: INTEN 1: 2: 3: WDrst 0: PSF0 1: PSF1 2: PRST 3: - PortA 75 117 xxxx Port A status MPortA 76 118 0000 Port A mask 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 17 www.emmicroelectronic.com EM6604 Register name IRQportA add hex 77 add dec 119 reset value b'3210 0000 write_bits read_bits Remarks Read/Write_bits 0: IRQpa0 1: IRQpa1 2: IRQpa2 3: IRQpa3 0: PB0 1: PB1 2: PB2 3: PB3 0: PC0 1: PC1 2: PC2 3: PC3 0: MTim 0: MTim 1: 1: TimIRQ 2: MPrsc 2: MPrsc 3: 3: PrescIRQ 0: BCF0 1: BCF1 2: 3: ------- Port A interrupt request PortB 78 120 1111 Port B Output PortC 7A 122 xxxx Port C Input/Output data INTctr 7D 125 0000 prescaler and timer interrupt mask and request Buzzer control BEEP 7E 126 0000 RegTestEM 7F 127 ---- reserved 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 18 www.emmicroelectronic.com EM6604 15. Electrical specifications 15.1 Absolute maximum ratings Min. Max. Units Power supply VDD-VSS - 0.2 + 3.6 V Input voltage VSS - 0.2 VDD+0.2 V Storage temperature - 40 + 125 C Electrostatic discharge to MIL-STD-883C method 3015 -2000 +2000 V Maximum soldering conditions 10s x 250C Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified electrical characteristics may affect device reliability or cause malfunction. 15.2: Standard Operating Conditions Parameter Value Description Temperature -20C...+65C VDD +1.2 ...+1.70V VSS 0 V (reference) CVDDCA min. 100nF (note1) switched logic supply capacitor fq 32768 Hz nominal frequency Rqs 35 kOhm typical quartz serial resistor CL 8.2pF typical quartz load capacitance df/f +/- 30 ppm quartz frequency tolerance Note1: This capacitor maintains the Supply to the core when the core has been isolated by the internal Supply switch during driving the high current outputs. The user should be aware that the selection of this capacitor will dictate the time that the core can be isolated. 15.3 Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions should be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. 15.4: DC characteristics - Power Supply Pins Vdd=1.5V, T=25C (unless otherwise specified) Parameter Conditions Symb. Min. Typ. Max. Unit ACTIVE Supply Current +25C (note2) 1.7 5.0 IVDDa A ACTIVE Supply Current (note2) (note3) = (in active mode) -20C...+65C 15.0 IVDDa A STANDBY Supply Current +25C 0.3 0.6 IVDDh A STANDBY Supply Current (note3) = (in Halt mode) -20C...+65C 10.0 IVDDh A RAM data retention Vrd 1.1 V Resistor Of VDDCA switch VDD=1.3V 300 kOhm Rdoff VDDCA=1.5V 450 2000 Ohm f(IVDD) Rdon POR voltage -20..+65 C 0.7 1.05 V VPOR SVLD voltage 1.10 1.25 1.38 V VSVLD Note2: test loop with successive writing and reading of two different addresses with an inverted values (five instructions should be reserved for this measurement), Note3: NOT tested if delivered in chip form. 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 19 www.emmicroelectronic.com EM6604 15.5: DC characteristics - Input/Output Pins Vdd=1.5V, -20C VIH RL01 = RL23 = 180 Ohm VDD=1.2V VDD=1.5V VDD=1.7V VOL = 0.15V, VDD = 1.2V VOL = 0.3V, VDD = 1.2V VOL = 0.3V, VDD = 1.5V VOH = 1.05V, VDD=1.2V VOH = 0.9V, VDD=1.2V VOH = 1.2V, VDD=1.5V IRL IRL IRL IOL IOL IOL IOH IOH IOH Input CLK'd Pull-up/down (if selected) on PortA and PortC Vdd=1.5V, -20C Copyright 2002, EM Microelectronic-Marin SA 20 www.emmicroelectronic.com EM6604 Input static Pull-up/down (if selected) on PortA and PortC, Test, Reset Vdd=1.5V, -20C 15.6 Oscillator 1.2V Copyright 2002, EM Microelectronic-Marin SA 21 www.emmicroelectronic.com EM6604 16. Pad Location Diagram A ll d im e ns ion s in M icro ns sxxcp v[RQ naQ v[PWU naN v[ONWU w [P NU V w [OV U P n QA w[OU TS n QA w[OT NS n PA w[OR NS n PA w[OP RS rcqrP w [OS PO tqqQ w [OQ PT naO v[VNS naP v[SSO E M 66 04 a f gn>q gx c >ai>v >[>Q NP P >a aCe eci>Ao >w >[>PP VT >a aCeec i e e>>v >[>OOW >a aai>>Ao>>w >[ >W N >a aai aNaia>eO>iaN >EaN>>x >[>OO>a aai tAAiP v[OUOV tAAiO v[OWTP pcqcr w [V T Q o m ii w [T S N n OA w[V T U n OA w[U NU n NA w[S NU n NA w[Q R U o ac w [OR w [KP NV w [N w[N qrMpqr v[OWPO v[PTNR tqqP v[PQPQ 17. Package and Ordering Information Dimensions of PDIP24 Package P-DIP24 .300 INCH body width v[PVQW n_P v[OQSW v[KPON n_Q v[OTOQ rcqr v[QRT tqqO v[PORO tEEa_ v[SRV n_N v[VOR n_O v[OONS v[N 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 22 www.emmicroelectronic.com EM6604 Dimensions of TSSOP24 Package TSSOP24 (0.65mm pitch, 4.4mm body width) Dimensions of SOP24 Package SOP-24(1.27mm pitch, 300mils body width) 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 23 www.emmicroelectronic.com EM6604 17.1 Ordering Information Packaged Device: EM6604 %%% SO24 B Customer Version: customer-specific number given by EM Microelectronic Package: SO24 = 24 pin SOIC TP24 = 24 pin TSSOP DL24 = 24 pin DIP (note 1) Delivery Form: A = Stick B = Tape&Reel (for SO24 and TP24 only) Device in DIE Form: EM6604 %%% WS 11 Customer Version: customer-specific number given by EM Microelectronic Die form: WW = Wafer WS = Sawn Wafer/Frame WP = Waffle Pack Thickness: 11 = 11 mils (280um), by default 27 = 27 mils (686um), not backlapped (for other thickness, contact EM) Note 1: Please contact EM Microelectronic-Marin S.A. for availability of DIP package. Ordering Part Number (selected examples) Part Number EM6604%%%SO24A EM6604%%%SO24B EM6604%%%TP24B EM6604%%%WS11 EM6604%%%WP11 EM6604%%%WW27 Package/Die Form 24 pin SOIC 24 pin SOIC 24 pin TSSOP Sawn wafer Die in waffle pack Unsawn wafer Delivery Form/Thickness Stick Tape&Reel Tape&Reel 11 mils 11 mils 27 mils Please make sure to give the complete Part Number when ordering, including the 3-digit version. The version is made of 3 digits %%%: the first one is a letter and the last two are numbers, e.g. P01 , P12, etc. 17.2 Package Marking DIP and SOIC marking: First line: Second line: Third line: EM6604 0 %%Y PPPPPPPPPPP CCCCCCCCCCC TSSOP marking: EM6 6 0 4%% PPPPPPPP CCCCYP Where: %% = last two-digits of the customer-specific number given by EM (e.g. 05, 12, etc.) Y = Year of assembly PP...P = Production identification (date & lot number) of EM Microelectronic CC...C = Customer specific package marking on third line, selected by customer 17.3 Customer Marking There are 11 digits available for customer marking on DIP24 and SO24. There are 4 digits available for customer marking on TSSOP24. Please specify below the desired customer marking. 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 24 www.emmicroelectronic.com EM6604 Changed on Jan. 6 1999 Table of contents/ Figures / Tables (page 3) Table 6.4 PortB ... -> Table 6.5 PortB ... (page 9) SVLDres bit at "1" means that power supply level is lower than 1,25V. The result SVLDres of the last measurement remains until the new one is started. The start of a new SVLD measurement resets the result of the previous one (SVLDres => 0). (page 14) th Updates since Rev C/401 (november 01) Date of Update Name 01.11.01 22.03.02 Chapter New Version concerned All 17 & 18 11/01 C/401 D/440 Changes Change Header & footer, Add URL mention Change pad loc. Diagram ordering information 03.02 REV. D/440 Copyright 2002, EM Microelectronic-Marin SA 25 www.emmicroelectronic.com |
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