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HUF76113T3ST Data Sheet June 2003 4.7A, 30V, 0.031 Ohm, N-Channel, Logic Level UltraFET Power MOSFET This N-Channel power MOSFET is (R) manufactured using the innovative UltraFET process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, low-voltage bus switches, and power management in portable and batteryoperated products. Formerly developmental type TA76113. Features * Logic Level Gate Drive * 4.7A, 30V * Ultra Low On-Resistance, rDS(ON) = 0.031 * Temperature Compensating PSPICE(R) Model * Temperature Compensating SABERTM Model * Thermal Impedance SPICE Model * Thermal Impedance SABER Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards" Ordering Information PART NUMBER HUF76113T3ST PACKAGE SOT-223 76113 BRAND Symbol D NOTE: HUF76113T3ST is available only in tape and reel. G S Packaging SOT-223 GATE DRAIN SOURCE DRAIN (FLANGE) (c)2003 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B2 HUF76113T3ST Absolute Maximum Ratings TA = 25oC, Unless Otherwise Specified HUF76113T3ST Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V DSS Drain to Gate Voltage (R GS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V DGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TA= 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA= 100oC, VGS = 5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA= 100oC, VGS = 4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 30 30 20 4.7 2.7 2.6 Figure 4 Figure 6 1.1 0.0091 -55 to 150 300 260 W W/oC oC oC oC UNITS V V V A A A CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications PARAMETER OFF STATE SPECIFICATIONS TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS ID = 250A, VGS = 0V (Figure 12) VDS = 25V, VGS = 0V VDS = 25V, VGS = 0V, TC = 150oC 30 - - 1 250 100 V A A nA Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance IGSS VGS = 20V VGS(TH) rDS(ON) VGS = VDS, ID = 250A (Figure 11) ID = 4.7A, VGS = 10V (Figure 9, 10) ID = 2.7A, VGS = 5V (Figure 9) ID = 2.6A, VGS = 4.5V (Figure 9) 1 - 0.027 0.033 0.035 3 0.031 0.038 0.040 V THERMAL SPECIFICATIONS Thermal Resistance Junction to Ambient RJA Pad Area = 0.173 in2 (Note 2) Pad Area = 0.068 in2 (See TB377) Pad Area = 0.026 in2 (See TB377) SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) tr td(OFF) tf tOFF VDD = 15V, ID 2.6A, RL = 5.8, VGS = 4.5V, RGS = 18 (Figure 15) 12 46 31 31 90 95 ns ns ns ns ns ns 110 133 157 oC/W oC/W oC/W (c)2003 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B2 HUF76113T3ST Electrical Specifications PARAMETER TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance NOTES: 2. Rated with RJA=110oC/W measured using FR-4 board with 0.173 in2 copper at 1000 seconds. CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) 625 310 60 pF pF pF Qg(TOT) Qg(5) Qg(TH) Qgs Qgd VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 15V, ID 2.7A, RL = 5.5 Ig(REF) = 1.0mA (Figure 14) 17.0 9.5 0.73 1.50 4.30 20.5 11.5 0.90 nC nC nC nC nC tON td(ON) tr td(OFF) tf tOFF VDD = 15V, ID 4.7A, RL = 3.2, VGS = 10V, RGS = 9.1 (Figure 16) 4 21 31 25 40 85 ns ns ns ns ns ns Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage SYMBOL VSD ISD = 4.7A ISD = 2.7A Reverse Recovery Time Reverse Recovered Charge trr QRR ISD = 2.7A, dISD/dt = 100A/s ISD = 2.7A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 1.00 44 46 UNITS V V ns nC Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) ID, DRAIN CURRENT (A) 5 VGS = 10V, RJA = 110oC/W 4 3 VGS = 4.5V, RJA = 110oC/W 2 1 0 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE (c)2003 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B2 HUF76113T3ST Typical Performance Curves 2 1 THERMAL IMPEDANCE ZJA, NORMALIZED (Continued) 0.1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM RJA = 110oC/W 0.01 SINGLE PULSE t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-1 100 10 1 102 103 0.001 10 -5 10-4 10 -3 10-2 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 500 RJA = 110oC/W IDM, PEAK CURRENT (A) 100 VGS = 5V VGS = 10V TC = 25 oC FOR TEMPERATURES ABOVE 25 oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TA 125 10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 1 10-5 10-4 10 -3 10 -2 10 -1 t, PULSE WIDTH (s) 100 101 102 103 FIGURE 4. PEAK CURRENT CAPABILITY 200 100 ID, DRAIN CURRENT (A) 40 IAS, AVALANCHE CURRENT (A) TJ = MAX RATED TA = 25oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] STARTING TJ = 25 oC 100s 10 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) VDSS(MAX) = 30V 1 10 1ms STARTING TJ = 150oC 10ms 1 1 100 0.01 0.1 1 10 100 tAV, TIME IN AVALANCHE (ms) VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY (c)2003 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B2 HUF76113T3ST Typical Performance Curves 30 25 20 15 10 150 oC 5 25 oC 0 0 1 2 3 4 VGS, GATE TO SOURCE VOLTAGE (V) 5 -55oC 0 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) (Continued) ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 30 25 20 15 10 5 VGS = 3V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25 oC VGS = 10V VGS = 5V VGS = 4V VGS = 3.5V FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS 80 rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) 70 60 ID = 4.7A 50 40 ID = 0.5A 30 20 2 4 6 1.8 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1.6 1.4 1.2 1.0 0.8 0.6 8 10 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 4.7A -80 -40 0 40 80 120 160 VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 1.2 1.1 NORMALIZED GATE THRESHOLD VOLTAGE 1.0 0.9 0.8 0.7 0.6 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A ID = 250A 1.1 1.0 0.9 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE (c)2003 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B2 HUF76113T3ST Typical Performance Curves 1000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD (Continued) 10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 15V 8 C, CAPACITANCE (pF) 800 CISS 600 6 400 4 WAVEFORMS IN DESCENDING ORDER: ID = 4.7A ID = 0.5A 0 5 10 Qg, GATE CHARGE (nC) 15 20 COSS 200 2 CRSS 0 0 5 10 15 20 25 VDS , DRAIN TO SOURCE VOLTAGE (V) 30 0 NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 100 VGS = 4.5V, VDD = 15V, ID = 2.6A, RL = 5.8 SWITCHING TIME (ns) 80 td(OFF) 60 tf tr SWITCHING TIME (ns) 150 VGS = 10V, VDD = 15V, ID = 4.7A, RL = 3.2 120 td(OFF) 90 tf 60 tr 30 td(ON) 40 td(ON) 20 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE () 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE () FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01 0 tAV FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS (c)2003 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B2 HUF76113T3ST Test Circuits and Waveforms (Continued) VDS RL VDD VDS VGS = 10 VGS + Qg(TOT) Qg(5) VDD VGS VGS = 1V 0 Qg(TH) Ig(REF) 0 VGS = 5V DUT Ig(REF) FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS VDS tON td(ON) RL VDS 90% tr tOFF td(OFF) tf 90% VGS + DUT RGS VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAVEFORM Thermal Resistance vs. Mounting Pad Area The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. In using surface mount devices such as the SOT-223 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. P DM (T -T ) JM A= -----------------------------Z JA (EQ. 1) 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. (c)2003 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B2 HUF76113T3ST Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 23 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are R JA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, P DM. The smallest areas represent 200 the minimum bond pad area and the package outline area respectively as determined from the package diagram Thermal resistances corresponding to other copper areas can be obtained from Figure 23 or by calculation using Equation 2. R JA is defined as the natural log of the area times a coefficient added to a constant. The area, in square inches is the top copper area including the gate and source pads. R JA = 65.3 - 25 x ln ( Area ) (EQ. 2) The transient thermal impedance (ZJA) is also effected by varied top copper board area. Figure 24 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1. 157 oC/W - 0.026in2 RJA (oC/W) 150 133 oC/W - 0.068in2 110 oC/W - 0.173in2 100 50 0.01 RJA = 65.3 - 25 * ln(AREA) 0.1 AREA, TOP COPPER AREA (in2) 1 FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA 120 100 IMPEDANCE (oC/W) ZJA, THERMAL 80 60 40 20 0 10 -1 COPPER BOARD AREA - DESCENDING ORDER 0.077 in2 0.308 in2 0.535 in2 0.760 in2 0.996 in2 10 0 101 t, RECTANGULAR PULSE DURATION (s) 10 2 103 FIGURE 24. THERMAL IMPEDANCE vs MOUNTING PAD AREA (c)2003 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B2 HUF76113T3ST PSPICE Electrical Model .SUBCKT HUF76113T3 2 1 3 ; CA 12 8 8.7e-10 CB 15 14 8.7e-10 CIN 6 8 5.6e-10 10 REV August 1998 LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + EBREAK MWEAK MMED MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 14 IT 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 17 18 DBODY DRAIN 2 RSLC1 51 ESLC 50 RSLC2 5 51 EBREAK 11 7 17 18 34.3 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.69e-9 LSOURCE 3 7 4.1e-10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD GATE 1 ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6 RLGATE RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 9.2e-3 RGATE 9 20 2.5 RLDRAIN 2 5 10 RLGATE 1 9 16.9 RLSOURCE 3 7 4.1 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 12.5e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD - - VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*180),2.5))} .MODEL DBODYMOD D (IS = 9.35e-13 RS = 1.39e-2 TRS1 = 1.12e-6 TRS2 = 1.05e-6 CJO = 9.85e-10 TT = 2.82e-8 M = 0.42) .MODEL DBREAKMOD D (RS = 1.5e-1 TRS1 = 3.51e-3 TRS2 = -5e-5) .MODEL DPLCAPMOD D (CJO = 4.4e-10 IS = 1e-30 N = 10 M = 0.6) .MODEL MMEDMOD NMOS (VTO = 1.95 KP = 3.55 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.5) .MODEL MSTROMOD NMOS (VTO = 2.23 KP = 29 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.68 KP = 0.095 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 25 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 9.7e-4 TC2 = -5e-7) .MODEL RDRAINMOD RES (TC1 = 5.8e-3 TC2 = 1.12e-5) .MODEL RSLCMOD RES (TC1 = -9.92e-3 TC2 = -2.06e-5) .MODEL RSOURCEMOD RES (TC1 = 3e-3 TC2 = 0) .MODEL RVTHRESMOD RES (TC = -1.2e-3 TC2 = -5.42e-6) .MODEL RVTEMPMOD RES (TC1 = -1.9e-3 TC2 = 1e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -7.0 VOFF = -1.5) VON = -1.5 VOFF = -7.0) VON = -0.8 VOFF = 0.6) VON = 0.6 VOFF = -0.8) NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2003 Fairchild Semiconductor Corporation + DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD - RDRAIN 21 16 - VBAT + 8 22 RVTHRES HUF76113T3ST Rev. B2 HUF76113T3ST SABER Electrical Model REV October 1998 template huf76113T3 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 9.35e-13, cjo = 9.85e-10, tt = 2.82e-8, m = 0.42) d..model dbreakmod = () d..model dplcapmod = (cjo = 4.4e-10, is = 1e-30, n = 10, m = 0.6) m..model mmedmod = (type=_n, vto = 1.95, kp = 3.55, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.23, kp = 29, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.68, kp = 0.095, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7.0, voff = -1.5) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.5, voff = -7.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.8, voff = 0.6) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.6, voff = -0.8) c.ca n12 n8 = 8.7e-10 c.cb n15 n14 = 8.7e-10 c.cin n6 n8 = 5.6e-10 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod LGATE ESG + GATE 1 RLGATE CIN EVTEMP RGATE + 18 22 9 20 6 MSTRO 8 LDRAIN DPLCAP 10 RSLC1 51 RSLC2 ISCL RLDRAIN RDBREAK 72 DBREAK 11 MWEAK MMED EBREAK + 17 18 71 RDBODY 5 DRAIN 2 6 8 EVTHRES + 19 8 50 RDRAIN 21 16 i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 1.69e-9 l.lsource n3 n7 = 4.1e-10 DBODY RSOURCE LSOURCE 7 RLSOURCE SOURCE 3 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u 12 S1A 13 8 S1B CA 13 + EGS 6 8 S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17 RBREAK 18 RVTEMP 19 res.rbreak n17 n18 = 1, tc1 = 9.7e-4, tc2 = -5e-7 res.rdbody n71 n5 = 1.39e-2, tc1 = 1.12e-6, tc2 = 1.05e-6 res.rdbreak n72 n5 = 1.5e-1, tc1 = 3.51e-3, tc2 = -5e-5 res.rdrain n50 n16 = 9.2e-3, tc1 = 5.8e-3, tc2 = 1.12e-5 res.rgate n9 n20 = 2.5 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 16.9 res.rlsource n3 n7 = 4.1 res.rslc1 n5 n51 = 1e-6, tc1 = -9.92e-3, tc2 = -2.06e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 12.5e-3, tc1 = 3e-3, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.9e-3, tc2 = 1e-6 res.rvthres n22 n8 = 1, tc1 = -1.2e-3, tc2 = -5.42e-6 spe.ebreak n11 n7 n17 n18 = 34.3 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 VBAT + - - 8 22 RVTHRES equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 2.5)) } } (c)2003 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B2 HUF76113T3ST SPICE Thermal Model REV August 1998 HUF76113T3ST Copper Area = 0.077 in2 CTHERM1 th 8 1.9e-5 CTHERM2 8 7 9.5e-4 CTHERM3 7 6 1.9e-3 CTHERM4 6 5 3.5e-3 CTHERM5 5 4 2.0e-2 CTHERM6 4 3 6.5e-2 CTHERM7 3 2 2.4e-1 CTHERM8 2 tl 9.0e-1 RTHERM1 th 8 3.5e-3 RTHERM2 8 7 3.1e-2 RTHERM3 7 6 2.0e-1 RTHERM4 6 5 8.0e-1 RTHERM5 5 4 2.1 RTHERM6 4 3 11 RTHERM7 3 2 32 RTHERM8 2 tl 66 RTHERM1 8 CTHERM1 th JUNCTION RTHERM2 7 CTHERM2 RTHERM3 6 CTHERM3 RTHERM4 5 CTHERM4 SABER Thermal Model Copper Area = 0.077 in2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 = 1.9e-5 ctherm.ctherm2 8 7 = 9.5e-4 ctherm.ctherm3 7 6 = 1.9e-3 ctherm.ctherm4 6 5 = 3.5e-3 ctherm.ctherm5 5 4 = 2.0e-2 ctherm.ctherm6 4 3 = 6.5e-2 ctherm.ctherm7 3 2 = 2.4e-1 ctherm.ctherm8 2 tl = 9.0e-1 rtherm.rtherm1 th 8 = 3.5e-3 rtherm.rtherm2 8 7 = 3.1e-2 rtherm.rtherm3 7 6 = 2.0e-1 rtherm.rtherm4 6 5 = 8.0e-1 rtherm.rtherm5 5 4 = 2.1 rtherm.rtherm6 4 3 = 11 rtherm.rtherm7 3 2 = 32 rtherm.rtherm8 2 tl = 66 } RTHERM5 4 CTHERM5 RTHERM6 3 CTHERM6 RTHERM7 2 CTHERM7 RTHERM8 CTHERM8 tl AMBIENT TABLE 1. THERMAL MODELS COMPONENT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 0.077 in2 6.5e-2 2.4e-1 9.0e-1 11 32 66 0.308 in2 6.7e-2 3.5e-1 1.7 9 18 45.5 0.535 in2 6.7e-2 3.5e-1 1.9 9 16 40 0.76 in2 6.7e-2 3.5e-1 2 9 15.5 36 0.996 in2 6.7e-2 3.5e-1 2.4 9 14.5 31.5 (c)2003 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B2 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM FACTTM ActiveArrayTM FACT Quiet SeriesTM BottomlessTM FAST(R) CoolFETTM FASTrTM CROSSVOLTTM FRFETTM DOMETM GlobalOptoisolatorTM EcoSPARKTM GTOTM E2CMOSTM HiSeCTM I2CTM EnSignaTM Across the board. Around the world.TM The Power FranchiseTM Programmable Active DroopTM DISCLAIMER ImpliedDisconnectTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench(R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SILENT SWITCHER(R) SMART STARTTM SPMTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic(R) TruTranslationTM UHCTM UltraFET(R) VCXTM FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Preliminary No Identification Needed Full Production Obsolete Not In Production Rev. I2 |
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