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| PRELIMINARY Integrated Circuit Systems, Inc. ICS8430252-45 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER FEATURES * One differential 3.3V LVPECL output and One LVCMOS/LVTTL output * Crystal oscillator interface designed for a 25MHz, 18pF parallel resonant crystal * A 25MHz crystal generates both an output frequency of 156.25MHz (LVPECL) and 125MHz (LVCMOS) * VCO frequency: 625MHz * RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz) using a 25MHz crystal: 0.39ps (typical) * Full 3.3V supply mode * 0C to 70C ambient operating temperature * Industrial temperature available upon request * Available in both standard and lead-free RoHS compliant packages GENERAL DESCRIPTION The ICS8430252-45 is a 2 output LVPECL and LVCMOS/LVTTL Synthesizer optimized to genHiPerClockSTM erate Ethernet reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 25MHz, 18pF parallel resonant crystal, the following frequencies can be generated: 156.25MHz LVPECL output and, 125MHz LVCMOS output. The 8430252-45 uses ICS' 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS8430252-45 is packaged in a small 16-pin TSSOP package. IC S BLOCK DIAGRAM OE Pullup PIN ASSIGNMENT OE VEE QA VCCO_A nc nc VCCA VCC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CLK_EN VEE QB nQB VCCO_B XTAL_IN XTAL_OUT VEE XTAL_IN XTAL_OUT 25MHz /5 QA OSC Phase Detector VCO 625MHz QB /4 Feedback Divider /25 nQB CLK_EN Pullup ICS8430252-45 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8430252CG-45 www.icst.com/products/hiperclocks.html REV. B DECEMBER 9, 2005 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430252-45 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Type Description Output enable pin. LVCMOS/LVTTL interface levels. See Table 3A Function Table. Negative supply pin. LVCMOS/LVTTL clock output. Output supply pin for QA output. No connect. Analog supply pin. Core supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Output supply pin for QB, nQB outputs. Differential clock outputs. LVPECL interface levels. Clock enable pin. LVCMOS/LVTTL interface levels. See Table 3B Function Table. TABLE 1. PIN DESCRIPTIONS Number 1 2, 9, 15 3 4 5, 6 7 8 10, 11 12 13, 14 16 Name OE VEE QA VCCO_A nc VCCA VCC XTAL_OUT, XTAL_IN VCCO_B nQB, QB CLK_EN Input Power Output Power Unused Power Power Input Power Output Input Pullup Pullup TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN CPD RPULLUP Input Capacitance Power Dissipation Capacitance Input Pullup Resistor VCC, VCCA, VCCO_A, VCCO_B = 3.465V Test Conditions Minimum Typical 4 10 51 Maximum Units pF pF k TABLE 3A. OE SELECT FUNCTION TABLE Input OE 0 1 Output QA Hi-Z Active TABLE 3B. CLK_EN SELECT FUNCTION TABLE Input CLK_EN 0 1 QB Low Active Outputs nQB High Active 8430252CG-45 www.icst.com/products/hiperclocks.html 2 REV. B DECEMBER 9, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430252-45 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 4.6V -0.5V to VCC + 0.5V 50mA 100mA 89C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_A, VCCO_B = 3.3V5%, TA = 0C TO 70C Symbol VCC VCCA VCCO_A, VCCO_B IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 75 8 Maximum 3.465 3.465 3.465 Units V V V mA mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = 3.3V5%, TA = 0C TO 70C Symbol VIH VIL IIH IIL VOH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current OE, CLK_EN OE, CLK_EN VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V -150 2.6 0.5 V V Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 5 Units V V Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 NOTE 1: Outputs terminated with 50 to VCCO_A/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit". TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_B = 3.3V5%, TA = 0C TO 70C Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V NOTE 1: Outputs terminated with 50 to VCCO_B - 2V. 8430252CG-45 www.icst.com/products/hiperclocks.html 3 REV. B DECEMBER 9, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430252-45 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Test Conditions Minimum Typical Fundamental 25 50 7 1 MHz pF mW Maximum Units TABLE 5. CRYSTAL CHARACTERISTICS Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant crystal. TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO_A, VCCO_B = 3.3V5%, TA = 0C TO 70C Symbol fOUT tjit(O) t R / tF odc Parameter Output Frequency Range RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time Output Duty Cycle QA QB, nQB QA QB, nQB 125MHz (1.875MHz - 20MHz) 156.25MHz (1.875MHz - 20MHz) 20% to 80% Test Conditions Minimum Typical 156.25 125 0.41 0.39 775 390 50 50 Maximum Units MHz MHz ps ps ps ps % % QA QB, nQB NOTE 1: Please refer to the Phase Noise Plots. 8430252CG-45 www.icst.com/products/hiperclocks.html 4 REV. B DECEMBER 9, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430252-45 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 156.25MHZ -10 -20 -30 -40 -50 -60 -70 10Gb Ethernet Filter 156.25MHz RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.39ps (typical) 0 NOISE POWER dBc Hz -80 -90 -100 -110 Raw Phase Noise Data -120 -130 -140 -160 -170 -180 -190 1k 10k Phase Noise Result by adding 10Gb Ethernet Filterto raw data 100k -150 1M 10M 100M OFFSET FREQUENCY (HZ) 8430252CG-45 www.icst.com/products/hiperclocks.html 5 REV. B DECEMBER 9, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430252-45 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V 1.65V5% V CC , VCCA, VCCO_B Qx SCOPE VCC , VCCA , VCCO_A SCOPE Qx LVPECL VEE nQx LVCMOS VEE -1.3V0.165V -1.65V5% 3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT Phase Noise Plot 3.3V CORE/3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT V CCO_LVCMOS Noise Power QA t PW Phase Noise Mask t PERIOD 2 f1 Offset Frequency f2 odc = t PW t PERIOD x 100% RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER nQB QB LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 80% 80% 20% t PW t PERIOD odc = t PW t PERIOD Clock Outputs 20% tR tF x 100% LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 80% VSW I N G Clock Outputs 20% tR tF 20% LVCMOS OUTPUT RISE/FALL TIME 80% LVPECL OUTPUT RISE/FALL TIME 8430252CG-45 www.icst.com/products/hiperclocks.html 6 REV. B DECEMBER 9, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430252-45 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8430252-45 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_X should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01F VCCA .01F 10F 10 FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS8430252-45 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p Figure 2. CRYSTAL INPUt INTERFACE 8430252CG-45 www.icst.com/products/hiperclocks.html 7 REV. B DECEMBER 9, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430252-45 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER AND RECOMMENDATIONS FOR UNUSED INPUT INPUTS: OUTPUT PINS OUTPUTS: LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. SELECT PINS: All select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. TERMINATION FOR 3.3V LVPECL OUTPUT designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are 3.3V Zo = 50 125 125 FOUT FIN Zo = 50 Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT FOUT FIN Zo = 50 84 84 RTT = FIGURE 3A. LVPECL OUTPUT TERMINATION FIGURE 3B. LVPECL OUTPUT TERMINATION 8430252CG-45 www.icst.com/products/hiperclocks.html 8 REV. B DECEMBER 9, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430252-45 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8430252-45. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8430252-45 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 75mA = 259.88mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 90mW Total Power_MAX (3.465V, with all outputs switching) = 259.9mW + 60mW = 319.9mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.320W * 81.8C/W = 96.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE JA FOR 16-PIN TSSOP, FORCED CONVECTION JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W 200 118.2C/W 81.8C/W 500 106.8C/W 78.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8430252CG-45 www.icst.com/products/hiperclocks.html 9 REV. B DECEMBER 9, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430252-45 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. CC * For logic high, VOUT = VOH_MAX = VCC_MAX - 0.9V (V CCO_MAX -V OH_MAX ) = 0.9V =V - 1.7V * For logic low, VOUT = V (V CCO_MAX OL_MAX CC_MAX -V OL_MAX ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V - (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= Pd_H = [(V OH_MAX CC_MAX CC_MAX OH_MAX OH_MAX CC_MAX OH_MAX L CC_MAX L [(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(V OL_MAX - (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 8430252CG-45 www.icst.com/products/hiperclocks.html 10 REV. B DECEMBER 9, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430252-45 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 8. JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W 200 118.2C/W 81.8C/W 500 106.8C/W 78.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8430252-45 is: 2070 8430252CG-45 www.icst.com/products/hiperclocks.html 11 REV. B DECEMBER 9, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430252-45 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 16 LEAD TSSOP PACKAGE OUTLINE - G SUFFIX FOR TABLE 9. PACKAGE DIMENSIONS SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum Reference Document: JEDEC Publication 95, MO-153 8430252CG-45 www.icst.com/products/hiperclocks.html 12 REV. B DECEMBER 9, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430252-45 FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8430252CG-45 30252C45 16 Lead TSSOP tube 0C to 70C ICS8430252CG-45T 30252C45 16 Lead TSSOP 2500 tape & reel 0C to 70C ICS8430252CG-45LF TBD 16 Lead "Lead-Free" TSSOP tube 0C to 70C ICS8430252CG-45LFT TBD 16 Lead "Lead-Free" TSSOP 2500 tape & reel 0C to 70C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8430252CG-45 www.icst.com/products/hiperclocks.html 13 REV. B DECEMBER 9, 2005 |
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