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IDT74ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
FEATURES:
- - - - - - - - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) VCC = 3.3V 0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range VCC = 2.5V 0.2V CMOS power levels (0.4 W typ. static) Rail-to-Rail output swing for increased noise margin Available in SOIC, SSOP and TSSOP packages
IDT74ALVC125
DESCRIPTION:
This quadruple bus buffer gate is built using advanced dual metal CMOS technology. The ALVC125 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. The ALVC125 has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
Drive Features for ALVC125: - High Output Drivers: 24mA - Suitable for heavy loads
APPLICATIONS:
* 3.3V High Speed Systems * 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1O E
1
3O E
10
1A
2
3 1Y 3A
9
8
3Y
2O E
4
4O E
13
5 2A
6 2Y 4A
12
11 4Y
INDUSTRIAL TEMPERATURE RANGE
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c 1999 Integrated Device Technology, Inc.
SEPTEMBER 2000
DSC-4635/-
IDT74ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS (1)
Symbol VTERM(2) Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND
ALVC QUAD Link
Max. - 0.5 to + 4.6 - 0.5 to VCC + 0.5 - 65 to + 150 - 50 to + 50 50 - 50 100
Unit V V C mA mA mA mA
1O E 1A 1Y 2O E 2A 2Y
1 2 3 4 5 6 7
14 13 12 SO14-1 SO14-2 11 SO14-3 10 9 8
VCC
4O E 4A 4Y 3O E 3A 3Y
VTERM(3) TSTG IOUT IIK IOK ICC ISS
GN D
SOIC/ SSOP/ TSSOP TOP VIEW
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
CAPACITANCE
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance
(TA = +25C, f = 1.0MHz)
Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
ALVC QUAD Link
I/O Port Capacitance
NOTE: 1. As applicable to the device type.
PIN DESCRIPTION
Pin Names xOE xA xY Description Output Enable Inputs (Active LOW) Data Inputs 3-State Outputs
FUNCTION TABLE
Inputs xOE L L H
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance
(each buffer)
(1)
xA H L X
Output xY H L Z
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IDT74ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current Quiescent Power Supply Current Variation VCC = 2.3V, IIN = - 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND Test Conditions VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Min. 1.7 2 -- -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- - 0.7 100 0.1 -- Max. -- -- 0.7 0.8 5 5 10 10 - 1.2 -- 10 750 A A V mV A A A V Unit V
NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3.0V VCC = 3.0V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3.0V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55
ALVC QUAD Link
Unit V
V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
c
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IDT74ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, TA = 25oC
VCC = 2.5V 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance per gate Outputs enabled Power Dissipation Capacitance per gate Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 20 3 VCC = 3.3V 0.3V Typical 30 6 Unit pF pF
SWITCHING CHARACTERISTICS
Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay xA to xY Output Enable Time xOE to xY Output Disable Time xOE to xY
(1)
VCC = 2.5V 0.2V Min. 1 1.5 1 Max. 3.1 5.4 4.1
VCC = 2.7V Min. 1 1.5 1.3 Max. 3.1 5.3 4.4
VCC = 3.3V 0.3V Min. 1.1 1.5 1.7 Max. 3 4.5 4.2 Unit ns ns ns
NOTE: 1. See test circuits and waveforms. TA = - 40C to + 85C.
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IDT74ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V 0.3V 6 2.7 1.5 300 300 50 VCC(1) = 2.7V 6 2.7 1.5 300 300 50 VCC(2)= 2.5V 0.2V Unit 2 x Vcc V Vcc Vcc / 2 150 150 30 V V mV mV pF
ALVC QUAD Link
SAM E PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
ALVC Link
TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 Pulse Generator
(1, 2)
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT SW ITCH NORMALLY CLO SED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
VLOAD Open GND
VIN D.U.T.
VOUT
RT
500 CL
ALVC Link DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
ALVC Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SET-UP, HOLD, AND RELEASE TIMES
DATA INPUT TIM ING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL tREM tSU tH VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
ALVC Link
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD
GND Open
ALVC QUAD Link
tSU
tH
OUTPUT SKEW - TSK (x)
INPUT tPLH1 tPHL1
VIH VT 0V VOH
PULSE WIDTH
LOW -HIGH-LOW PULSE tW HIGH-LOW -HIGH PULSE VT
ALVC Link
OUTPUT 1
tSK (x)
tSK (x)
VT VOL VOH
VT
OUTPUT 2 tPLH2 tPHL2
VT VOL
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
ALV C Link
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IDT74ALVC125 3.3V CMOS QUADRUPLE BUS BUFFER GATE
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
ID T XX Temp. R ange ALVC XXX Device Type XX Package
DC PY PG 125
Sm all Outline IC (SO 14-1) Shrink S m all Outline Package (S O14-2) Thin Shrink Small Outline Package (SO14-3) Quadruple Bus Buffer Gate with 3-S tate Outputs, 24m A
74
- 40C to +85C
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