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| TECHNICAL DATA IN74LV139 Dual 2-to-4 line decoder/demultiplexer; inverting The IN74LV139 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HCT139. The74LV139 is dual 2-to-4 line decoder/demultiplexer . This device has two independent decoders, each accepting two binary weighted inputs (A0a,A0b and A1a,A1b) and providing four mutually exclusive active LOW outputs (nY0 to nY3). Each decoder has an active LOW enable input (nE) When nE is HIGH, every output is forced HIGH. The enable can be used as the data input for a 1-to-4 demultiplexer application. * Optimized for Low Voltage applications:1.2 to 3.6 V * Demultiplexing capability * Two independent 2-to-4 decoders * Multifunction capability * Active LOW mutually exclusive outputs * Output capability: standard 16 1 16 1 D SUFFIX SOIC N SUFFIX PLASTIC ORDERING INFORMATION IN74LV139N Plastic IN74LV139D SOIC TA = -40 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs E H L L L L PIN 16 =VCC PIN 8 = GND A1 X L L H H A0 X L H L H Outputs Y0 Y1 Y2 Y3 H L H H H H H L H H H H H L H H H H H L H = high level (steady state) L = low level (steady state) X = don't care INTEGRAL 1 IN74LV139 MAXIMUM RATINGS Symbol VCC IIK IOK IO ICC Tstg PD * Value -0.5 to +7.0 20 50 25 50 -65 to +150 750 500 260 C VI< - 0.5 or VI> Vcc+0.5V VO< - 0.5 or VO> Vcc+0.5V -0.5A TL * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/C from 70 to 125C SOIC Package: : - 8 mW/C from 70 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO TA tr, t f DC supply voltage DC input voltage, DC output voltage Operating ambient temperature range in free air Input rise and fall times except for Schmitt-trigger inputs Vcc= 1.0 ? 2.0A Vcc= 2.0 ? 2.7A Vcc= 2.7 ? 3.6A Vcc= 3.6 ? 5.5A Parameter Min 1.2 0 0 -40 0 0 0 Max 5.5 VCC VCC +125 500 200 100 50 Unit V V V C ns/B This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. INTEGRAL 2 IN74LV139 DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions VCC, A 25C min VIH High-level input voltage 1.2 2.0 2.7 to 3.6 4.5 to 5.5 1.2 2.0 2.7 to 3.6 4.5 to 5.5 -I0=100A VIH or VIL 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 1.2 2.0 3.0 3.0 4.5 5.5 5.5 0.9 1.4 2.0 0.7 Vcc 1.85 2.55 2.85 3.45 4.35 5.35 2.48 3.70 max 0.3 0.6 0.8 0.3 Vcc Guaranteed Limit io -40C to 85C min 0.9 1.4 2.0 0.7 Vcc 1.8 2.5 2.8 3.4 4.3 5.3 2.40 3.60 max 0.3 0.6 0.8 0.3 Vcc io -40C to 125C min 0.9 1.4 2.0 0.7 Vcc 1.8 2.5 2.8 3.4 4.3 5.3 2.20 3.50 max 0.3 0.6 0.8 0.3 Vcc A Unit VIL Low -level input voltage A VOH High-level output voltage A VIH or VIL -IO=6.0 mA -IO=12.0 mA VOL Low-level output VIH or VIL voltage I0=100A B 0.15 0.15 0.15 0.33 0.40 0.1 8.0 0.2 0.2 0.2 0.40 0.55 1.0 80 0.2 0.2 0.2 0.50 0.65 1.0 160 B VIH or VIL IO=6.0 mA IO=12.0 mA II ICC Input leakage current Quiescent supply current VCC or GND VCC or GND IO=0 B - - - ieA ieA INTEGRAL 3 IN74LV139 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tLH = tHL = 2.5 nc, VIL=0B, VIH=VCC) Symbol Parameter VCC V 25C min tPLH, tPHL Propagation delay, input A to output Y (Figures 1) 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 5.0 O=+25 iN max 140 27 20 16 13 120 22 16 13 10 7.0 Guaranteed Limit io -40C to 85C min max 140 31 23 18 15 120 27 20 16 13 io -40C to 125C min max 140 39 29 23 19 120 34 25 20 16 ns Unit tPLH, t PHL Propagation delay , E to output Y (Figures 2) - - - ns CI Input capacitance pF Power dissipation capacitance (per enabled output) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC - Power dissipation capacitance per multiplexer Typical @25C,VCC=5.5 V 84 pF tr INPUT A 90% 50% 10% tf Vcc GND tr INPUT E 90% 50% 10% tf Vcc GND tPHL OUTPUT Y 90% 50% 10% tPLH OUTPUT Y tPHL 90% 50% 10% tPLH Figure 1. Switching Waveforms Figure 2. Switching Waveforms INTEGRAL 4 IN74LV139 TEST POINT DEVICE UNDER TEST OUTPUT C * L * Includes all prode and jig capacitance Figure 3. Test Circuit EXPANDED LOGIC DIAGRAM (1/2 of Device) INTEGRAL 5 IN74LV139 CHIP PAD DIAGRAM 1.70+-0.03 14 15 13 12 11 10 09 1.46 +-0.03 Pad size (mm) 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 16 01 08 Y 02 03 04 07 05 06 0 X Chip marking LV139 Location of marking (mm): left lower corner x = 0.950, y = 0.130; Thickness of chip:0.46 0.02 mm PAD LOCATION Pad Pad Name X No. 01 Ea 0.1245 02 A0a 0.1245 03 A1a 0.2920 04 Y0a 0.5480 05 Y1a 0.7520 06 Y2a 1.2830 07 Y3a 1.4845 08 GND 1.4840 09 Y3b 1.4845 10 Y2b 1.2830 11 Y1b 0.7520 12 Y0b 0.5480 13 A1b 0.2920 14 A0b 0.1245 15 Eb 0.1245 16 Vcc 0.1245 Note: Pad location is given as per passivation layer Y 0.4625 0.1290 0.1290 0.1290 0.1290 0.1290 0.1845 0.6770 1.1720 1.2265 1.2265 1.2265 1.2265 1.2265 0.8930 0.6650 INTEGRAL 6 |
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