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 IN74LV573
OCTAL D-TYPE TRANSPARENT LATCH (3-STATE)
By pinning IN74LV573 are compatible with IN74HC573A and IN74HCT573A series. Input voltage levels are compatible with stadard CMOS levels. Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS Voltage supply range from 1.2 to 5.5 V LOW input current: 1.0 ; 0.1 at = 25 Output current 8 m Latch current: not less than150 m at = 125 ESD acceptable value: not less than 2000 V as per HBM and not less than 200 V as per MM
ORDERING INFORMATION IN74LV573N Plastic DIP IN74LV573D SOIC TA = -40 to 125 C for all packages
* * * * * *
FUNCTION TABLE Inputs OE LE L H L H L L
D H L X
H X X H -HIGH voltage level L - LOW voltage level X - don't care Z - High impedance state
Outputs Q H L no change Z
PIN ASSIGNMENT
OE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LE
1
IN74LV573
ABSOLUTE MAXIMUM RATINGS Symb Parameter ol Vcc Supply voltage Iik, Input diode current Iok Io Icc IGND Tstg PD Output diode current Output current bus drivers DC Vcc or GND current for types bus driver outputs GND current Storage temperature range Power dissipation per package: DIP SO Rating -0.5 to +7.0 20 50 35 70 50 -65 to +150 750 500 Uni t V mA mA mA mA m mW Conditions VI<-0.5 V VI>Vcc>+0.5 V V0<-0.5 V VI>Vcc>+0.5 V -0.5 VNotes: Power dissipation value decreases for: DIP - 12 mWC the range from 70 to 125 SO - 8 mWC the range from 70 to 125
RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Vcc Supply voltage 1.0 VI Input voltage 0 V Output voltage 0 T Operating temperature range -40 tr,tf Input rise and fall times
Vcc= 1.0 / 2.0 V Vcc= 2.0 / 2.7 V Vcc= 2.7 / 3.6 V Vcc= 3.6 / 5.5 V - The IC function down to V = 1.0 V (input levels - VIL=0 V, VIH=Vcc); DC characterisics are guaranteed at Vcc=1.2 / 5.5 V.
Max 5.5 Vcc Vcc +125 500 200 100 50
Unit V V V o C ns/V
Conditions
2
IN74LV573
DC CHARACTERISTICS
Sym bol Parameter Conditions Limits Vc VI +85 +125 Unit -40 to +25C (V) Min Max Min Max Min Max 1.2 0.9 0.9 0.9 V 2.0 1.4 1.4 1.4 2.7 to 3.6 2.0 2.0 2.0 4.5 to 5.5 0.7 Vcc 0.7 Vcc 0.7 Vcc -1.2 0.3 0.3 0.3 V 2.0 0.6 0.6 0.6 2.7 to 3.6 0.8 0.8 0.8 4.5 to 5.5 0.3 Vcc 0.3 Vcc 0.3 Vcc 1.2 VIH IO =-100 1.05 1.0 1.0 V 2.0 or 1.85 1.8 1.8 2.7 VIL 2.55 2.5 2.5 3.6 3.45 3.4 3.4 5.5 5.35 5.3 5.3 3.0 VIH IO =-8 mA 2.48 2.40 2.20 V 4.5 or IO =-16 mA 3.70 3.60 3.50 VIL 1.2 2.0 2.7 3.6 5.5 3.0 4.5 5.5 5.5 5.5 2.7 3.6 VIH IO =100 or VIL VIH IO =8 mA or IO =16 mA VIL V or GND VIH or VIL V Io = 0 or GND VI = Vcc-0.6V 0.15 0.15 0.15 0.15 0.15 0.33 0.40 1.0 0.5 8.0 0.2 0.2 0.2 0.2 0.2 0.2 0.40 0.55 1.0 5.0 80 0.5 0.2 0.2 0.2 0.2 0.2 0.50 0.65 1.0 10.0 160 0.85 V
VIH HIGH level input voltage VIL LOW level output voltage
VOH HIGH level output voltage VOH HIGH level output voltage; BUS driver outputs VOL LOW level output voltage VOL LOW level voltage; BUS driver outputs II Input leakage current IOZ OFF-state current Icc Supply current Icc Additional supply current per input
V
mA
3
IN74LV573
AC CHARACTERISICS (CL=50 pF, RL=1 K, tLH = tHL = 2.5 ns)
Sym bol tPHL/PLH Parameter Propagation delay Dn to Qn Propagation delay LE to Qn 3-state output enable time OE to Qn 3-state outpiut disable time OE to Qn LE pulse width HIGH Conditions Vcc 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 5.0 5.5 VI = Vcc or GND -40 to +25C Min Max 150 30 23 18 15 160 34 28 20 17 140 28 22 17 14 160 31 23 20 17 100 29 21 17 15 50 15 11 8 6 40 8 8 8 8 7.0 52 Limits +85C +125C Min Max Min Max 160 170 39 49 29 36 23 29 19 24 180 190 43 53 31 34 25 31 21 26 160 170 37 48 28 35 22 28 18 23 160 170 39 48 29 36 24 29 20 24 125 150 34 41 25 30 20 24 18 21 75 100 17 20 13 15 10 12 8 10 40 40 8 8 8 8 8 8 8 8 Unit ns
tPHL/PLH
VI = Vcc or GND
ns
tPZH/PZL
VI = Vcc or GND
ns
tPHZ/PLZ
VI = Vcc or GND
ns
tW
ns
tsu
Setup time Dn to LE
ns
th
Hold time Dn to LE
ns
CI CPD
Input capacitance Power dissipation capacitance per package
=+25 =+25 VI = Vcc or GND
ns ns
4
IN74LV573
Drawing of the chip
1.9 mm
18 19 20
17
16 15
14
13 12
On-chip marking
1.51 mm
11
74LV573/574
1 10 9 2 3 4 5 6 7 8
Pad number 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20
Pads allocation Table coordinates (counted from lower left corner), mm X Y 0.128 0.545 0.128 0.229 0.330 0.120 0.576 0.120 0.738 0.120 1.054 0.120 1.216 0.120 1.466 0.120 1.682 0.314 1.682 0.533 1.682 0.839 1.682 1.108 1.422 1.274 1.149 1.274 0.971 1.274 0.811 1.274 0.633 1.274 0.360 1.274 0.128 1.108 0.128 0.854
Pad size, mm 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108
5


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