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| TECHNICAL DATA IN74HCT21A Dual 4-Input AND Gate The IN74HCT21A is high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL) . The device provide the Dual 4-input AND function. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 4.5 to 5.5 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION IN74HCT21AN Plastic IN74HCT21AD SOIC IZ74HCT21A Chip TA = -55 to 125 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT A1 B1 Y1 C1 C1 D1 A1 B1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 B2 A2 Y2 V CC D2 C2 A2 B2 Y2 C2 D2 A L PIN 14 =VCC PIN 7 = GND X X X H X = don't care B X L X X H Y1 GND FUNCTION TABLE Inputs N X X L X H D X X X L H Output Y L L L L H INTEGRAL 1 IN74HCT21A MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP** SOIC Package** Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. **Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 4.5 0 -55 0 0 0 Max 5.5 VCC +125 1000 500 400 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. INTEGRAL 2 IN74HCT21A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test Conditions VCC V Guaranteed Limit 25 C to -55C 2.0 2.0 0.8 0.8 4.42 5.42 3.98 0.09 0.09 0.26 -0.1 0.1 4.0 85 C 2.0 2.0 0.8 0.8 4.4 5.4 3.84 0.1 0.1 0.33 -1.0 1.0 40 125 C 2.0 2.0 0.8 0.8 4.4 5.4 3.70 0.1 0.1 0.4 -1.0 1.0 160 A A A V V Unit VIH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VIN=VIH or VIL IOUT = - 50 ? A VIN= VIH or VIL IOUT = - 4.0 mA 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 5.5 VIL V VOH V VOL Maximum Low-Level Output Voltage VIN= VIH or VIL IOUT = 50 ? A VIN= VIH or VIL IOUT = 4.0 mA IIL IIH ICC Maximum Low-Level Input Leakage Current Maximum High-Level Input Leakage Current Maximum Quiescent Supply Current (per Package) Maximum Additional Quiescent Supply Current on input pin VIN= 0 V VIN= VCC VIN=VCC or 0 V IOUT=0 ? A VIN=3.4 V any one input, VIN= 0 V or VCC others inputs ICCT 5.5 -55C 2.9 25C ? -125C 2.4 mA INTEGRAL 3 IN74HCT21A AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol tPHL, t PLH tTHL, t TLH CIN Parameter Maximum Propagation Delay (Figure 1) Maximum Output Transition Time (Figure 1) Maximum Input Capacitance V 4.5 4.5 5.0 Guaranteed Limit 25 C to -55C 27 15 10 85C 34 19 10 125C 41 22 10 Unit ns ns pF Power Dissipation Capacitance (Per Gate) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC TA=25C,VCC=5.0 V 50 pF tLH 0.9 0.9 V1 tHL V IH Input 0.1 V1 0.1 GND VOH tPLH 0.9 tPHL 0.9 V1 0.1 Output V1 0.1 0V tTLH V 1 = 1.3 V V I = 3.0 V t THL Figure 1. Switching Waveforms VCC VI PULSE GENERATOR RT DEVICE UNDER TEST VO Termination resistance RT - should be equal to ZOUT of pulse generators CL 50 pF Figure 2. Test Circuit INTEGRAL 4 IN74HCT21A CHIP PAD DIAGRAM IZ74HCT21A Chip marking IN74HCT21 (x=1.009; y=0.727) 12 13 1.12 0.03 11 10 09 08 07 06 14 01 02 03 04 05 1.22 0.03 Pad size 0.108 x 0.108 mm (Pad size is given as per passivation layer) Thickness of chip 0.46 0,02 mm PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 Symbol A1 B1 C1 D1 Y1 GND Y2 A2 B2 C2 D2 Vcc X 1.1165 0.2405 0.5105 0.6925 1.0065 1.0065 1.0065 1.0065 1.0065 0.6925 0.5105 0.2405 0.1165 0.1165 Y 0.3160 0.1150 0.1020 0.1150 0.1400 0.3160 0.4840 0.7040 0.8800 0.9050 0.9180 0.9050 0.6960 0.5360 INTEGRAL 5 |
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